Relevant bibliographies by topics / FPGA

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'FPGA'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 April 2025

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Journal articles on the topic "FPGA"

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Girau, Bernard. "FPNA: INTERACTION BETWEEN FPGA AND NEURAL COMPUTATION." International Journal of Neural Systems 10, no. 03 (June 2000): 243–59. http://dx.doi.org/10.1142/s0129065700000211.

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Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed in ref. 1 allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.
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LEE, HANHO, and GERALD E. SOBELMAN. "VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 17–52. http://dx.doi.org/10.1142/s021812660400126x.

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This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layout and implementation of the new digit-serial FPGA architecture. Digit-serial DSP designs using the digit-serial FPGA (DS-FPGA) are compared to those implemented on Xilinx FPGAs. We have estimated that the DS-FPGA are about 2.5~3 times more efficient in area and faster than the equivalent digit-serial DSP architectures implemented using Xilinx FPGAs.
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Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (February 26, 2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.

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The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.
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Mbongue, Joel Mandebi, Danielle Tchuinkou Kwadjo, Alex Shuping, and Christophe Bobda. "Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–31. http://dx.doi.org/10.1145/3474058.

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Cloud deployments now increasingly exploit Field-Programmable Gate Array (FPGA) accelerators as part of virtual instances. While cloud FPGAs are still essentially single-tenant, the growing demand for efficient hardware acceleration paves the way to FPGA multi-tenancy. It then becomes necessary to explore architectures, design flows, and resource management features that aim at exposing multi-tenant FPGAs to the cloud users. In this article, we discuss a hardware/software architecture that supports provisioning space-shared FPGAs in Kernel-based Virtual Machine (KVM) clouds. The proposed hardware/software architecture introduces an FPGA organization that improves hardware consolidation and support hardware elasticity with minimal data movement overhead. It also relies on VirtIO to decrease communication latency between hardware and software domains. Prototyping the proposed architecture with a Virtex UltraScale+ FPGA demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization, which is one of the goals of virtualization. Overall, our FPGA design achieved about 2× higher maximum frequency than the state of the art and a bandwidth reaching up to 28 Gbps on 32-bit data width.
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Yu, Hoyoung, Hansol Lee, Sangil Lee, Youngmin Kim, and Hyung-Min Lee. "Recent Advances in FPGA Reverse Engineering." Electronics 7, no. 10 (October 12, 2018): 246. http://dx.doi.org/10.3390/electronics7100246.

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In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products.
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krishna, Mr P. V. Murali, and Kantumajji Navyasri. "ACCELERATING HIGH-PERFORMANCE VOLTAGE SOURCE INVERTER PROTOTYPING WITH FPGA IMPLEMENTATION." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (December 30, 2023): 1–10. http://dx.doi.org/10.55041/ijsrem27818.

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This paper highlights the advantages of FPGA-based rapid prototyping as a powerful tool for accelerating the development cycle of high-performance Voltage Source Inverters. By providing a flexible and efficient platform for algorithm testing, hardware evaluation, and performance optimization, it contributes to advancements in power electronics and facilitates the deployment of robust VSIs in diverse application domains. Through extensive experimentation, we demonstrate the effectiveness of the FPGA-based rapid prototyping platform in achieving high- performance VSI control. The FPGA's real-time capabilities facilitate swift algorithm development and testing, ensuring robustness and reliability. Moreover, the platform supports real-time hardware-level fault analysis and mitigation strategies, enhancing the overall resilience of the VSI. This paper presents an innovative approach utilizing Field- Programmable Gate Arrays (FPGAs) for rapid prototyping of high-performance VSIs. This abstract outlines the core objectives, methods, and potential contributions of a project aimed at expediting the development of high-performance Voltage Source Invertersthrough FPGA-based prototyping. KEYWORDS FPGA (Field-Programmable Gate Array), Voltage Source Inverter, High-Performance Prototyping, Power Electronics, Hardware-in-the-Loop (HIL), Rapid Prototyping, Real-Time Simulation, Control Algorithms, Digital Signal Processing (DSP),Power Conversion, Description Language (HDL),System-on-Chip (SoC),Field-Programmable Analog Array (FPAA),Power Quality, Grid Integration
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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>
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Sauvage, Laurent, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, and Yves Mathieu. "Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/375245.

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FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.
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Zhao, Tianrun. "FPGA-Based Machine Learning: Platforms, Applications, Design Considerations, Challenges, and Future Directions." Highlights in Science, Engineering and Technology 62 (July 27, 2023): 96–101. http://dx.doi.org/10.54097/hset.v62i.10430.

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Field-Programmable Gate Arrays (FPGAs) have emerged as a promising platform for accelerating machine learning tasks due to their high parallelism, low latency, and hardware customization ability. In this paper, the authors provide an overview of popular FPGA platforms for machine learning and compare the tradeoffs among FPGAs, GPUs, and CPUs for machine learning. The authors also present specific applications of machine learning based on FPGAs, including those in autonomous driving and healthcare. Additionally, the paper explores FPGA design considerations, such as architecture, resource utilization, and power consumption. Nonetheless, obstacles persist in the realm of FPGA-based machine learning that require attention. Identifying the ideal balance between adaptability and performance, considering factors such as space, energy usage, and latency, is still challenging. As the capabilities of FPGAs expand, there is a significant need for devices that have a smaller footprint, reduced power consumption, and minimized delays. The paper emphasizes the necessity of ongoing research in the field of FPGA-based machine learning to address these issues and continue enhancing the performance and effectiveness of machine learning systems.
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Zhang, Qian Li, Fang Yu, Yan Li, Ming Li, Yan Zhao, and Liang Chen. "Architecture-Specific Mapping Tool for SOI-Based FPGA." Advanced Materials Research 159 (December 2010): 438–43. http://dx.doi.org/10.4028/www.scientific.net/amr.159.438.

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This paper addresses several key issues in the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process, with particular emphasis on FPGA architecture interrelated mapping step and packing method for CAD tool. Considering the routability and testability of the FPGA and the CAD tool, the algorithm combines the FPGA structure with the object netlist, mapping the basic elements into basic building blocks in order to reduce the resource usage. The result is proven in extensive test circuits used in our FPGA design.
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Dissertations / Theses on the topic "FPGA"

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Carrick, Matthew. "Logical Representation of FPGAs and FPGA Circuits within the SCA." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/33858.

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A very basic engineering tradeoff is performance versus flexibility and this design choice must be made when developing a software radio. Hardware devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) all provide a designer with choices along the performance versus flexibility spectrum. The designer must choose a combination of GPP, DSP, FPGA and ASIC devices to balance the needs of performance versus flexibility. The Software Communications Architecture (SCA) is a specification for a software radio architecture produced by the Joint Program Executive Office (JPEO) Joint Tactical Radio System (JTRS). The 2.2 revision of the SCA only implies support for GPPs, with no specified support for additional devices such as FPGAs. However, FPGA integration within the scope of the SCA is still possible. The integration of an additional processing hardware device other than a GPP requires the ability to logically represent the device within the Core Framework. This representation is implemented within the OSSIE Core Framework, an open source implementation of the SCA. The representation requires the support of multiple implementations of signal processing components within the framework, a simple component deployment model, and the abstraction of the FPGA interactions into a software component.
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Lavin, Christopher Michael. "Using Hard Macros to Accelerate FPGA Compilation for Xilinx FPGAs." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2933.

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Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.
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Krčma, Martin. "Akcelerace neuronových sítí v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-235409.

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This thesis deals with a training of the FPNN structures. It focuses on the ways of direct conversion of the pretrained arti cial neural networks to FPNNs. This is useful when original training data set is not reachable.
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Tianxu, Yue. "Convolutional Neural Network FPGA-accelerator on Intel DE10-Standard FPGA." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-178174.

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Convolutional neural networks (CNNs) have been extensively used in many aspects, such as face and speech recognition, image searching and classification, and automatic drive. Hence, CNN accelerators have become a trending research. Generally, Graphics processing units (GPUs) are widely applied in CNNaccelerators. However, Field-programmable gate arrays (FPGAs) have higher energy and resource efficiency compared with GPUs, moreover, high-level synthesis tools based on Open Computing Language (OpenCL) can reduce the verification and implementation period for FPGAs. In this project, PipeCNN[1] is implemented on Intel DE10-Standard FPGA. This OpenCL design acceleratesAlexnet through the interaction between Advanced RISC Machine (ARM) and FPGA. Then, PipeCNN optimization based on memory read and convolution is analyzed and discussed.
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Simmler, Harald C. "Preemptive multitasking auf FPGA-Prozessoren : ein Betriebssystem für FPGA-Prozessoren /." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9460961.

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Mou, Pedro Antonio. "General purpose bioelectric signals acquisition platform combining FPGA and FPAA = 結合FPGA及FPAA的通用生物電信號採集平台." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2182896.

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Ivebrink, Pontus, and Peter Ytterström. "Frekvensuppdelning med FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56238.

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Examensarbetets syfte var att skapa ett frekvensspektrum för ljud. För att representera detta frekvensspektrum används staplar av lysdioder. Systemet implementeras på ett Altera DE2 utvecklingskort. Olika sätt för att skapa dessa frekvensuppdelningar har testats och olika metoder för att lösa dessa har också testats.

Den slutliga implementeringen består av en filterbank som utnyttjar nersampling för att återanvända filter och sänka ordningen på dessa. Det största problemet var att få plats med allt på den FPGA som användes. Genom att byta till en lite mer komplicerad men effektivare filterstruktur så löstes detta problem och vi fick även gott om utrymme över.

Manualer och datablad har inte alltid varit lätta att tolka och ibland har andra metoder använts än de som beskrivs i dessa manualer med tips från support forum och handledare. Det finns vissa förbättringar att göra och vissa saker skulle kunnat göras annorlunda för att spara resurser med ett lite sämre resultat. När projektet var klart hade alla krav som ställts uppfyllts.

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Gravdal, Fredrik. "Selvrekonfigurering av FPGA." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10356.

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Den tradisjonelle designflyten i utviklingen av mikroelektronikk forutsetter at alle utviklingsaktivitetene er unnagjort pre-kjøretid, og at ferdiggenererte, udelelige konfigurasjonsfiler brukes for å konfigurere brikkene. De fleste systemer som benytter FPGA-teknologi i dag har derfor et begrenset utvalg forhåndsgenererte konfigurasjoner å velge mellom for å løse en oppgave. Ideen bak denne oppgaven er ønsket om å lage et rekonfigurerbart system der det er FPGA-en selv som står for rekonfigureringen uten noe behov for ekstern tilkobling eller manipulasjon. Dette for å drive den innovative utviklingen av dynamiske hardwaresystemer. Systemet er laget på en Suzakuplattform med en Spartan-3 XC3S1000 FPGA fra Xilinx. Det er utviklet to program, CLBRead og CLBWrite som kjøres på en microblazeprosessor. CLBRead kan lese en CLB-struktur med forskjellig størrelse, der en enkelt CLB er den minste oppdelingen, til fil. En CLB-struktur kan leses ut fra flash på FPGA-kortet, eller fra en bitstrømsfil på en PC. CLBWrite skriver en filstruktur generert av CLBRead til flashområdet der FPGA-konfigurasjonene ligger. Ved oppstart av FPGA-en vil det nye oppsettet konfigureres opp. Systemet som er utviklet gjør at FPGA-en kan rekonfigureres helt uten behov for ekstern tilkobling eller manipulasjon. Det er FPGA-en selv som gjør hele jobben. Forskjellige moduler kan lagres og lastes inn ved behov. Systemer er testet med to moduler, en OG-port og en ELLER-port, der disse kan byttes med hverandre og endringene kan måles med et digitalt multimeter.

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Paananen, V. (Ville). "Neuroverkkojen FPGA-toteutus." Bachelor's thesis, University of Oulu, 2018. http://urn.fi/URN:NBN:fi:oulu-201805312377.

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Tässä työssä esitellään kaksi erilaista neuroverkkoa, monikerrosperceptron ja konvolutionaalinen neuroverkko, ja tutkitaan niiden toteutettavuutta käyttämällä FPGA-piirirakennetta. Työssä kuvataan neuroverkkojen taustaa ja esitellään niiden toimintaa ja suunnittelua ohjaavia parametreja. Lisäksi tutkitaan FPGA-piirien eduja ja haasteita. Työ tehtiin kirjallisuuskatsauksena käyttämällä lähteinä ajankohtaisten neuroverkkotutkimusten tuloksia
This work presents two different neural networks, multi-layer-perceptron and convolutional neural network and their FPGA-implementation is researched. The work describes the background for neural networks and presents their operation and the parameters that guide their design. The benefits and challenges of FPGA-circuits are also researched. The work was done as a literature review using the the contemporary neural network research
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Малахова, О. Ю., І. О. Шевцов, and В. С. Чумак. "Електроміограф на FPGA." Thesis, ХНУВС, 2022. https://openarchive.nure.ua/handle/document/20336.

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Електроміографія є методом дослідження біопотенціалів, що утворюються в скелетних м’язах людини і тварин під час збудження м’язових волокон. Електроміографічні дослідження широко використовуються в дослідженнях рухових розладів в ортопедії та протезуванні, фізіології роботи та руху, аналізу втоми і рухових навичок, що також носить загальну назву інженерної психології, а також у передових дослідження нервової активності, психофізіологічних дослідженнях вікових особливостей, тому, грамотне призначення ЕМГобстеження дозволяє отримати максимум інформації за мінімальних витрат часу, що сприяє великому різноманіттю приладів ЕМГ – електроміографів, які відрізняються функціями, розмірами і технічними характеристиками
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Books on the topic "FPGA"

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Simpson, Philip. FPGA Design. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0.

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Simpson, Philip Andrew. FPGA Design. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7.

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Instruments, Texas. FPGA applications handbook. [USA]: Texas Instruments, 1994.

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Instruments, Texas. FPGA: Applications handbook. [Dallas, Tex.]: Texas Instruments, 1993.

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Instruments, Texas. FPGA applications handbook. [USA]: Texas Instruments, 1993.

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David E. Van den Bout. FPGA workout: Beginning exercises with the Intel FLEXlogic FPGA. Apex, N.C: X Engineering Software Systems Corp., 1994.

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Pang, Aiken, and Peter Membrey. Beginning FPGA: Programming Metal. Berkeley, CA: Apress, 2017. http://dx.doi.org/10.1007/978-1-4302-6248-0.

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Skliarova, Iouliia, and Valery Sklyarov. FPGA-BASED Hardware Accelerators. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-20721-2.

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Corporation, Actel. The FPGA design guide. Sunnyvale, CA: Actel Corporation, 1991.

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Lukats, Antti. Antti-Brain Vol I. USA: Smashwords, 2021.

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Book chapters on the topic "FPGA"

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Reinders, James, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, and Xinmin Tian. "Programming for FPGAs." In Data Parallel C++, 451–502. Berkeley, CA: Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9691-2_17.

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AbstractChapter 17 raises considerations to keep in mind when targeting FPGAs using C++ with SYCL. It describes mappings from device code to FPGA devices, how FPGA software and hardware execute a SYCL application, and tips and techniques to keep in mind when writing and optimizing parallel kernels for an FPGA.
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Simpson, Philip. "Best Practices for Successful FPGA Design." In FPGA Design, 1–3. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_1.

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Simpson, Philip. "The Hardware to Software Interface." In FPGA Design, 91–94. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_10.

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Simpson, Philip. "Functional Verification." In FPGA Design, 95–106. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_11.

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Simpson, Philip. "Timing Closure." In FPGA Design, 107–32. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_12.

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Simpson, Philip. "In-System Debug." In FPGA Design, 133–44. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_13.

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Simpson, Philip. "Design Sign-Off." In FPGA Design, 145–46. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_14.

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Simpson, Philip. "Project Management." In FPGA Design, 5–7. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_2.

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Simpson, Philip. "Design Specification." In FPGA Design, 9–13. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_3.

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Simpson, Philip. "Resource Scoping." In FPGA Design, 15–21. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_4.

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Conference papers on the topic "FPGA"

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Bragança, Lucas, Jeronimo Penha, Michael Canesche, Dener Ribeiro, José Augusto M. Nacif, and Ricardo Ferreira. "An Open-Source Cloud-FPGA Gene Regulatory Accelerator." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2021. http://dx.doi.org/10.5753/wscad.2021.18527.

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FPGAs are suitable to speed up gene regulatory network (GRN) algorithms with high throughput and energy efficiency. In addition, virtualizing FPGA using hardware generators and cloud resources increases the computing ability to achieve on-demand accelerations across multiple users. Recently, Amazon AWS provides high-performance Cloud's FPGAs. This work proposes an open source accelerator generator for Boolean gene regulatory networks. The generator automatically creates all hardware and software pieces from a high-level GRN description. We evaluate the accelerator performance and cost for CPU, GPU, and Cloud FPGA implementations by considering six GRN models proposed in the literature. As a result, the FPGA accelerator is at least 12x faster than the best GPU accelerator. Furthermore, the FPGA reaches the best performance per dollar in cloud services, at least 5x better than the best GPU accelerator.
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Caponetto, R., G. Dongola, and A. Gallo. "FPGA Implementation of Self-Tuning Regulators." In ASME 2009 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/detc2009-87351.

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The paper presents an hardware realization of a self-tuning control system implemented on a development board, Field Programmable Gate Arrays (FPGAs) based, able to adapt the control rules for an uncertain and disturbance affected plant. In the paper the on-line estimation of the plant parameters is realized by applying the “Recursive Least Squares with exponential forgetting” method and the control law is designed by using the “Pole Placement” procedure. These algorithms require a greater computational load, justifying therefore the FPGA utilization, especially in the case of high speed variation of the plant parameters. In order to test the FPGA hardware implementation of Self-Tuning regulators the process is implemented on DSPACE and the parameter variations are produced via an Human Machine Interface (HMI) console. Besides, thanks to the reprogrammability of FPGAs, these devices allow the use of such adaptive control systems in hazardous area.
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Silva, Lucas B. da, Jeronimo Costa Penha, Dener V. Ribeiro, Alysson Silva, José Augusto M. Nacif, and Ricardo Ferreira. "HPyC-FPGA - Integração de Aceleradores em FPGA de Alto Desempenho com Python para Jupyter Notebooks." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2022. http://dx.doi.org/10.5753/wscad.2022.226383.

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O desenvolvimento de aceleradores em FPGAs (Field Programmable Gates Arrays) ainda é um desafio. Recentemente, o ambiente PYNQ da Xilinx possibilitou a integração de código Python com aceleradores em FPGA. A maioria dos exemplos está voltada para placas de prototipação utilizadas no desenvolvimento de aplicações embarcadas. Este artigo apresenta o algoritmo K-means de aprendizado de máquina não supervisionado como estudo de caso. A principal contribuição deste trabalho é o encapsulamento de 3 aceleradores acoplados com PYNQ usando o ambiente Jupyter Notebook. A avaliação foi realizada em uma máquina de alto desempenho utilizando um FPGA Alveo U55C com memória HBM (High Bandwidth Memory). Os resultados são promissores, além de mostrar as facilidades de uso do FPGA de forma encapsulada, o ganho de desempenho foi de uma a duas ordens de grandezas em comparação a um sistema com dois processadores Xeon(R) Silver 4210R com 10 núcleos cada, executando a etapa de classificação do algoritmo K-means.
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Lei, Shuliang, Andy Provenza, Alan Palazzolo, and Raymond Beach. "Implementation of Magnetic Suspension Control With FPGA." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-44057.

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This paper presents a methodology for an alternative implementation of DSP-based controllers typically used for magnetic bearing (MB) levitation and control on FPGA hardware. The approach takes s-domain transfer functions of the controller components and discretizes them using z-transform conversions into discrete time domain expressions. These expressions, which are essentially digital IIR filters, are synthesized and implemented to obtain downloadable bit-stream using Xilinx ISE software packages. In the example presented, the executable code was sent to configure the two FPGAs for control. An equivalent PD with notch filter FPGA-based controller was constructed to replicate an existing two-axis DSP controller used to control a radial magnetic bearing on a vertical rotor in the Dynamic Spin Rig Facility at NASA Glenn Research Center. The FPGA controller was successfully demonstrated on the NASA hardware.
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Jorge, Carlos Antonio, Alexandre Nery, and Alba Melo. "Uma implementação do algoritmo LCS em FPGA usando High-Level Synthesis." In XX Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2019. http://dx.doi.org/10.5753/wscad.2019.8679.

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Este trabalho apresenta uma implementação do algoritmo Longest Common Subsequence (LCS) para comparação de duas sequências biológicas utilizando linguagem de alto nı́vel High Level Synthesis (HLS) para FPGAs. Foram comparados resultados entre a execução em uma CPU Intel Core i73770 e uma FPGA Xilinx® ADM-PCIE-KU3 que possui uma Xilinx Kintex® UltraScale XCKU060-2. Os resultados mostraram que a implementação em CPU consumiu 6,8x mais energia em relação à FPGA.
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Guerra, Victor S., and Gabriel L. Nazar. "A Partition-Aware VNF Placement Methodology for FPGA-Equipped NFVIs." In Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos, 1078–91. Sociedade Brasileira de Computação, 2024. http://dx.doi.org/10.5753/sbrc.2024.1545.

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In the context of Network Function Virtualization (NFV), Field Programmable Gate Arrays (FPGAs) can be used to reduce bottlenecks introduced by the substitution of dedicated hardware middleboxes by virtualized implementations. The problem of placing Virtualized Network Functions (VNFs) on FPGA-equipped NFV infrastructures, however, imposes additional challenges that require an accurate modeling of the FPGA fabric. More specifically, simultaneous sharing of the FPGA requires careful partitioning of its resources into fixed regions that can be dynamically reconfigure and to which functions can be mapped. In this work, we will demonstrate that accurate modeling of the FPGA partitions into the placement solution is crucial to achieve solutions that are guaranteed to be viable. Experimental results obtained through two Integer Liner Programming models will be used to demonstrate that partition awareness can avoid invalid solutions caused by overestimation of the device capabilities, with a small impact on the number of allocated user requisitions.
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Babeshko, Eugene, Ievgenii Bakhmach, Vyacheslav Kharchenko, Eugene Ruchkov, and Oleksandr Siora. "Operating Reliability Assessment of FPGA-Based NPP I&C Systems: Approach, Technique and Implementation." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-66862.

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Operating reliability assessment of instrumentation and control systems (I&Cs) is always one of the most important activities, especially for critical domains like nuclear power plants (NPPs). Intensive use of relatively new technologies like field programmable gate arrays (FPGAs) in I&C which appear in upgrades and in newly built NPPs makes task to develop and validate advanced operating reliability assessment methods that consider specific technology features very topical. Increased integration densities make the reliability of integrated circuits the most crucial point in modern NPP I&Cs. Moreover, FPGAs differ in some significant ways from other integrated circuits: they are shipped as blanks and are very dependent on design configured into them. Furthermore, FPGA design could be changed during planned NPP outage for different reasons. Considering all possible failure modes of FPGA-based NPP I&C at design stage is a quite challenging task. Therefore, operating reliability assessment is one of the most preferable ways to perform comprehensive analysis of FPGA-based NPP I&Cs. This paper summarizes our experience on operating reliability analysis of FPGA based NPP I&Cs.
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Leite, Gustavo, Alexandro Baldassin, Guido Araujo, and José Nelson Amaral. "Performance Evaluation of Compiler Optimizations in FPGA Accelerators." In XX Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2019. http://dx.doi.org/10.5753/wscad.2019.8681.

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With the increasing power wall in microprocessor design, engineers shifted their attention to heterogeneous architectures, wherein several classes of devices are used for computation. Among them are FPGAs which offer comparable performance to CPUs while consuming only a fraction of energy. Despite the increasing interest in these devices, programmability and performance engineering in FPGAs remain hard. This work presents an evaluation of the most prominent code transformations targeting FPGAs. More specifically, it studies the performance effect of unrolling loops, replicating compute units and transferring data using DMA in a matrix multiplication OpenCL kernel through an Intel® FPGA. The results indicate that these optimizations can achieve speedups up to 3.78× for a matrix multiplication application, and 412.5× speedup in data transfer.
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Jiang, Cindy X., Tom T. Hartley, and Joan E. Carletta. "High Performance Low Cost Implementation of FPGA-Based Fractional-Order Operators." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84796.

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Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. As an illustration, the fundamental operators to a real power is approximated via the binomial expansion of the backward difference. The resulting high-order FIR filter is implemented in a pipelined multiplierless architecture on a low-cost Spartan-3 FPGA. Unlike common digital implementations in which all filter coefficients have the same word length, this approach exploits variable word length for each coefficient. Our system requires twenty percent less hardware than a system of comparable quality generated by Xilinx’s System Generator on its most area-efficient multiplierless setting. The work shows an effective way to implement a high quality, high throughput approximation to a fractional-order system, while maintaining less cost than traditional FPGA-based designs.
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Medeiros, V. W. C., R. C. F. Rocha, A. P. A. Ferreira, J. C. B. L. Correia, J. P. F. Barbosa, A. G. Silva-Filho, M. E. Lima, Rodrigo Gandra, and Ricardo Bragança. "FPGA-based Accelerator to Speed-up Seismic Applications." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2011. http://dx.doi.org/10.5753/wscad.2011.17269.

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Hardware accelerators such as GPGPUs and FPGAs have been used as an alternative to the conventional CPU in scientific computing applications and have shown significant performance improvements. In this context, this work presents an FPGA-based solution that explores efficiently the reuse of data and parallelization in both space and time domains for the first computational stage of the RTM (Reverse Time Migration) algorithm, the seismic modeling. We also implemented the same algorithm for CPU architectures and GPGPU and our results demonstrate that the FPGA-based approach can be a viable solution to improve performance. Experimental results show a speedup of 1.668 times compared with GPGPU and 25.79 times compared to CPU. Results were evaluated with the Marmousi velocity model, considering the same parameters in all approaches.
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Reports on the topic "FPGA"

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Brotz, Jay Kristoffer, Ross W. Hymel, Ratish J. Punnoose, Tom Mannos, Neil Grant, and Neil Evans. FPGA Authentication Methods. Office of Scientific and Technical Information (OSTI), May 2017. http://dx.doi.org/10.2172/1367230.

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Kou, Stephen, Jens Palsberg, and Jeffrey Brooks. From OO to FPGA :. Office of Scientific and Technical Information (OSTI), September 2012. http://dx.doi.org/10.2172/1096949.

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Hormigo Jiménez, Marco, and Fco Javier Hormigo Aguilar. Aceleración del DTW en FPGA. Fundación Avanza, May 2023. http://dx.doi.org/10.60096/fundacionavanza/2282022.

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El DTW es un algoritmo que compara series temporales. En este articulo, diseñaremos un circuito digital en una FPGA para intentar reducir su largo tiempo de computación. Consiguiendo que el diseño calcule mas de 9000 cálculos por segundo.
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Jin, Zheming, Kazutomo Yoshii, Hal Finkel, and Franck Cappello. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL. Office of Scientific and Technical Information (OSTI), May 2017. http://dx.doi.org/10.2172/1372106.

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Gray, Darius. FPGA Trigger System to Run Klystrons. Office of Scientific and Technical Information (OSTI), August 2010. http://dx.doi.org/10.2172/992940.

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Merkel, Justin. Quantized Recurrent Neural Network on FPGA. Ames (Iowa): Iowa State University, May 2022. http://dx.doi.org/10.31274/cc-20240624-1184.

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Olsen, Jamieson, Tiehui Ted Liu, Jim Hoff, Zhen Hu, Jim Yuan Wu, and Zijun Xu. An FPGA-based Pattern Recognition Associative Memory. Office of Scientific and Technical Information (OSTI), July 2018. http://dx.doi.org/10.2172/1480099.

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Hill, Jeffrey O. The LANSCE FPGA Embedded Signal Processing Framework. Office of Scientific and Technical Information (OSTI), October 2013. http://dx.doi.org/10.2172/1095850.

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Eddy, N., and O. Lysenko. Wire Position Monitoring with FPGA based Electronics. Office of Scientific and Technical Information (OSTI), January 2009. http://dx.doi.org/10.2172/971001.

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Hutchings, Brad, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, and Mike Rytting. A CAD Suite for High-Performance FPGA Design. Fort Belvoir, VA: Defense Technical Information Center, January 1999. http://dx.doi.org/10.21236/ada450475.

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