Academic literature on the topic 'FPGA application in Power system'

Rapid and continuous evolution in telecommunication standards and applications has increased the demand for a platform with high parallelization capability, high flexibility, and low power consumption. FPGAs are known platforms that can provide all these requirements. However, the evaluation of approaches, architectures, and scheduling policies in this era requires a suitable and open-source benchmark suite that runs on FPGA. This paper harnesses high-level synthesis tools to implement high-performance, resource-efficient, and easy-maintenance kernels for FPGAs. We provide various implementations of each kernel of PHY-Bench and WiBench, which are the most well-known benchmark suites for telecommunication applications on FPGAs. We analyze the execution time and power consumption of different kernels on ARM processors and FPGA. We have made all sources and documentation public for the benefit of the research community. The codes are flexible, and all kernels can easily be regenerated for different sizes. The results show that the FPGA can increase the speed by up to 19.4 times. Furthermore, we show that the power consumption of the FPGA can be reduced by up to 45% by partially reconfiguring a kernel that fits the size of the input data instead of using a large kernel that supports all inputs. We also show that partial reconfiguration can improve the execution time for processing a sub-frame in the uplink application by 33% compared to an FPGA-based approach without partial reconfiguration.

With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded. Current applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable logic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration. But the dimension introduced in the design of these systems requires more abstraction to manage their complexity and efficient models to provide reliable preliminary estimations. While classical multiprocessor systems can be modeled without difficulty, the use of partial run-time reconfiguration in heterogeneous flexible system-on-chips is generally not covered. The contribution of this paper is to address this with an extension of the AADL language able to model the reconfigurable logic, possibly considering dynamic reconfiguration and power consumption requirements. The proposed AADL model is divided into three levels to provide a generic and hierarchical approach separating the static and dynamic parts of current FPGAs. These levels are exposed in detail and illustrated on a concrete example of FPGA device. The design space exploration of an application deployment using this model is also presented.

In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board. This work presents an FPGA controlled system that takes ladder diagram (LD) control for a PLC and converts this control to Verilog HDL and programs an FPGA such that the FPGA prototyping board is used to control a real industrial application. We explore this approach since FPGA implementation of LD control could significantly reduce the cost of implementing these controllers with other potential advantages such as the improved granularity of timing control from milliseconds to nanoseconds, additional available pins for inputs and outputs far exceeding that of microprocessors, and lower power consumption for control. In this work, we provide details and descriptions of our industrial system (ALD), the LD control of this system and its implementation, our software flow to convert LDs to Verilog HDL, and our FPGA prototype board design to replace the existing electronic controller. We show how our LD-Verilog HDL converter in conjunction with FPGAs matches a PLC and demonstrate some of the benefits of using an FPGA.

Modbus bus has been widely used in the power system. For the seamless integrated realization of enterprise control and management information, the remote interaction of Modbus bus meter data is needed. This design is based on the problems involved in the process of practical power system application. Using FPGA EP2C35F672 hardware platform, UART, DM9000A external chips are extended to complete remote operation and monitoring of Modbus equipment. The field bus and the Internet network interconnection can be realized, so the decentralization and open for control system are improved. The design can be used to rebuild the existing power field bus network. This design has good prospects and practical value.