Relevant bibliographies by topics / FPGA-Based systems

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'FPGA-Based systems'

Author: Grafiati
Published: 9 March 2023

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Journal articles on the topic "FPGA-Based systems"

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MELNYK, A., and V. MELNYK. "Self-Configurable FPGA-Based Computer Systems." Advances in Electrical and Computer Engineering 13, no. 2 (2013): 33–38. http://dx.doi.org/10.4316/aece.2013.02005.

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Sahar, Abdelhedi. "Fall Detection FPGA-Based Systems: A Survey." International Journal of Automation and Smart Technology 6, no. 4 (December 1, 2016): 191–202. http://dx.doi.org/10.5875/ausmt.v6i4.1105.

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Kassas, Zaher M. "Methodologies for Implementing FPGA-Based Control Systems." IFAC Proceedings Volumes 44, no. 1 (January 2011): 9911–16. http://dx.doi.org/10.3182/20110828-6-it-1002.00783.

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Ivanov, V. K., and E. V. Nosov. "Serial communication protocol for FPGA-based systems." Journal of Physics: Conference Series 1326 (October 2019): 012044. http://dx.doi.org/10.1088/1742-6596/1326/1/012044.

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SKLYAROV, V. "HARDWARE/SOFTWARE MODELING OF FPGA-BASED SYSTEMS." Parallel Algorithms and Applications 17, no. 1 (January 2002): 19–39. http://dx.doi.org/10.1080/10637190208941432.

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Montone, A., M. D. Santambrogio, F. Redaelli, and D. Sciuto. "Floorplacement for Partial Reconfigurable FPGA-Based Systems." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/483681.

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We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based onexternal wirelength. Our work aims at identifying groups ofReconfigurable Functional Unitsthat are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).
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Huffmire, Ted, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy Levin, Thuy D. Nguyen, and Cynthia Irvine. "Managing Security in FPGA-Based Embedded Systems." IEEE Design & Test of Computers 25, no. 6 (November 2008): 590–98. http://dx.doi.org/10.1109/mdt.2008.166.

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Dandalis, A., and V. K. Prasanna. "Configuration compression for FPGA-based embedded systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 12 (December 2005): 1394–98. http://dx.doi.org/10.1109/tvlsi.2005.862721.

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Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. "Dynamic Reliability Management for FPGA-Based Systems." International Journal of Reconfigurable Computing 2020 (June 13, 2020): 1–19. http://dx.doi.org/10.1155/2020/2808710.

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Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.
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Chen, Fu Long, Zhao Xia Zhu, and Xiao Ya Fan. "FPGA-Based In-Circuit Verification of Digital Systems." Advanced Materials Research 187 (February 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.
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Dissertations / Theses on the topic "FPGA-Based systems"

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Stavström, Marcus. "Evaluation of FPGA based Test Systems." Thesis, Linköpings universitet, Datorteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-119094.

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This master thesis report covers an investigation of how FPGA based hardware can be used to create customizable measurement instruments, for test of electrical equipment in JAS 39 Gripen. The investigation is done at Saab Support and Services in Arboga. Electrical equipment are gradually replacing functions, which previously have been obtained by other systems, in safety critical environments. Since the functions are safety critical, they require regular testing in order to verify proper operation. The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is an example of such system. Proper operation of the avionics in it are essential in order to maintain flying safety. There already exist systems today that can verify the functionality of electronics in JAS 39 Gripen. However, there are a number of scenarios where those test systems are somewhat inflexible. More flexible test systems are often desired. This flexibility can be obtained by using congurable hardware, suggestively with FPGAs. This approach is investigated in this master thesis.
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Lepistö, Niklas. "FPGA based architectures for embedded video systems /." Sundsvall : Departement of Information Technology and Media, Mid Sweden University, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-188.

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Devic, Florian. "Securing embedded systems based on FPGA technologies." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20107.

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Les systèmes embarqués peuvent contenir des données sensibles. Elles sont généralement échangées en clair entre le système sur puces et la mémoire, mais aussi en interne. Cela constitue un point faible: un attaquant peut observer cet échange et récupérer des informations ou insérer du code malveillant. L'objectif de la thèse est de fournir une solution dédiée et adaptée à ces problèmes en considérant l'intégralité de la durée de vie du système embarqué (démarrage, mises à jour et exécution) et l'intégralité des données (bitstream du FPGA, noyau du système d'exploitation, code et données critiques). En outre, il est nécessaire d'optimiser les performances des mécanismes matériels de sécurité introduits afin de correspondre aux attentes des systèmes embarqués. Cette thèse se distingue en proposant des solutions innovantes et adaptées au monde des FPGAs
Embedded systems may contain sensitive data. They are usually exchanged in plaintext between the system on chips and the memory, but also internally. This is a weakness: an attacker can spy this exchange and retrieve information or insert malicious code. The aim of the thesis is to provide a dedicated and suitable solution for these problems by considering the entire lifecycle of the embedded system (boot, updates and execution) and all the data (FPGA bitstream, operating system kernel, critical data and code). Furthermore, it is necessary to optimize the performance of hardware security mechanisms introduced to match the expectations of embedded systems. This thesis is distinguished by offering innovative and suitable solutions for the world of FPGAs
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Hauff, Martin Anthony, and marty@extendabilities com au. "Compiler Directed Codesign for FPGA-based Embedded Systems." RMIT University. Electrical and Computer Engineering, 2008. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20081202.141333.

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As embedded systems designers increasingly turn to programmable logic technologies in place of off-the-shelf microprocessors, there is a growing interest in the development of optimised custom processing cores that can be designed on a per-application basis. FPGAs blur the traditional distinction between hardware and software and offer the promise of application specific hardware acceleration. But realizing this in a general sense requires a significant departure from traditional embedded systems development flows. Whereas off-the-shelf processors have a fixed architecture, the same cannot be said of purpose-built FPGA-based processors. With this freedom comes the challenge of empirically determining the optimal boundary point between hardware and software. The fluidity of the hardware/software partition also poses an interesting challenge for compiler developers. This thesis presents a tool and methodology that addresses these codesign challenges in a new way. Described as 'compiler-directed codesign', it makes use of a suitably modified compiler to help direct the development of a custom processor core on a per-application basis. By exposing the compiler's internal representation of a compiled target program, visibility into those instructions, and hardware resources, that are most sought after by the compiler can be gained. This information is then used to inform further processor development and to determine the optimal partition between hardware and software. At each design iteration, the machine model is updated to reflect the available hardware resources, the compiler is rebuilt, and the target application is compiled once again. By including the compiler 'in-the-loop' of custom processor design, developers can accurately quantify the impact on performance caused by the addition or removal of specific hardware resources and iteratively converge on an optimal solution. Compiler Directed Codesign has advantages over existing codesign methodologies because it offers both a concrete point from which to begin the partitioning process as well as providing quantifiable and rapid feedback of the merits of different partitioning choices. When applied to an Adaptive PCM Encoder/Decoder case study, the Compiler Directed Codesign technique yielded a custom processor core that was between 36% and 73% smaller, consumed between 11% to 19% less memory, and performed up to 10X faster than comparable general-purpose FPGA-based processor cores. The conclusion of this work is that a suitably modified compiler can serve a valuable role in directing hardware/software partitioning on a per-application basis.
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Chiurco, Giovanni <1982&gt. "Cooperative and reconfigurable telecommunication systems based on FPGA." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amsdottorato.unibo.it/3466/1/Chiurco_Giovanni_CooperativeAndReconfigurableTelecommunicationSystemsBasedOnFpga.pdf.

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This work has been realized by the author in his PhD course in Electronics, Computer Science and Telecommunication at the University of Bologna, Faculty of Engineering, Italy. The subject of this thesis regards important channel estimation aspects in wideband wireless communication systems, such as echo cancellation in digital video broadcasting systems and pilot aided channel estimation through an innovative pilot design in Multi-Cell Multi-User MIMO-OFDM network. All the documentation here reported is a summary of years of work, under the supervision of Prof. Oreste Andrisano, coordinator of Wireless Communication Laboratory - WiLab, in Bologna. All the instrumentation that has been used for the characterization of the telecommunication systems belongs to CNR (National Research Council), CNIT (Italian Inter-University Center), and DEIS (Dept. of Electronics, Computer Science, and Systems). From November 2009 to May 2010, the author spent his time abroad, working in collaboration with DOCOMO - Communications Laboratories Europe GmbH (DOCOMO Euro-Labs) in Munich, Germany, in the Wireless Technologies Research Group. Some important scientific papers, submitted and/or published on IEEE journals and conferences have been produced by the author.
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Chiurco, Giovanni <1982&gt. "Cooperative and reconfigurable telecommunication systems based on FPGA." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amsdottorato.unibo.it/3466/.

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This work has been realized by the author in his PhD course in Electronics, Computer Science and Telecommunication at the University of Bologna, Faculty of Engineering, Italy. The subject of this thesis regards important channel estimation aspects in wideband wireless communication systems, such as echo cancellation in digital video broadcasting systems and pilot aided channel estimation through an innovative pilot design in Multi-Cell Multi-User MIMO-OFDM network. All the documentation here reported is a summary of years of work, under the supervision of Prof. Oreste Andrisano, coordinator of Wireless Communication Laboratory - WiLab, in Bologna. All the instrumentation that has been used for the characterization of the telecommunication systems belongs to CNR (National Research Council), CNIT (Italian Inter-University Center), and DEIS (Dept. of Electronics, Computer Science, and Systems). From November 2009 to May 2010, the author spent his time abroad, working in collaboration with DOCOMO - Communications Laboratories Europe GmbH (DOCOMO Euro-Labs) in Munich, Germany, in the Wireless Technologies Research Group. Some important scientific papers, submitted and/or published on IEEE journals and conferences have been produced by the author.
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Zou, Ding, Changyu Lin, and Ivan B. Djordjevic. "FPGA-based LDPC-coded APSK for optical communication systems." OPTICAL SOC AMER, 2017. http://hdl.handle.net/10150/623873.

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In this paper, with the aid of mutual information and generalized mutual information (GMI) capacity analyses, it is shown that the geometrically shaped APSK that mimics an optimal Gaussian distribution with equiprobable signaling together with the corresponding gray-mapping rules can approach the Shannon limit closer than conventional quadrature amplitude modulation (QAM) at certain range of FEC overhead for both 16-APSK and 64-APSK. The field programmable gate array (FPGA) based LDPC-coded APSK emulation is conducted on block interleaver-based and bit interleaver-based systems; the results verify a significant improvement in hardware efficient bit interleaver-based systems. In bit interleaver-based emulation, the LDPC-coded 64-APSK outperforms 64-QAM, in terms of symbol signal-to-noise ratio (SNR), by 0.1 dB, 0.2 dB, and 0.3 dB at spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz, respectively. It is found by emulation that LDPC-coded 64-APSK for spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz is 1.6 dB, 1.7 dB, and 2.2 dB away from the GMI capacity. (C) 2017 Optical Society of America
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Coyne, Jack W. "FPGA-based co-processor for singular value array reconciliation tomography." Worcester, Mass. : Worcester Polytechnic Institute, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-090507-114502/.

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Al-Araje, Abdul-Nasser. "Micronetwork based system-on-FPGA (SOFPGA) architecture." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1122609799.

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Alam, Nahid Mahfuza. "Implementation of Genetic Algorithms in FPGA-based reconfigurable computing systems." Connect to this title online, 2009. http://etd.lib.clemson.edu/documents/1252424140/.

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Books on the topic "FPGA-Based systems"

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Sklyarov, Valery, Iouliia Skliarova, Alexander Barkalov, and Larysa Titarenko. Synthesis and Optimization of FPGA-Based Systems. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-04708-9.

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Woods, Roger, John McAllister, Ying Yi, and Gaye Lightbody. FPGA-based Implementation of Signal Processing Systems. Chichester, UK: John Wiley & Sons, Ltd, 2017. http://dx.doi.org/10.1002/9781119079231.

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Gong, Lingkan, and Oliver Diessel. Functional Verification of Dynamically Reconfigurable FPGA-based Systems. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-06838-1.

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Waidyasooriya, Hasitha Muthumala, Masanori Hariyama, and Kunio Uchiyama. Design of FPGA-Based Computing Systems with OpenCL. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-68161-0.

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FPGA-based implementation of complex signal processing systems. Chichester, United Kingdom: John Wiley & Sons, 2008.

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Ullah, Salim, and Akash Kumar. Approximate Arithmetic Circuit Architectures for FPGA-based Systems. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-21294-9.

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Scott, Hauck, and DeHon André, eds. Reconfigurable computing: The theory and practice of FPGA-based computation. Amsterdam: Morgan Kaufmann, 2008.

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Farooq, Umer. Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization. New York, NY: Springer New York, 2012.

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Amos, Doug. FPGA-based prototyping methodology manual: Best practices in design-for-prototyping. Mountain View, Calif: Synopsys Press, 2011.

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Deschamps, Jean-Pierre. Guide to FPGA Implementation of Arithmetic Functions. Dordrecht: Springer Netherlands, 2012.

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Book chapters on the topic "FPGA-Based systems"

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McAllister, John. "FPGA-Based DSP." In Handbook of Signal Processing Systems, 707–39. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6859-2_22.

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McAllister, John. "FPGA-based DSP." In Handbook of Signal Processing Systems, 363–92. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6345-1_14.

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Angepat, Hari, Derek Chiou, Eric S. Chung, and James C. Hoe. "Categorizing FPGA-based Simulators." In FPGA-Accelerated Simulation of Computer Systems, 45–47. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-031-01744-5_5.

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Surshetty, Sanjay Kumar, Alisha Oraon, Renuka Kumari, Shradha Shreya, and Vijay Nath. "FPGA-Based Smart Irrigation System." In Nanoelectronics, Circuits and Communication Systems, 139–48. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2854-5_14.

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Babu, Hafiz Md Hasan. "FPGA-Based Programmable Logic Controller." In VLSI Circuits and Embedded Systems, 311–20. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-25.

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Brugger, Christian, Christian De Schryver, and Norbert Wehn. "Bringing Flexibility to FPGA Based Pricing Systems." In FPGA Based Accelerators for Financial Applications, 167–90. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15407-7_8.

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Di Stefano, Antonio, and Costantino Giaconia. "An FPGA-Based Adaptive Fuzzy Coprocessor." In Computational Intelligence and Bioinspired Systems, 590–97. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11494669_72.

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De Schryver, Christian, and Carolina Pereira Nogueira. "Towards Automated Benchmarking and Evaluation of Heterogeneous Systems in Finance." In FPGA Based Accelerators for Financial Applications, 75–95. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15407-7_4.

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Varela, Javier Alejandro, Christian Brugger, Songyin Tang, Norbert Wehn, and Ralf Korn. "Pricing High-Dimensional American Options on Hybrid CPU/FPGA Systems." In FPGA Based Accelerators for Financial Applications, 143–66. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15407-7_7.

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Panwar, Adesh. "Verification Platform for FPGA Based Architecture." In Advances in Intelligent Systems and Computing, 393–98. New Delhi: Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-0740-5_47.

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Conference papers on the topic "FPGA-Based systems"

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Oda, Naotaka, Teruji Tarumi, Atsushi Tanaka, Mikio Izumi, and Toshifumi Sato. "Development of FPGA-Based Safety-Related I&C Systems." In 12th International Conference on Nuclear Engineering. ASMEDC, 2004. http://dx.doi.org/10.1115/icone12-49167.

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Toshiba has developed FPGA-based systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related I&C systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on.
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Siora, Alexander, Volodymyr Sklyar, Yuriy Rozen, Svetlana Vinogradskaya, and Mikhail Yastrebenetsky. "Licensing Principles of FPGA-Based NPP I&C Systems." In 17th International Conference on Nuclear Engineering. ASMEDC, 2009. http://dx.doi.org/10.1115/icone17-75270.

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This paper objective is to discuss licensing principles of FPGA-based NPP I&C systems. Licensing aspects of FPGA-based NPP I&C systems lay in peculiarities of FPGA-technology. The main idea for licensing performing of FPGA-based NPP I&C systems lays in consideration of FPGA-chip as hardware and FPGA-project as software. FPGA related licensing principles are discussed in details in the paper.
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Skliarova, Iouliia, Valery Sklyarov, Alexander Sudnitson, and Margus Kruus. "Teaching FPGA-based systems." In 2014 IEEE Global Engineering Education Conference (EDUCON). IEEE, 2014. http://dx.doi.org/10.1109/educon.2014.6826133.

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Kharchenko, Vyacheslav S., Eugenii S. Bakhmach, Alexandr A. Siora, Vladimir V. Sklyar, and Viktor I. Tokarev. "Diversity-Oriented FPGA-Based NPP I&C Systems: Safety Assessment, Development, Implementation." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29754.

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Key challenges caused by implementation of diversity-oriented approach and FPGA technology are discussed in context of NPP I&C systems safety. National and international standards containing the requirements to diversity application in NPP I&C systems are analyzed. A few evolution stages of multi-version NPP I&C systems (Reactor Trip Systems) are described taking into account different types of version redundancy (hardware, software, FPGA diversity). Main attention is attended to the methods of increasing tolerance of NPP I&C systems to physical and design faults using multiversion technologies. A life cycle model and multi-version technologies of FPGA-based I&C systems development are analyzed. Implementation results of safety-critical NPP I&Cs developed by RPC “Radiy” using FPGA technology are described. The FPGA-based platform RADIY™ ensures scalability system functions, dependability and diversity. More than 20 different FPGA-based I&C systems were successfully developed, produced and implemented on the NPPs of Ukraine and Bulgaria during last five years.
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Palsberg, Jens, Scott Hauck, and Katherine Compton. "Session details: FPGA-based systems." In DAC04: The 41st Annual Design Automation Conference 2004. New York, NY, USA: ACM, 2004. http://dx.doi.org/10.1145/3246101.

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Tan-Phat, Phan, Paul C. P. Chao, and Huang Zih-Wei. "FPGA-Based Implementation of Torque Controller for 6-DOF Articulated Robots." In ASME 2021 30th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/isps2021-65255.

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Abstract This paper aims to design an impedance position-based proportional-integral-derivative (PID) controller based on forward and inverse kinematics of HIWIN RA605 articulated robot, and Field-Programmable Gate Array (FPGA) implementation for a PID torque controller. In order to control the robot, the FPGA needs to output commands to communicate with the AC servo motor drivers. An FPGA-based controller for a 6-degree-of-freedom (DOF) articulated robot that implements several tasks such as hardware implementation, encoder counters, noise cancellation algorithm, analog generators, PID controller, and communication are included, the processing time of the FPGA is 16 μs. Meanwhile, the whole process of the system only takes 82 μs to complete.
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Halupka, D. "FPGA-based speech enhancement." In Embedded Systems Conference ESS2005 Incorporating the IEE FPGA Developers Forum. IEE, 2005. http://dx.doi.org/10.1049/ic:20050644.

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Saramud, Mikhail V., Vasiliy V. Losev, and Angelina E. Petetskaya. "Implementation of decision‐making algorithms in redundant systems on FPGA." In V International Scientific Workshop on Modeling, Information Processing and Computing. CEUR-WS.org, 2022. http://dx.doi.org/10.47813/dnit-mip5/2022-3091-66-71.

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The paper describes the problem of creating fault-tolerant real-time control systems. The authors describe methods for improving the reliability of control systems for both hardware and software. The features of the system operation in real time are presented. The paper considers various versions of hardware platforms for real-time operation are such as CPU applying RTOS, FPGA, ASIC. The peculiarities of applying FPGA and developing software for it are outlined. The main blocks that make up the FPGA are represented. The hardware platform for prototype implementation is proposed. The authors opt to follow myRIO-1900 based on SoC Xilinx Zynq-7010 as it contains FPGA, CPU with RTOS implementation for it. A new approach is proposed. It combines the implementation of a decision-making block in control systems by means of a real-time operating system running on a CPU and a special FPGA that implements watchdogs and decision-making algorithms in multiversion systems. Watchdog on the FPGA monitors the main decision block in the RTOS. It should provide a response within a specified period of time. If this does not happen, it starts a spare decision block implemented on the FPGA. It is guaranteed to make a decision in one clock cycle of the FPGA. This approach will improve the overall reliability of fault-tolerant control systems without significantly increasing their cost.
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9

Laczko, P., B. Feher, and B. Benyo. "FPGA-based BLAST prefiltering." In 2010 IEEE 14th International Conference on Intelligent Engineering Systems (INES 2010). IEEE, 2010. http://dx.doi.org/10.1109/ines.2010.5483825.

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Sklyarov, Valery, and Iouliia Skliarova. "Data processing in FPGA-based systems." In 2012 6th International Conference on Application of Information and Communication Technologies (AICT). IEEE, 2012. http://dx.doi.org/10.1109/icaict.2012.6398506.

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Reports on the topic "FPGA-Based systems"

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Hu, Yalin. Exploring formal verification methodology for FPGA-based digital systems. Office of Scientific and Technical Information (OSTI), September 2012. http://dx.doi.org/10.2172/1055616.

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El-Ghazawi, Tarek, Alan D. George, Ivan Gonzalez, Herman Lam, Saumil Merchant, Proshanta Saha, Melissa Smith, Greg Stitt, Nahid Alam, and Esam El-Araby. Exploration of a Research Roadmap for Application Development and Execution on Field-Programmable Gate Array (FPGA)-Based Systems. Fort Belvoir, VA: Defense Technical Information Center, October 2008. http://dx.doi.org/10.21236/ada494473.

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