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Dissertations / Theses on the topic 'FPGA-Based systems'

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Published: 9 March 2023

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1

Stavström, Marcus. "Evaluation of FPGA based Test Systems." Thesis, Linköpings universitet, Datorteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-119094.

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This master thesis report covers an investigation of how FPGA based hardware can be used to create customizable measurement instruments, for test of electrical equipment in JAS 39 Gripen. The investigation is done at Saab Support and Services in Arboga. Electrical equipment are gradually replacing functions, which previously have been obtained by other systems, in safety critical environments. Since the functions are safety critical, they require regular testing in order to verify proper operation. The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is an example of such system. Proper operation of the avionics in it are essential in order to maintain flying safety. There already exist systems today that can verify the functionality of electronics in JAS 39 Gripen. However, there are a number of scenarios where those test systems are somewhat inflexible. More flexible test systems are often desired. This flexibility can be obtained by using congurable hardware, suggestively with FPGAs. This approach is investigated in this master thesis.
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2

Lepistö, Niklas. "FPGA based architectures for embedded video systems /." Sundsvall : Departement of Information Technology and Media, Mid Sweden University, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-188.

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3

Devic, Florian. "Securing embedded systems based on FPGA technologies." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20107.

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Les systèmes embarqués peuvent contenir des données sensibles. Elles sont généralement échangées en clair entre le système sur puces et la mémoire, mais aussi en interne. Cela constitue un point faible: un attaquant peut observer cet échange et récupérer des informations ou insérer du code malveillant. L'objectif de la thèse est de fournir une solution dédiée et adaptée à ces problèmes en considérant l'intégralité de la durée de vie du système embarqué (démarrage, mises à jour et exécution) et l'intégralité des données (bitstream du FPGA, noyau du système d'exploitation, code et données critiques). En outre, il est nécessaire d'optimiser les performances des mécanismes matériels de sécurité introduits afin de correspondre aux attentes des systèmes embarqués. Cette thèse se distingue en proposant des solutions innovantes et adaptées au monde des FPGAs
Embedded systems may contain sensitive data. They are usually exchanged in plaintext between the system on chips and the memory, but also internally. This is a weakness: an attacker can spy this exchange and retrieve information or insert malicious code. The aim of the thesis is to provide a dedicated and suitable solution for these problems by considering the entire lifecycle of the embedded system (boot, updates and execution) and all the data (FPGA bitstream, operating system kernel, critical data and code). Furthermore, it is necessary to optimize the performance of hardware security mechanisms introduced to match the expectations of embedded systems. This thesis is distinguished by offering innovative and suitable solutions for the world of FPGAs
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Hauff, Martin Anthony, and marty@extendabilities com au. "Compiler Directed Codesign for FPGA-based Embedded Systems." RMIT University. Electrical and Computer Engineering, 2008. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20081202.141333.

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As embedded systems designers increasingly turn to programmable logic technologies in place of off-the-shelf microprocessors, there is a growing interest in the development of optimised custom processing cores that can be designed on a per-application basis. FPGAs blur the traditional distinction between hardware and software and offer the promise of application specific hardware acceleration. But realizing this in a general sense requires a significant departure from traditional embedded systems development flows. Whereas off-the-shelf processors have a fixed architecture, the same cannot be said of purpose-built FPGA-based processors. With this freedom comes the challenge of empirically determining the optimal boundary point between hardware and software. The fluidity of the hardware/software partition also poses an interesting challenge for compiler developers. This thesis presents a tool and methodology that addresses these codesign challenges in a new way. Described as 'compiler-directed codesign', it makes use of a suitably modified compiler to help direct the development of a custom processor core on a per-application basis. By exposing the compiler's internal representation of a compiled target program, visibility into those instructions, and hardware resources, that are most sought after by the compiler can be gained. This information is then used to inform further processor development and to determine the optimal partition between hardware and software. At each design iteration, the machine model is updated to reflect the available hardware resources, the compiler is rebuilt, and the target application is compiled once again. By including the compiler 'in-the-loop' of custom processor design, developers can accurately quantify the impact on performance caused by the addition or removal of specific hardware resources and iteratively converge on an optimal solution. Compiler Directed Codesign has advantages over existing codesign methodologies because it offers both a concrete point from which to begin the partitioning process as well as providing quantifiable and rapid feedback of the merits of different partitioning choices. When applied to an Adaptive PCM Encoder/Decoder case study, the Compiler Directed Codesign technique yielded a custom processor core that was between 36% and 73% smaller, consumed between 11% to 19% less memory, and performed up to 10X faster than comparable general-purpose FPGA-based processor cores. The conclusion of this work is that a suitably modified compiler can serve a valuable role in directing hardware/software partitioning on a per-application basis.
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5

Chiurco, Giovanni <1982&gt. "Cooperative and reconfigurable telecommunication systems based on FPGA." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amsdottorato.unibo.it/3466/1/Chiurco_Giovanni_CooperativeAndReconfigurableTelecommunicationSystemsBasedOnFpga.pdf.

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This work has been realized by the author in his PhD course in Electronics, Computer Science and Telecommunication at the University of Bologna, Faculty of Engineering, Italy. The subject of this thesis regards important channel estimation aspects in wideband wireless communication systems, such as echo cancellation in digital video broadcasting systems and pilot aided channel estimation through an innovative pilot design in Multi-Cell Multi-User MIMO-OFDM network. All the documentation here reported is a summary of years of work, under the supervision of Prof. Oreste Andrisano, coordinator of Wireless Communication Laboratory - WiLab, in Bologna. All the instrumentation that has been used for the characterization of the telecommunication systems belongs to CNR (National Research Council), CNIT (Italian Inter-University Center), and DEIS (Dept. of Electronics, Computer Science, and Systems). From November 2009 to May 2010, the author spent his time abroad, working in collaboration with DOCOMO - Communications Laboratories Europe GmbH (DOCOMO Euro-Labs) in Munich, Germany, in the Wireless Technologies Research Group. Some important scientific papers, submitted and/or published on IEEE journals and conferences have been produced by the author.
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6

Chiurco, Giovanni <1982&gt. "Cooperative and reconfigurable telecommunication systems based on FPGA." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amsdottorato.unibo.it/3466/.

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This work has been realized by the author in his PhD course in Electronics, Computer Science and Telecommunication at the University of Bologna, Faculty of Engineering, Italy. The subject of this thesis regards important channel estimation aspects in wideband wireless communication systems, such as echo cancellation in digital video broadcasting systems and pilot aided channel estimation through an innovative pilot design in Multi-Cell Multi-User MIMO-OFDM network. All the documentation here reported is a summary of years of work, under the supervision of Prof. Oreste Andrisano, coordinator of Wireless Communication Laboratory - WiLab, in Bologna. All the instrumentation that has been used for the characterization of the telecommunication systems belongs to CNR (National Research Council), CNIT (Italian Inter-University Center), and DEIS (Dept. of Electronics, Computer Science, and Systems). From November 2009 to May 2010, the author spent his time abroad, working in collaboration with DOCOMO - Communications Laboratories Europe GmbH (DOCOMO Euro-Labs) in Munich, Germany, in the Wireless Technologies Research Group. Some important scientific papers, submitted and/or published on IEEE journals and conferences have been produced by the author.
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7

Zou, Ding, Changyu Lin, and Ivan B. Djordjevic. "FPGA-based LDPC-coded APSK for optical communication systems." OPTICAL SOC AMER, 2017. http://hdl.handle.net/10150/623873.

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In this paper, with the aid of mutual information and generalized mutual information (GMI) capacity analyses, it is shown that the geometrically shaped APSK that mimics an optimal Gaussian distribution with equiprobable signaling together with the corresponding gray-mapping rules can approach the Shannon limit closer than conventional quadrature amplitude modulation (QAM) at certain range of FEC overhead for both 16-APSK and 64-APSK. The field programmable gate array (FPGA) based LDPC-coded APSK emulation is conducted on block interleaver-based and bit interleaver-based systems; the results verify a significant improvement in hardware efficient bit interleaver-based systems. In bit interleaver-based emulation, the LDPC-coded 64-APSK outperforms 64-QAM, in terms of symbol signal-to-noise ratio (SNR), by 0.1 dB, 0.2 dB, and 0.3 dB at spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz, respectively. It is found by emulation that LDPC-coded 64-APSK for spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz is 1.6 dB, 1.7 dB, and 2.2 dB away from the GMI capacity. (C) 2017 Optical Society of America
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8

Coyne, Jack W. "FPGA-based co-processor for singular value array reconciliation tomography." Worcester, Mass. : Worcester Polytechnic Institute, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-090507-114502/.

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9

Al-Araje, Abdul-Nasser. "Micronetwork based system-on-FPGA (SOFPGA) architecture." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1122609799.

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10

Alam, Nahid Mahfuza. "Implementation of Genetic Algorithms in FPGA-based reconfigurable computing systems." Connect to this title online, 2009. http://etd.lib.clemson.edu/documents/1252424140/.

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11

Parthasarathy, Anand Kumar. "Feasibility analysis of FPGA based spindle motor controller." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2009.
Includes bibliographical references.
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12

Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

QC 20140609

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13

Yang, Conghuan. "Real-time FPGA-based co-simulation of large scale power systems." Thesis, University of Birmingham, 2018. http://etheses.bham.ac.uk//id/eprint/8037/.

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With the rapid increase of size and complexity of modem electrical power systems, 1) the simulation accuracy and 2) the capability of simulating large power systems have become two conflicting objectives. This thesis proposes a novel FPGA-RTDS co-simulator to meet these two objectives. As the basis of the co-simulator, a library of power system components is developed in FPGA, including the most commonly used power system elements and control systems. The proposed cosimulator combines the advantages of 1) the paralleled architecture, high logic density and high clock speed from FPGA and 2) better modelling flexibility and user-friendly GUI from RTDS together. Multi-FPGA structure is introduced to further improve the simulation capability for large power systems. The use of detailed EMT models in the whole system guarantees the accuracy of simulation and eliminates the potential interface error. Deeply pipelined and massively paralleled algorithms have been designed to maximize time and hardware efficiency. The modular design significantly improves the system expandability. Case studies including large scale power system with more than 4000 nodes are presented to demonstrate the simulation capability. Comparisons are made with SIMULINK and RTDS to verify the accuracy of the proposed co-simulator.
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Rowberry, Hayden Cole. "A Soft-Error Reliability Testing Platform for FPGA-Based Network Systems." BYU ScholarsArchive, 2019. https://scholarsarchive.byu.edu/etd/7739.

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FPGAs are frequently used in network systems to provide the performance and flexibility that is required of modern computer networks while allowing network vendors to bring products to market quickly. Like all electronic devices, FPGAs are vulnerable to ionizing radiation which can cause applications operating on an FPGA to fail. These low-level failures can have a wide range of negative effects on the performance of a network system. As computer networks play a larger role in modern society, it becomes increasingly important that these soft errors are addressed in the design of network systems.This work presents a framework for testing the soft-error reliability of FPGA-based networking systems. The framework consists of the NetFPGA development board, a custom traffic generator, and a custom high-speed JTAG configuration device. The NetFPGA development board is versatile and can be used to implement a wide range of network applications. The traffic generator is used to exercise the network system on the NetFPGA and to determine the health of that system. The JTAG configuration device is used to manage reliability experiments, to perform fault injection into the FPGA, and to monitor the NetFPGA during radiation tests.This thesis includes soft-error reliability tests that were performed on an Ethernet switch network system. Using both fault injection and accelerate radiation testing, the soft error sensitivity of the Ethernet switch was measured. The Ethernet switch design was then mitigated using triple module redundancy and duplication with compare. These mitigated designs were also tested and compared against the baseline design. Radiation testing shows that TMR provides a 5.05x improvement in reliability over the baseline design. DWC provides a 5.22x improvement in detectability over the baseline design without reducing the reliability of the system.
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Bowen, John Kipp. "Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/31088.

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Modern Field Programmable Gate Arrays (FPGAs) can implement entire run-time reconfigurable systems using partial reconfiguration. Module-based run-time reconfiguration permits the construction of custom applications at run-time using pre-compiled Intellectual Property (IP) from a module library. The need for both flexible module placement and custom inter-module communication is mostly ignored by existing modular run-time reconfiguration approaches and few existing tool flows for module generation address the need for automation. This thesis introduces an automated compile-time tool flow for generating dynamic modules that allow flexible run-time placement and communication synthesis.
Master of Science
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16

Soh, Jeremy. "A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter." Thesis, The University of Sydney, 2017. http://hdl.handle.net/2123/17286.

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Sustained technological progress has come to a point where robotic/autonomous systems may well soon become ubiquitous. In order for these systems to actually be useful, an increase in autonomous capability is necessary for aerospace, as well as other, applications. Greater aerospace autonomous capability means there is a need for high performance state estimation. However, the desire to reduce costs through simplified development processes and compact form factors can limit performance. A hardware-based approach, such as using a Field Programmable Gate Array (FPGA), is common when high performance is required, but hardware approaches tend to have a more complicated development process when compared to traditional software approaches; greater development complexity, in turn, results in higher costs. Leveraging the advantages of both hardware-based and software-based approaches, a hardware/software (HW/SW) codesign of the Unscented Kalman Filter (UKF), based on an FPGA, is presented. The UKF is split into an application-specific part, implemented in software to retain portability, and a non-application-specific part, implemented in hardware as a parameterisable IP core to increase performance. The codesign is split into three versions (Serial, Parallel and Pipeline) to provide flexibility when choosing the balance between resources and performance, allowing system designers to simplify the development process. Simulation results demonstrating two possible implementations of the design, a nanosatellite application and a Simultaneous Localisation and Mapping (SLAM) application, are presented. These results validate the performance of the HW/SW UKF and demonstrate its portability, particularly in small aerospace systems. Implementation (synthesis, timing, power) details for a variety of situations are presented and analysed to demonstrate how the HW/SW codesign can be scaled for any application.
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Palm, Johan. "High Performance FPGA-Based Computation and Simulation for MIMO Measurement and Control Systems." Thesis, Mälardalen University, School of Innovation, Design and Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-7477.

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The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors.

Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware.

In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware.

Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.

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McKeown, Mark. "Re-configurable FPGA-based semiconductor IP solutions for mobile cellular communications systems." Thesis, University of Glasgow, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.416544.

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McDaniel, Larry T. III. "An Investigation of Differential Power Analysis Attacks on FPGA-based Encryption Systems." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/33451.

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Hardware devices implementing cryptographic algorithms are finding their way into many applications. As this happens, the ability to keep the data being processed or stored on the device secure grows more important. Power analysis attacks involve cryptographic hardware leaking information during encryption because power consumption is correlated to the key used for encryption. Power analysis attacks have proven successful against public and private key cryptosystems in a variety of form factors. The majority of the countermeasures that have been proposed for this attack are intended for software implementations on a microcontroller. This project focuses on the development of a VHDL tool for investigating power analysis attacks on FPGAs and exploring countermeasures that might be used. The tool developed here counted the transitions of CLB output signals to estimate power and was used to explore the impact of possible gate-level countermeasures to differential power analysis. Using this tool, it was found that only a few nodes in the circuit have a high correlation to bits of the key. This means that modifying only a small portion of the circuit could dramatically increase the difficulty of mounting a differential power analysis attack on the hardware. Further investigation of the correlation between CLB outputs and the key showed that a tradeoff exists between the amount of space required for decorrelation versus the amount of decorrelation that is desired, allowing a designer to determine the amount of correlation that can be removed for available space. Filtering of glitches on CLB output signals slightly reduced the amount of correlation each CLB had. Finally, a decorrelation circuit was proposed and shown capable of decorrelating flip-flop outputs of a CLB, which account for less than 10% of the CLB outputs signals.
Master of Science
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20

Adnan, Muhammad Wasif. "Implementation of an FPGA based Emulator for High Speed Power Electronic Systems." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175752.

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During development of control systems for power electronic systems, it is desirable to test the controller in real-time, by interfacing it with an emulator device. In this context, this work comprises the development of an emulator that can model accurately the dynamics of high speed power electronic systems and provides interfaces that are compatible with the real hardware. The realtime state calculations, based on discrete models, were performed on custom logic, implemented on an FPGA. The realized system allows to emulate Linear Parameter Varying (LPV) systems, achieving sampling rates up to 12MHz using a low cost Xilinx FPGA. As a result, power electronic systems with very high switching frequencies can be modeled. In addition, the FPGA incorporates a soft-core processor that allows a designer to easily re-configure the system model through software. The emulator system has been validated for a multiphase DC-DC converter, by comparing its results with the real hardware setup.
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Siegle, Felix. "Fault detection, isolation and recovery schemes for spaceborne reconfigurable FPGA-based systems." Thesis, University of Leicester, 2016. http://hdl.handle.net/2381/37521.

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This research contributes to a better understanding of how reconfigurable Field Programmable Gate Array (FPGA) devices can safely be used as part of satellite payload data processing systems that are exposed to the harsh radiation environment in space. Despite a growing number of publications about low-level mitigation techniques, only few studies are concerned with high-level Fault Detection, Isolation and Recovery (FDIR) methods, which are applied to FPGAs in a similar way as they are applied to other systems on board spacecraft. This PhD thesis contains several original contributions to knowledge in this field. First, a novel Distributed Failure Detection method is proposed, which applies FDIR techniques to multi-FPGA systems by shifting failure detection mechanisms to a higher intercommunication network level. By doing so, the proposed approach scales better than other approaches with larger and complex systems since data processing hardware blocks, to which FDIR is applied, can easily be distributed over the intercommunication network. Secondly, an innovative Availability Analysis method is proposed that allows a comparison of these FDIR techniques in terms of their reliability performance. Furthermore, it can be used to predict the reliability of a specific hardware block in a particular radiation environment. Finally, the proposed methods were implemented as part of a proof of concept system: On the one hand, this system enabled a fair comparison of different FDIR configurations in terms of power, area and performance overhead. On the other hand, the proposed methods were all successfully validated by conducting an accelerated proton irradiation test campaign, in which parts of this system were exposed to the proton beam while the proof of concept application was actively running.
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Pratt, Brian Hogan. "Analysis and Mitigation of SEU-induced Noise in FPGA-based DSP Systems." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2482.

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This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates reduced-precision redundancy (RPR) as an effective and efficient alternative to the popular triple modular redundancy (TMR) for FPGA-based communications systems. Fault injection experiments show that RPR can improve the failure rate of a communications system by over 20 times over the unmitigated system at a cost less than half that of TMR by focusing on the critical SEUs. This dissertation contrasts the cost and performance of three different variations of RPR, one of which is a novel variation developed here, and concludes that the variation referred to as "Threshold RPR" is superior to the others for FPGA systems. Finally, this dissertation presents several methods for applying Threshold RPR to a system with the goal of reducing mitigation cost and increasing the system performance in the presence of SEUs. Additional fault injection experiments show that optimizing the application of RPR can result in a decrease in critical SEUs by as much 65% at no additional hardware cost.
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Ramalho, Lucas Arruda. "An FPGA based 3.8 Tbps Data Sourcing and Emulator System." Universidade Estadual Paulista (UNESP), 2018. http://hdl.handle.net/11449/153037.

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A evolução dos Multi Gigabit Transceivers (MGT) nos Field Programmable Gate Arrays (FPGA) trouxeram oportunidades para o desenvolvimento de sistemas de aquisição e formatadores de dados em diversas áreas. As novas famílias de FPGAs são capazes de lidar com canais de transmissão com velocidade da ordem de Gbps que utilizam protocolos seriais de alta velocidade, podendo assim se tornar o futuro dos processadores downstream ou upstream. Os sistemas digitais criados para esse propósito, precisam ser confiáveis e síncronos entre dezenas de canais e placas. Como forma de permitir o teste de projetos com essa taxa massiva de bits, essa tese descreve o desenvolvimento do Data Sourcing System (DSS). Esse sistema deve ser capaz de testar qualquer application upstream ou downstream, permitir controle e acesso remoto aos sinais internos dos FPGAs, medir sincronismo e latência entre MGTs e avaliar integridade de links através de bit error rate (BER). Este trabalho faz parte de uma colaboração internacional liderada pelo Fermilab que propôs, com a contribuição do sistema descrito nesta tese, um sistema de trigger de nível 1 para o Compact Muon Solenoid (CMS) Outer Tracker. O dectetor CMS é um experimento vinculado ao European Organization for Nuclear Research (CERN). O DSS foi implementado sobre a placa Pulsar 2b, uma placa padrão Advanced Telecommunication Computing Architecture (ATCA), desenvolvida pelo Fermilab, que conta com um dispositivo FPGA para programação e costumização de aplicações. O setup de hardware utilizado foi construído sobre dois bastidores ATCA com 12 placas Pulsares 2b em cada. A taxa de dados máxima atingida foi de 3.84 Tbps entre os dois bastidores ATCAs. O DSS está operacional e foi utilizado para emular o fluxo de dados de saída do CMS Silicon Outer Tracker, e auxiliar na demonstração da proposta trigger de nível 1. Esta tese descreve essa demonstração como estudo de caso, que testa o formatador de dados do trigger (downstream) através do DSS e- mulando a saída de dados do detector. Nesse estudo de caso, tanto o DSS e o trigger proposto foram implementados utilizando o mesmo hardware ATCA e a Pulsar 2b. O foco do estudo de caso é descrever a comunicação entre o Data Sourcing shelf e o Pattern Recognition shelf. O DSS atendeu aos requisitos da demonstração provendo uma interface de usuário que permite aos desenvolvedores de trigger inserir sinais de controle e executar operações de leitura e escrita de forma remota nos FPGAs.
The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is operational and was already used to emulate the CMS Silicon Tracker data, and helped the demonstration of a L1 Trigger approach. This thesis describes the demonstration performed as case of study, which used the DSS as upstream system and tested the trigger data delivery as a downstream. In the case of study, both DSS and the proposed trigger are performed by the same ATCA hardware and the Pulsar 2b. The case of study focused to describe the communication between the Data Sourcing shelf and the Pattern Recognition shelf. Data Sourcing reached those requirements for the demonstration and provided a user interface that allows the trigger developers to insert control signals or to perform W/R operations inside Pulsar 2b FPGA block memories.
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Lundkvist, Herman, and Alexander Yngve. "Accelerated Simulation of Modelica Models Using an FPGA-Based Approach." Thesis, Linköpings universitet, Datorteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-145692.

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This thesis presents Monza, a system for accelerating the simulation of modelsof physical systems described by ordinary differential equations, using a generalpurpose computer with a PCIe FPGA expansion card. The system allows bothautomatic generation of an FPGA implementation from a model described in theModelica programming language, and simulation of said system.Monza accomplishes this by using a customizable hardware architecture forthe FPGA, consisting of a variable number of simple processing elements. A cus-tom compiler, also developed in this thesis, tailors and programs the architectureto run a specific model of a physical system.Testing was done on two test models, a water tank system and a Weibel-lung,with up to several thousand state variables. The resulting system is several timesfaster for smaller models and somewhat slower for larger models compared to aCPU. The conclusion is that the developed hardware architecture and softwaretoolchain is a feasible way of accelerating model execution, but more work isneeded to ensure faster execution at all times.
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Ellsworth, Kevin M. "Understanding Design Requirements for Building Reliable, Space-Based FPGA MGT Systems Based on Radiation Test Results." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3159.

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Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. These tests were specifically designed to discover system susceptibilities, and effective mechanisms for upset detection, recovery, and recovery detection. Test results reveal that the Aurora protocol serves as an effective basis for simple point-to-point communication for space-based systems but that some additional logic is necessary for high reliability. Particularly, additional upset detection and recovery mechanisms are necessary as well as additional status indicators. These additions are minimal, however, and not all are necessary depending on system requirements. The most susceptible part of the MGT system is the MGT tile components on the RX data path. Upsets to these components most often results in data corruption only and do not affect system operation or disrupt the communication link. Most other upsets which do disrupt normal system operation can be recovered automatically by the Aurora protocol with built-in mechanisms. Only 1% of observed events in testing required additional recovery mechanisms not supplied by Aurora. In addition to test data results, this work also provides suggestions for system designers based on various system requirements and a proposed MGT system design based on the Aurora protocol. The proposed system serves as an example to illustrate how test data can be used to guide the system design and determine system availability. With this knowledge designers are able to build reliable MGT systems for a variety of space-based systems.
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Modi, Bala. "FPGA-based high throughput regular expression pattern matching for network intrusion detection systems." Thesis, University of Kent, 2015. https://kar.kent.ac.uk/56664/.

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Network speeds and bandwidths have improved over time. However, the frequency of network attacks and illegal accesses have also increased as the network speeds and bandwidths improved over time. Such attacks are capable of compromising the privacy and confidentiality of network resources belonging to even the most secure networks. Currently, general-purpose processor based software solutions used for detecting network attacks have become inadequate in coping with the current network speeds. Hardware-based platforms are designed to cope with the rising network speeds measured in several gigabits per seconds (Gbps). Such hardware-based platforms are capable of detecting several attacks at once, and a good candidate is the Field-programmable Gate Array (FPGA). The FPGA is a hardware platform that can be used to perform deep packet inspection of network packet contents at high speed. As such, this thesis focused on studying designs that were implemented with Field-programmable Gate Arrays (FPGAs). Furthermore, all the FPGA-based designs studied in this thesis have attempted to sustain a more steady growth in throughput and throughput efficiency. Throughput efficiency is defined as the concurrent throughput of a regular expression matching engine circuit divided by the average number of look up tables (LUTs) utilised by each state of the engine"s automata. The implemented FPGA-based design was built upon the concept of equivalence classification. The concept helped to reduce the overall table size of the inputs needed to drive the various Nondeterministic Finite Automata (NFA) matching engines. Compared with other approaches, the design sustained a throughput of up to 11.48 Gbps, and recorded an overall reduction in the number of pattern matching engines required by up to 75%. Also, the overall memory required by the design was reduced by about 90% when synthesised on the target FPGA platform.
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Lee, Tien-Lung. "An interface methodology for reconfigurable FPGA peripherals : a feature-based approach /." [St. Lucia, Qld.], 2005. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe19194.pdf.

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Pahlavan, Yali Moein. "FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/51193.

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The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance of modern embedded processors, they are outpaced by computational demands of the growing number of modern applications. This trend has led to emergence of hardware accelerators in embedded systems. While the processing power of dedicated hardware modules seems appealing, they require significant effort of development and integration to gain performance benefit. Thus, it is prudent to investigate and estimate the integration overhead and consequently the hardware acceleration benefit before committing to implementation. In this work, we present FPGA-Roofline, a visual model that offers insights to designers and developers to have realistic expectations of their system and that enables them to do their design and analysis in a faster and more efficient fashion. FPGA-Roofline allows simultaneous analysis of communication and computation resources in FPGA-based hardware accelerators. To demonstrate the effectiveness of our model, we have implemented hardware accelerators in FPGA and used our model to analyze and optimize the overall system performance. We show how the same methodology can be applied to the design process of any FPGA-based hardware accelerator to increase productivity and give insights to improve performance and resource utilization by finding the optimal operating point of the system.
Master of Science
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Abdollahzadeh, Zare Mohammad. "FPGA-Based Simulation and Implementation of Induction Motor Torque Control Systems Based on Direct Torque Control (DTC)." Thesis, North Dakota State University, 2014. https://hdl.handle.net/10365/27275.

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Electric drives for induction machines are of great importance because of the popularity of this machine type. To design, simulate and implement such drives, fast, reliable digital signal processors are needed. Recently Field Programmable Gate Array (FPGA) has been used in electric drive applications. This is mostly because of higher flexibility of hardware solutions compared to software solutions. In this thesis, FPGA-based simulation and implementation of direct torque control (DTC) of induction motors are studied. DTC is simulated on an FPGA as well as a personal computer. Results prove the FPGA-based simulation to be 12 times faster. Also an experimental setup of DTC is implemented using both FPGA and dSPACE. The FPGA-based design provides a potential sampling frequency of 800 kHz. This is a breakthrough knowing that a low ripple DTC is highly dependent on high sampling frequencies. Finally, a configurable torque/speed control system is designed and implemented on dSPACE.
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Zou, Ding, and Ivan B. Djordjevic. "FPGA-Based Rate-Compatible LDPC Codes for the Next Generation of Optical Transmission Systems." IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016. http://hdl.handle.net/10150/621685.

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In this paper, we propose a rate-compatible forward error-correcting (FEC) scheme based on low-density-parity check (LDPC) codes together with its software reconfigurable unified field-programmable gate array (FPGA) architecture. By FPGA emulation, we demonstrate that the proposed class of rate-compatible LDPC codes based on puncturing and generalized LDPC coding with an overhead from 25% to 46% provides a coding gain ranging from 12.67 to 13.8 dB at a post-FEC bit-error rate (BER) of 10(-15). As a result, the proposed rate-compatible codes represent one of the strong FEC candidates of soft-decision FEC for both short-haul and long-haul optical transmission systems.
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Alvis, Wendy. "Development of an FPGA based autopilot hardware platform for research and development of autonomous systems." [Tampa, Fla] : University of South Florida, 2008. http://purl.fcla.edu/usf/dc/et/SFE0002321.

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Mühlfellner, Peter. "Selection, Analysis and Implementationof Image-based Feature Extraction Approaches for a Heterogenous, Modular and FPGA-based Architecture for Camera-based Driver Assistance Systems." Thesis, Högskolan i Halmstad, Intelligenta system (IS-lab), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-16377.

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We propose a scalable and fexible hardware architecture for the extraction of image features, used in conjunction with an attentional cascade classifier for appearance-based object detection. Individual feature processors calculate feature-values in parallel, using parameter-sets and image data that is distributed via BRAM buffers. This approach can provide high utilization- and throughput-rates for a cascade classifier. Unlike previous hardware implementations, we are able to flexibly assign feature processors to either work on a single- or multiple image windows in parallel, depending on the complexity of the current cascade stage. The core of the architecture was implemented in the form of a streaming based FPGA design, and validated in simulation, synthesis, as well as via the use of a Logic Analyser for the verification of the on-chip functionality. For the given implementation, we focused on the design of Haar-like feature processors, but feature processors for a variety of heterogenous feature types, such as Gabor-like features, can also be accomodated by the proposed hardware architecture.
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Bondehagen, Brent. "FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT." UKnowledge, 2013. http://uknowledge.uky.edu/ece_etds/23.

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Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface topology, phase information can be calculated and a 3D model constructed. Phase Measuring Profilometry (PMP) is a particular type of SLI that requires three or more patterns temporarily multiplexed. High speed PMP attempts to scan moving objects whose motion is small so as to have little impact on the 3-D model. Given that practically all machine vision cameras and high speed cameras employ a Field Programmable Gate Array (FPGA) interface directly to the image sensors, the opportunity exists to do the processing on camera. This thesis focuses on the design, implementation, testing, and evaluation of a camera-projector system to implement a PMP dual-frequency scheme for 3-D shape measurement on a single FPGA chip. The processor architecture is implemented and tested using the Xilinx Spartan 3 FPGA chip on an Opal Kelly development board. The hardware is described using VHDL and Verilog Hardware Description Languages (HDLs).
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Zou, Ding, and Ivan B. Djordjevic. "FPGA-based rate-adaptive LDPC-coded modulation for the next generation of optical communication systems." OPTICAL SOC AMER, 2016. http://hdl.handle.net/10150/621981.

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In this paper, we propose a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that the proposed class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10(-15) for BPSK transmission. In addition, the proposed rate-adaptive LDPC coding combined with higher-order modulations have been demonstrated including QPSK, 8-QAM, 16-QAM, 32-QAM, and 64-QAM, which covers a wide range of signal-to-noise ratios. Furthermore, we apply the unequal error protection by employing different LDPC codes on different bits in 16-QAM and 64-QAM, which results in additional 0.5dB gain compared to conventional LDPC coded modulation with the same code rate of corresponding LDPC code. (C) 2016 Optical Society of America
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Watt, James Penn. "A Highly Abstracted Method of FPGA-Based Development for Secondary Surveillance Radar Transpond Detection." DigitalCommons@CalPoly, 2009. https://digitalcommons.calpoly.edu/theses/148.

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Traditional FPGA-based digital design is based on writing hardware definition language (HDL) code from scratch. Time to market, cost of development, and the level of training required for designers all can be reduced with a simplified and abstracted design strategy. This project intends to demonstrate a graphical user interface (GUI) layer of abstraction on top of existing commercially produced design aids including MATLAB, Simulink, and Xilinx System Generator. This project performs and demonstrates a specific implementation example of a Secondary Surveillance Radar (SSR) message decoder as proof-of-concept for the abstracted design method. The abstracted digital design methods shown in this project can be adapted for use in other areas of development and research including digital signal processing and communications.
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Aounis, Abdulmagid. "An investigation into induction motor vector control based on reusable VHDL digital architectures and FPGA rapid prototyping." Thesis, De Montfort University, 2002. http://hdl.handle.net/2086/5206.

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Niknahad, Mahtab [Verfasser]. "Using Fine Grain Approaches for highly reliable Design of FPGA-based Systems in Space / Mahtab Niknahad." Karlsruhe : KIT Scientific Publishing, 2013. http://www.ksp.kit.edu.

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Staub, Dillon. "Bio-Inspired Hardware Security Defenses: A CRISPR-Cas-Based Approach for Detecting Trojans in FPGA Systems." University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1563872470616901.

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Jaoua, Mohamed. "Development of an FPGA-based High-Speed Wireless Communication System in the 60GHz Frequency Band For CERN facilities and 5G deployment." Thesis, Linköpings universitet, Kommunikationssystem, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-147677.

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The work is devoted in the development and the exploration of the capabilities of the state of art unlicensed 60GHz (V-Band) mm-wave band that has raised so much interest and attention from numerous companies and laboratories for implementing Multi-gigabit communications [17] and especially for the 5th generation of cellular network and wireless systems. Implementing a high wireless data transfer system requires a high bandwidth and the one around the 60GHz frequency turned out to be a very promising candidate [13]. In this thesis, different protocols were investigated and simulated on MATLAB and implemented on low-cost Field-Programmable Gate Arrays (FPGAs) in order to test its performance with different transmission protocols and systems and insure a robust communication system at the frequency band around 60GHz. Furthermore, the system was tested with a series of different binary sequences such as pseudo-random bi-nary sequences (PRBS-7, PRBS-15, PRBS-23 and PRBS-31) and a high data rate communication link also in the design. The link has been tested in the lab environment and two systems have successfully achieved a relatively low bit-error rate.
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Gray, Carl Edward. "An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44858.

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This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.
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McKechnie, Paul Edward. "Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems." Thesis, University of Glasgow, 2010. http://theses.gla.ac.uk/1879/.

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As networks become more versatile, the computational requirement for supporting additional functionality increases. The increasing demands of these networks can be met by Field Programmable Gate Arrays (FPGA), which are an increasingly popular technology for implementing packet processing systems. The fine-grained parallelism and density of these devices can be exploited to meet the computational requirements and implement complex systems on a single chip. However, the increasing complexity of FPGA-based systems makes them susceptible to errors and difficult to test and debug. To tackle the complexity of modern designs, system-level languages have been developed to provide abstractions suited to the domain of the target system. Unfortunately, the lack of formality in these languages can give rise to errors that are not caught until late in the design cycle. This thesis presents three techniques for verifying and validating FPGA-based packet processing systems described in a system-level description language. First, a type system is applied to the system description language to detect errors before implementation. Second, system-level transaction monitoring is used to observe high-level events on-chip following implementation. Third, the high-level information embodied in the system description language is exploited to allow the system to be automatically instrumented for on-chip monitoring. This thesis demonstrates that these techniques catch errors which are undetected by traditional verification and validation tools. The locations of faults are specified and errors are caught earlier in the design flow, which saves time by reducing synthesis iterations.
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Khan, Habib ul Hasan [Verfasser], Diana [Gutachter] Göhringer, and Heinrich Theodor [Gutachter] Vierhaus. "Automated Debugging Methodology for FPGA-based Systems / Habib ul Hasan Khan ; Gutachter: Diana Göhringer, Heinrich Theodor Vierhaus." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/1230578358/34.

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Vyas, Dhaval N. "FPGA-based hardware accelerator design for performance improvement of a system-on-a-chip application." Diss., Online access via UMI:, 2005.

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Habbestad, Torstein. "An FPGA-based implementation of the Conjugate Gradient Method used to solve Large Dense Systems of Linear Equations." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-15403.

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To find the solution to large dense systems have always been a very time consuming problem, this thesis tries to accelerate this problem by implementing an highly pipelined conjugate gradient method on an FPGA, it has been used to solve dense systems of linear equations and has been tested and compared to a software version of the algorithm. The FPGA where capable of utilizing 90 % of the available memory bandwidth, in addition it is shown that the FPGA implemented Conjugate Gradient Method can be 30x faster compared to a custom made Conjugate Gradient method in software.
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MEHROTRA, RAHUL. "INVESTIGATION OF A HIGH-SPEED FPGA-BASED ARCHITECTURE TO SOLVE LINEAR SYSTEMS OF EQUATIONS USING THE JACOBI METHOD." University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1188583326.

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Amsaad, Fathi Hassan Mohamed. "A Trusted and Efficient Security Approach for the Detection of Hardware Trojans and Authentication of FPGA-based Systems." University of Toledo / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1512494875469127.

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Kini, Akshatha Jagannath. "Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems." Thesis, Virginia Tech, 2018. http://hdl.handle.net/10919/82666.

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Unmanned Aerial Systems (UAS) are aircraft without a human pilot on board. They are comprised of a ground-based autonomous or human operated control system, an unmanned aerial vehicle (UAV) and a communication, command and control (C3) link between the two systems. UAS are widely used in military warfare, wildfire mapping, aerial photography, etc primarily to collect and process large amounts of data. While they are highly efficient in data collection and processing, they are susceptible to software espionage and data manipulation. This research aims to provide a novel solution to enhance the security of the flight controller thereby contributing to a secure and robust UAS. The proposed solution begins by introducing a new technology in the domain of flight controllers and how it can be leveraged to overcome the limitations of current flight controllers. The idea is to decouple the applications running on the flight controller from the task of data validation. The authenticity of all external data processed by the flight controller can be checked without any additional overheads on the flight controller, allowing it to focus on more important tasks. To achieve this, we introduce an adjacent controller whose sole purpose is to verify the integrity of the sensor data. The controller is designed using minimal resources from the reconfigurable logic of an FPGA. The secondary I/O processor is implemented on an incipient Zynq SoC based flight controller. The soft-core microprocessor running on the configurable logic of the FPGA serves as a first level check on the sensor data coming into the flight controller thereby forming a trusted boundary layer.
Master of Science
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Meder, Lukas Dominik [Verfasser], and J. [Akademischer Betreuer] Becker. "Timing Synchronization and Fast-Control for FPGA-based large-scale Readout and Processing Systems / Lukas Dominik Meder ; Betreuer: J. Becker." Karlsruhe : KIT-Bibliothek, 2017. http://d-nb.info/1136021841/34.

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Gebhardt, Pierre Klaus. "Design and investigation of an FPGA-based data acquisition and control architecture with MRI RF interference reduction capabilities for simultaneous PET/MRI systems." Thesis, King's College London (University of London), 2017. https://kclpure.kcl.ac.uk/portal/en/theses/design-and-investigation-of-an-fpgabased-data-acquisition-and-control-architecture-with-mri-rf-interference-reduction-capabilities-for-simultaneous-petmri-systems(20109be2-4865-47da-9b90-2ad80a54c85e).html.

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The combination of Positron Emission Tomography (PET) and Magnetic Resonance Imaging (MRI) as a multi-modality imaging technique allows the simultaneous acquisition of information about metabolic processes with very sensitivity from PET, and high-resolution anatomical or functional MR images with an excellent soft-tissue contrast from MRI. However, the design of PET/MRI systems providing an unaffected PET and MRI performance during simultaneous operation is challenging. An integration and operation of PET with a large field of view for clinical whole-body imaging can be realised through the use of semiconductorbased photo-detectors which are MR-compatible and very small compared to conventional photo-detectors. PET systems based on these new photo-detector require a dramatically higher, typically two orders of magnitude, number of detector channels to be read out by the PET acquisition system. The latter are usually designed for particular systems and are not based on architectural approaches to be easily adaptable to different detector configurations. The first aim of this thesis was to conceive a PET data acquisition architecture with concepts offering a high level of flexibility in order to meet the requirements of current and future, preclinical and clinical PET and PET/MRI detector configurations using semiconductor photo-detectors. This architecture was implemented for two preclinical PET inserts, Hyperion I and Hyperion IID, designed for simultaneous PET/MRI. The second system uses the latest detector technology known as the digital SiPM (made by Philips). The PET data acquisition platform design for Hyperion IID as well as investigations in the data transmission stability under different PET and PET/MRI operating conditions are presented. PET detectors operated in an MRI bore commonly use radio-frequency (RF) shielding to reduce PET-related RF interference and hence preserve the MR image quality. However, shields require conducting materials which give rise to eddy currents within the switching MRI fields. These eddy currents lead to local MRI field disturbances and thus MR image artefacts. The drawbacks could be avoided by operating a PET system without RF shielding, which would, however, require the PET system not to couple spurious RF signals into the MRI RF signal receive coil. The second objective of the thesis was therefore to exploit the novel capabilities of the new data acquisition system and modify the RF emissions from the PET electronics in such ways that the RF noise coupling into the MRI coil can be lowered. Three different RF interference reduction (IR) techniques are proposed which are based on rmware of field-programmable gate array (FPGA) devices, thereby offering RF IR modifications at any time compared to permanently mounted PET shields. The techniques were studied by performing simulations PET and MRI measurements. The thesis closes with PET/MRI in vivo and ex vivo measurement results to demonstrate the feasibility and stability of the data acquisition system and the imaging capabilities of Hyperion IID.
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El-Hassan, Fadi. "Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems." Thèse, Université d'Ottawa / University of Ottawa, 2014. http://hdl.handle.net/10393/30660.

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Abstract:
The dissemination of various types of data faces ongoing challenges with the growing need of accessing manifold information. Since the interest in content is what drives data networks, some new technologies and thoughts attempt to cope with these challenges by developing content-based rather than address-based architectures. The Publish/ Subscribe paradigm can be a promising approach toward content-based data dissemination, especially that it provides total decoupling between publishers and subscribers. However, in content-based publish/subscribe systems, subscriptions are expressive and the information is often delivered based on the matched expressive content - which may not deeply alleviate considerable performance challenges. This dissertation explores a hardware solution for disseminating data in content-based publish/subscribe systems. This solution consists of an efficient hardware architecture of an XML/XPath broker that can route information based on content to either other XML/XPath brokers or to ultimate users. A network of such brokers represent an overlay structure for XML content-based publish/subscribe data dissemination systems. Each broker can simultaneously process many XPath subscriptions, efficiently parse XML publications, and subsequently forward notifications that result from high-performance matching processes. In the core of the broker architecture, locates an XML parser that utilizes a novel Skeleton CAM-Based XML Parsing (SCBXP) technique in addition to an XPath processor and a high-performance matching engine. Moreover, the broker employs effective mechanisms for content-based routing, so as subscriptions, publications, and notifications are routed through the network based on content. The inherent reconfigurability feature of the broker’s hardware provides the system architecture with the capability of residing in any FPGA device of moderate logic density. Furthermore, such a system-on-chip architecture is upgradable, if any future hardware add-ons are needed. However, the current architecture is mature and can effectively be implemented on an ASIC device. Finally, this thesis presents and analyzes the experiments conducted on an FPGA prototype implementation of the proposed broker/router. The experiments tackle tests for the SCBXP alone and for two phases of development of the whole broker. The corresponding results indicate the high performance that the involved parsing, storing, matching, and routing processes can achieve.
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