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Journal articles on the topic 'FPGA-Based systems'

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Published: 9 March 2023

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1

MELNYK, A., and V. MELNYK. "Self-Configurable FPGA-Based Computer Systems." Advances in Electrical and Computer Engineering 13, no. 2 (2013): 33–38. http://dx.doi.org/10.4316/aece.2013.02005.

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2

Sahar, Abdelhedi. "Fall Detection FPGA-Based Systems: A Survey." International Journal of Automation and Smart Technology 6, no. 4 (December 1, 2016): 191–202. http://dx.doi.org/10.5875/ausmt.v6i4.1105.

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3

Kassas, Zaher M. "Methodologies for Implementing FPGA-Based Control Systems." IFAC Proceedings Volumes 44, no. 1 (January 2011): 9911–16. http://dx.doi.org/10.3182/20110828-6-it-1002.00783.

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4

Ivanov, V. K., and E. V. Nosov. "Serial communication protocol for FPGA-based systems." Journal of Physics: Conference Series 1326 (October 2019): 012044. http://dx.doi.org/10.1088/1742-6596/1326/1/012044.

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5

SKLYAROV, V. "HARDWARE/SOFTWARE MODELING OF FPGA-BASED SYSTEMS." Parallel Algorithms and Applications 17, no. 1 (January 2002): 19–39. http://dx.doi.org/10.1080/10637190208941432.

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6

Montone, A., M. D. Santambrogio, F. Redaelli, and D. Sciuto. "Floorplacement for Partial Reconfigurable FPGA-Based Systems." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/483681.

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We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based onexternal wirelength. Our work aims at identifying groups ofReconfigurable Functional Unitsthat are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).
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Huffmire, Ted, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy Levin, Thuy D. Nguyen, and Cynthia Irvine. "Managing Security in FPGA-Based Embedded Systems." IEEE Design & Test of Computers 25, no. 6 (November 2008): 590–98. http://dx.doi.org/10.1109/mdt.2008.166.

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8

Dandalis, A., and V. K. Prasanna. "Configuration compression for FPGA-based embedded systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 12 (December 2005): 1394–98. http://dx.doi.org/10.1109/tvlsi.2005.862721.

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9

Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. "Dynamic Reliability Management for FPGA-Based Systems." International Journal of Reconfigurable Computing 2020 (June 13, 2020): 1–19. http://dx.doi.org/10.1155/2020/2808710.

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Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.
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10

Chen, Fu Long, Zhao Xia Zhu, and Xiao Ya Fan. "FPGA-Based In-Circuit Verification of Digital Systems." Advanced Materials Research 187 (February 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.

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In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.
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11

Ttofis, Christos, Theocharis Theocharides, and Maria K. Michael. "FPGA-Based Laboratory Assignments for NoC-Based Manycore Systems." IEEE Transactions on Education 55, no. 2 (May 2012): 180–89. http://dx.doi.org/10.1109/te.2011.2159795.

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12

Melnyk, Viktor. "Self-Configurable FPGA-Based Computer Systems: Basics and Proof of Concept." Advances in Cyber-Physical Systems 1, no. 1 (February 23, 2016): 39–50. http://dx.doi.org/10.23939/acps2016.01.039.

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13

Lindoso, Almudena, and Luis Entrena. "High performance FPGA-based image correlation." Journal of Real-Time Image Processing 2, no. 4 (December 2007): 223–33. http://dx.doi.org/10.1007/s11554-007-0066-5.

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14

Zabołotny, W. M. "QEMU-based hardware/software co-development for DAQ systems." Journal of Instrumentation 17, no. 04 (April 1, 2022): C04004. http://dx.doi.org/10.1088/1748-0221/17/04/c04004.

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Abstract Modern DAQ systems typically use the FPGA-based PCIe cards to concentrate and deliver the data to a computer used as an entry node of the data processing network. This paper presents a QEMU-based methodology for the co-development of the FPGA-based hardware part, the Linux kernel driver, and the data receiving application. This approach enables quick verification of the FPGA firmware architecture, organization of control registers, the functionality of the driver, and the user-space application. The developed design may be tested in different emulated architectures with a changeable CPU, IOMMU, size of memory, and the number of DAQ cards.
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15

Vo, Hai Hong, Hung Quoc Nguyen, and Tuyet Kim Tran. "Development of triggering and DAQ systems for radiation detectors using FPGA technology." Science and Technology Development Journal - Natural Sciences 1, T4 (December 31, 2017): 197–204. http://dx.doi.org/10.32508/stdjns.v1it4.481.

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Field-programmable gate array (FPGA) technology has been widely used in setting up triggering systems and DAQ systems for radiation detectors, because it has several advantages such as fast digital processing, compact, programmable and high stability. Since 2010, with we have developed FPGA-based trigger systems and FPGA-based DAQ systems used for radiation detectors. Triggering systems for cosmic ray measurements, readout electronic for environmental radiation monitor in air. We also developed nuclear electronic equipment such as spectrum analyzer MCA (Flash-ADC/FPGA based), the pulse generator, counters, readout electronic for multiple radiation sensors. In this paper, we present two experiments, on the cosmic-ray induced response on the NaI(Tl) detector and environmental radiation monitoring system. For those experiments, trigger system are built by FPGA-based technology.
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16

Węgrzyn, Mariusz, and Janusz Sosnowski. "Tracing Fault Effects in FPGA Systems." International Journal of Electronics and Telecommunications 60, no. 1 (March 1, 2014): 92–97. http://dx.doi.org/10.2478/eletel-2014-0012.

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Abstract The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets - SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.
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17

Nasser, Fadi T., and Ivan A. Hashim. "Power optimization of binary division based on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (December 1, 2021): 1354. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1354-1366.

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In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.
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18

An, Xin, Eric Rutten, Jean-Philippe Diguet, Nicolas le Griguer, and Abdoulaye Gamatié. "Discrete Control for Reconfigurable FPGA-based Embedded Systems*." IFAC Proceedings Volumes 46, no. 22 (2013): 151–56. http://dx.doi.org/10.3182/20130904-3-uk-4041.00017.

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19

Zhang, Jiliang, and Gang Qu. "Recent Attacks and Defenses on FPGA-based Systems." ACM Transactions on Reconfigurable Technology and Systems 12, no. 3 (September 25, 2019): 1–24. http://dx.doi.org/10.1145/3340557.

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20

DIESSEL, OLIVER, and HOSSAM ELGINDY. "ON DYNAMIC TASK SCHEDULING FOR FPGA-BASED SYSTEMS." International Journal of Foundations of Computer Science 12, no. 05 (October 2001): 645–69. http://dx.doi.org/10.1142/s0129054101000709.

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The development of FPGAs that can be programmed to implement custom circuits by modifying memory has inspired researchers to investigate how FPGAs can be used as a computational resource in systems designed for high performance applications. When such FPGA–based systems are composed of arrays of chips or chips that can be partially reconfigured, the programmable array space can be partitioned among several concurrently executing tasks. If partition sizes are adapted to the needs of tasks, then array resources become fragmented as tasks with varying requirements are processed. Tasks may end up waiting despite their being sufficient, albeit fragmented resources available. We examine the problem of repartitioning the system (rearranging a subset of the executing tasks) at run–time in order to allow waiting tasks to enter the system sooner. In this paper, we introduce the problems of identifying and scheduling feasible task rearrangements when tasks are moved by reloading. It is shown that both problems are NP–complete. We develop two very different heuristic approaches to finding and scheduling suitable rearrangements. The first method, known as Local Repacking, attempts to minimize the size of the subarray needing rearrangement. Candidate subarrays are repacked using known bin packing algorithms. Task movements are scheduled so as to minimize delays to their execution. The second approach, called Ordered Compaction, constrains the movements of tasks in order to efficiently identify and schedule feasible rearrangements. The heuristics are compared by time complexity and resulting system performance on simulated task sets. The results indicate that considerable scheduling advantages are to be gained for acceptable computational effort. However, the benefits may be jeopardized by delays to moving tasks when the average cost of reloading tasks becomes significant relative to task service periods. We indicate directions for future research to mitigate the cost of moving executing tasks.
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21

Edwards, Stephen A. "Experiences teaching an FPGA-based embedded systems class." ACM SIGBED Review 2, no. 4 (October 2005): 56–62. http://dx.doi.org/10.1145/1121812.1121823.

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22

Rodriguez-Araujo, J., J. J. Rodriguez-Andina, J. Farina, F. Vidal, J. L. Mato, and M. A. Montealegre. "Industrial Laser Cladding Systems: FPGA-Based Adaptive Control." IEEE Industrial Electronics Magazine 6, no. 4 (December 2012): 35–46. http://dx.doi.org/10.1109/mie.2012.2221356.

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23

Wegrzyn, Marek. "FPGA-Based Logic Controllers for Safety Critical Systems." IFAC Proceedings Volumes 34, no. 22 (November 2001): 584–89. http://dx.doi.org/10.1016/s1474-6670(17)33003-3.

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24

Koch, Dirk, Christian Beckhoff, and Jürgen Teich. "Hardware Decompression Techniques for FPGA-Based Embedded Systems." ACM Transactions on Reconfigurable Technology and Systems 2, no. 2 (June 2009): 1–23. http://dx.doi.org/10.1145/1534916.1534919.

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25

Buchenrieder, K., R. Kress, A. Pyttel, A. Sedlmeier, and C. Veith. "FPGA-based parallel ASIP architecture for reactive systems." Electronics Letters 33, no. 10 (1997): 842. http://dx.doi.org/10.1049/el:19970555.

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26

Lei, Neng Fang. "The Design of Digital Communication System Based on FPGA." Applied Mechanics and Materials 687-691 (November 2014): 3093–96. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3093.

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The paper investigates the Multi-FPGA systems structure, including interconnect and configuration structure of the systems. After analyzing several common FPGA systems interconnection structure, we present its features. The paper analyses the feasibility and technical advantages for FPGA systems to use in digital array radar receiver design, and discusses their specific implementation, and designs a set of IF receiver with twenty reception elements.
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27

Sharma, Upasana, and Shampa Chakraverty. "A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems." International Journal of Engineering and Technology 4, no. 6 (2012): 821–25. http://dx.doi.org/10.7763/ijet.2012.v4.492.

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28

Juhász, László, and Jürgen Maas. "Fpga-based control of piezoelectric actuators." Serbian Journal of Electrical Engineering 8, no. 2 (2011): 181–201. http://dx.doi.org/10.2298/sjee1102181j.

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In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 ?m/s up to 5 cm/s are given.
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29

Kieu-Do-Nguyen, Binh, Cuong Pham-Quoc, and Cong-Kha Pham. "High-Performance FPGA-Based BWA-MEM Accelerator." International Journal of Machine Learning and Computing 11, no. 3 (May 2021): 256–61. http://dx.doi.org/10.18178/ijmlc.2021.11.3.1044.

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There is no denying that Bioinformatics is one of the most important realms for our forthcoming development. As a demonstration of this fact, a plethora of new algorithms that were published over the last decade. Those significantly boost up the processes of biological analysis, especially for DNA alignment. Despite their undeniable contributions, it is still far more to state that DNA alignment has already achieved the ideal performance. In this work, we focus on the DNA alignment system which is based on our improved BWA-MEM algorithm that we have already published. Besides that, we also propose some optimization methods which was applied in order to improve the performance as well as the stability of our entire system. The system offers a speed-up by 46.52x when compared with the other computing platforms.
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30

Smekal, David, Frantisek Nemeth, and Jan Dvorak. "An FPGA-based Priority Packet Queues." IFAC-PapersOnLine 52, no. 27 (2019): 377–81. http://dx.doi.org/10.1016/j.ifacol.2019.12.689.

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31

Dai, Yan. "Design FFT Processor Based on FPGA." International Journal of Control and Automation 9, no. 11 (November 30, 2016): 137–42. http://dx.doi.org/10.14257/ijca.2016.9.11.12.

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32

Hilgurt, Sergii. "Parallel Combining Different Approaches to Multi-pattern Matching for Fpga-based Security Systems." Advances in Cyber-Physical Systems 5, no. 1 (November 28, 2017): 8–15. http://dx.doi.org/10.23939/acps2020.01.008.

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The multi-pattern matching is a fundamental technique found in applications like a network intrusion detection system, anti-virus, anti-worms and other signature- based information security tools. Due to rising traffic rates, increasing number and sophistication of attacks and the collapse of Moore’s law, traditional software solutions can no longer keep up. Therefore, hardware approaches are frequently being used by developers to accelerate pattern matching. Reconfigurable FPGA-based devices, providing the flexibility of software and the near-ASIC performance, have become increasingly popular for this purpose. Hence, increasing the efficiency of reconfigurable information security tools is a scientific issue now. Many different approaches to constructing hardware matching circuits on FPGAs are known. The most widely used of them are based on discrete comparators, hash-functions and finite automata. Each approach possesses its own pros and cons. None of them still became the leading one. In this paper, a method to combine several different approaches to enforce their advantages has been developed. An analytical technique to quickly advance estimate the resource costs of each matching scheme without need to compile FPGA project has been proposed. It allows to apply optimization procedures to near-optimally split the set of pattern between different approaches in acceptable time.
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33

Levin, Il’ya, Aleksey Dordopulo, Yuriy Doronchenko, Maksim Raskladkin, and Aleksandr Fedorov. "Immersion cooling system for FPGA-based reconfigurable computer systems." Program Systems: Theory and Applications 7, no. 4 (2016): 65–81. http://dx.doi.org/10.25209/2079-3316-2016-7-4-65-81.

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34

Masselos, K., and N. S. Voros. "Implementation of Wireless Communications Systems on FPGA-Based Platforms." EURASIP Journal on Embedded Systems 2007 (2007): 1–9. http://dx.doi.org/10.1155/2007/12192.

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35

Giaconia, G. C., A. Di Stefano, and G. Capponi. "FPGA-based concurrent watchdog for real-time control systems." Electronics Letters 39, no. 10 (2003): 769. http://dx.doi.org/10.1049/el:20030538.

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36

Szász, Csaba. "Modeling and simulation of FPGA-based redundant digital systems." International Review of Applied Sciences and Engineering 11, no. 1 (April 2020): 73–79. http://dx.doi.org/10.1556/1848.2020.00011.

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AbstractReliability is one of the most important criteria that characterize last generation digital systems. In a wide range of applications the required reliability level is achieved by using hardware redundant configurations. Perhaps their most common form is the triple modular redundancy (TMR) based on a majority voting structure. Researchers that use this strategy make a major assumption: in fault-free operation mode the outputs of these digital systems match in all. This paper proves that synchronization and matching in all the outputs of such systems is not such a trivial problem. In this endeavor FPGA-based (Field Programmable Gate Arrays) redundant topologies are considered for study and experiments. Upon these structures specially conceived redundant models have been developed and simulated. The results outline that synchronization of complex digital systems is a difficult engineering undertaking and any initial assumption should be managed with the adequate circumspection.
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37

Masselos, K., and NS Voros. "Implementation of Wireless Communications Systems on FPGA-Based Platforms." EURASIP Journal on Embedded Systems 2007, no. 1 (2007): 012192. http://dx.doi.org/10.1186/1687-3963-2007-012192.

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38

Sahamijoo, Amirzubir, Farzin Piltan, Hootan Ghiasi, Mohammad Reza Avazpour, Mohammad Hadi Mazloom, and Nasri B. Sulaiman. "Design SPARTAN FPGA-Based PD Controller for FOD Systems." International Journal of Smart Home 10, no. 11 (November 30, 2016): 177–96. http://dx.doi.org/10.14257/ijsh.2016.10.11.16.

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39

Kapre, Nachiket. "Optimizing Soft Vector Processing in FPGA-Based Embedded Systems." ACM Transactions on Reconfigurable Technology and Systems 9, no. 3 (September 12, 2016): 1–17. http://dx.doi.org/10.1145/2912884.

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40

Beltrán, Marta, Antonio Guzmán, and Fernando Sevillano. "High level performance metrics for FPGA-based multiprocessor systems." Performance Evaluation 67, no. 6 (June 2010): 417–31. http://dx.doi.org/10.1016/j.peva.2009.12.004.

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41

Krákora, Jan, and Zdeněk Hanzálek. "FPGA based tester tool for hybrid real-time systems." Microprocessors and Microsystems 32, no. 8 (November 2008): 447–59. http://dx.doi.org/10.1016/j.micpro.2008.07.003.

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42

Alabdo, Aiman, Javier Pérez, Gabriel J. Garcia, Jorge Pomares, and Fernando Torres. "FPGA-based architecture for direct visual control robotic systems." Mechatronics 39 (November 2016): 204–16. http://dx.doi.org/10.1016/j.mechatronics.2016.05.008.

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43

Bradáč, Z., and S. Valach. "10G bit ethernet phy implementation in FPGA based systems." IFAC Proceedings Volumes 39, no. 21 (February 2006): 427–32. http://dx.doi.org/10.1016/s1474-6670(17)30224-0.

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44

Akoglu, Ali, Adarsha Sreeramareddy, and Jeff G. Josiah. "FPGA based distributed self healing architecture for reusable systems." Cluster Computing 12, no. 3 (February 6, 2009): 269–84. http://dx.doi.org/10.1007/s10586-009-0082-2.

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45

Kadhim, Abdul-Karim A. R., and Abdul-Aziz A. Hussain. "Hierarchical matched filter based on FPGA for mobile systems." Computers & Electrical Engineering 35, no. 4 (July 2009): 549–55. http://dx.doi.org/10.1016/j.compeleceng.2008.08.006.

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46

Tempesti, Gianluca, Daniel Mange, and André Stauffer. "A robust multiplexer-based FPGA inspired by biological systems." Journal of Systems Architecture 43, no. 10 (January 1997): 719–33. http://dx.doi.org/10.1016/s1383-7621(94)00312-2.

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47

Mazloom, Mohammad Hadi, Farzin Piltan, Amirzubir Sahamijoo, Hootan Ghiasi, Mohammad Reza Avazpour, and Nasri B. Sulaiman. "Design PD Functional Based FPGA Controller for FOD Systems." International Journal of Hybrid Information Technology 10, no. 1 (January 31, 2017): 361–76. http://dx.doi.org/10.14257/ijhit.2017.10.1.30.

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48

Shreejith, Shanker, and Suhaib A. Fahmy. "Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems." IEEE Transactions on Vehicular Technology 64, no. 2 (February 2015): 453–65. http://dx.doi.org/10.1109/tvt.2014.2324532.

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49

Agnesina, Anthony, Sung Kyu Lim, Etienne Lepercq, and Jose Escobedo Del Cid. "Improving FPGA-Based Logic Emulation Systems through Machine Learning." ACM Transactions on Design Automation of Electronic Systems 25, no. 5 (October 2, 2020): 1–20. http://dx.doi.org/10.1145/3399595.

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50

Zou, Ding, Changyu Lin, and Ivan B. Djordjevic. "FPGA-based LDPC-coded APSK for optical communication systems." Optics Express 25, no. 4 (February 6, 2017): 3133. http://dx.doi.org/10.1364/oe.25.003133.

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