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Relevant bibliographies by topics / FPGA Encryption

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Journal articles
Dissertations / Theses
Book chapters
Conference papers

Academic literature on the topic 'FPGA Encryption'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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Journal articles on the topic "FPGA Encryption"

1

Mahmood, Zainab H., and Mahmood K. Ibrahem. "HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV." Iraqi Journal of Information & Communications Technology 2, no. 2 (November 1, 2019): 44–57. http://dx.doi.org/10.31987/ijict.2.2.69.

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

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Yang, Cheng-Hsiung, and Yu-Sheng Chien. "FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm." Symmetry 12, no. 2 (January 22, 2020): 189. http://dx.doi.org/10.3390/sym12020189.

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In this paper, we propose an image encryption algorithm based on four-dimensional chaotic system to generate key and improve advanced encryption standard. The encryption algorithm is optimized by using the pipeline and parallel computing features of Field Programmable Gate Array (FPGA). First, the chaotic system is used as a key generator for the encryption algorithm. Next, in the improved advanced encryption standard, ShiftRows and SubByres are modified with Spin-Sort and Cubic S-Box, and the round of encryption is reduced. We implement the encryption algorithm and the wired image transmission system to the ARM-based SoC-FPGA. The HPS software runs on Linux and is used to control the FPGA encryption algorithm and image transmission. Finally, the results from the encryption security analysis show that the proposed image encryption algorithm is safe and effective.

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Nayak, Nikhilesh, Akshay Chandak, Nisarg Shah, and B. Karthikeyan. "Encryption and decryption using FPGA." IOP Conference Series: Materials Science and Engineering 263 (November 2017): 052030. http://dx.doi.org/10.1088/1757-899x/263/5/052030.

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Gong, Yanping, Fengyu Qian, and Lei Wang. "Masked FPGA Bitstream Encryption via Partial Reconfiguration." International Journal of High Speed Electronics and Systems 28, no. 03n04 (September 2019): 1940022. http://dx.doi.org/10.1142/s0129156419400226.

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Field Programmable Gate Arrays (FPGA), as one of the popular circuit implementation platforms, provide the flexible and powerful way for different applications. IC designs are configured to FPGA through bitstream files. However, the configuration process can be hacked by side channel attacks (SCA) to acquire the critical design information, even under the protection of encryptions. Reports have shown many successful attacks against the FPGA cryptographic systems during the bitstream loading process to acquire the entire design. Current countermeasures, mostly random masking methods, are effective but also introduce large hardware complexity. They are not suitable for resource-constrained scenarios such as Internet of Things (IoT) applications. In this paper, we propose a new secure FPGA masking scheme to counter the SCA. By utilizing the FPGA partial reconfiguration feature, the proposed technique provides a light-weight and flexible solution for the FPGA decryption masking.

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Kumar Sahu, Sushanta, and Manoranjan Pradhan. "FPGA Implementation of RSA Encryption System." International Journal of Computer Applications 19, no. 9 (April 30, 2011): 10–12. http://dx.doi.org/10.5120/2391-3173.

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., Kumar Anubhav Tiwari. "FPGA BASED ENCRYPTION DESIGN USING VHDL." International Journal of Research in Engineering and Technology 03, no. 22 (June 25, 2014): 148–51. http://dx.doi.org/10.15623/ijret.2014.0322032.

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Hasan, Hind Ali Abdul, Safaa Maijd Mohammed, and Noor Hayder Abdul Ameer. "ADVANCED ENCRYPTION STANDARD USING FPGA OVERNETWORK." EUREKA: Physics and Engineering, no. 1 (January 29, 2021): 32–39. http://dx.doi.org/10.21303/2461-4262.2021.001613.

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The increase number of eavesdropping or cracker to attack the information and hack the privacy of people. So, the essential issue is making system capable of ciphering information with rapid speed. Due to the advance in computer eavesdropping and cracker that made them to analysis the way of ciphering in rapid speed way. The development in the computer especially in the rapid processer in the last decade create the breaching of any system is a matter of time. Owing to most of breaching ways are based on analysis of system that requireы to be breached and to try brute force on that system to crack it. However, the lacking of influential processers that are capable of breaching system since earlier processors are limit to number of instructions. It can be done in second, which was not sufficient trying to break the system using brute force. In addition, the time required is far away from getting valuable messages in the time that needed. So, the research gives the focus on performing rapid system for ciphering the information rapidly and changing the ciphering every few milliseconds. The changing of ciphering in every millisecond helps system form preventing the eavesdropping and cracker from imposing brute force on the system and hacking the messages and images. The system that created is based on Advanced Encryption Standard (AES), which is it very best performing algorithm in ciphering and deciphering since it doesn’t need complex mathematical formula. The research is about designing system that capable of performing AES by using high processer designed on Field programmable gate Area (FPGA). The ciphering of AES using FPGA helps minimize the time required to cipher the information. Also, the research will focus on ciphering and deciphering of images by AES using FPGA

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Zhao, Jin Hui, and Xiao Hong Wang. "Model of Video Encryption Based on FPGA." Advanced Materials Research 791-793 (September 2013): 1497–500. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.1497.

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On the Internet, most of media information is transmitted in plaintext. Some others can easily tamper or intercut the information, so there are threats to those information transmitted in plaintext. This paper designs a model of video encryption which uses AES algorithm and the model is based on FPGA platform. The model does the encryption in paralleling on XUPV5-110T development board. The encryption model can ensure the security and integrity of media information during the transmission process between a certain links on the network.

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Zeng, Rong, Xiu Li Huang, and Ya Dong Chen. "A High Rate Parallel Operation Encryption Card Design Base on FPGA." Applied Mechanics and Materials 668-669 (October 2014): 783–86. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.783.

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A design of encryption cards controlling multiple cipher chips’ high-rate parallel operation based on FPGA is proposed in this paper. According to the design method, we can achieve that multiple encryption card operates encryption in parallel way, which can improve the encryption and decryption rate of the encryption card without enhancing the performance of encryption chip, moreover, increase the key generation rate and management level of the key management system.

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Tang, Hong Wei. "32-bit Datapath AES IP Core Based on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 1848–51. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1848.

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This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.

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Dissertations / Theses on the topic "FPGA Encryption"

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Denning, Daniel. "Encryption systems for FPGA computing." Thesis, University of Glasgow, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438606.

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Sampath, Sowrirajan. "FPGA based Hardware Implementation of Advanced Encryption Standard." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736.

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KRISHNAN, AKHIL. "HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392.

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Svensson, Christian. "High-Speed Storage Encryption over Fibre Channel." Thesis, Linköpings universitet, Datorteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97043.

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This thesis focused on testing whether persistent encryption of Fibre Channel is doable and what kind of security it provides. It has been shown that intercepting, analysing and modifying Fibre Channel traﬃc is possible without any noticeable performance loss as long as latency is kept within certain boundaries. If latency are outside those boundaries extreme performance loss are to be expected. This latency demand puts further restrictions on the cryptography to be used. Two platforms were simulated, implemented and explained. One for intercepting and modifying Fibre Channel and one for analysing Fibre Channel traﬃc using Linux and Wireshark.

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Van, Dyken Jason Daniel. "Schemes to reduce power in FPGA implementations of the advanced encryption standard." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/J_Van_Dyken_111307.pdf.

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McDaniel, Larry T. III. "An Investigation of Differential Power Analysis Attacks on FPGA-based Encryption Systems." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/33451.

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Hardware devices implementing cryptographic algorithms are finding their way into many applications. As this happens, the ability to keep the data being processed or stored on the device secure grows more important. Power analysis attacks involve cryptographic hardware leaking information during encryption because power consumption is correlated to the key used for encryption. Power analysis attacks have proven successful against public and private key cryptosystems in a variety of form factors. The majority of the countermeasures that have been proposed for this attack are intended for software implementations on a microcontroller. This project focuses on the development of a VHDL tool for investigating power analysis attacks on FPGAs and exploring countermeasures that might be used. The tool developed here counted the transitions of CLB output signals to estimate power and was used to explore the impact of possible gate-level countermeasures to differential power analysis. Using this tool, it was found that only a few nodes in the circuit have a high correlation to bits of the key. This means that modifying only a small portion of the circuit could dramatically increase the difficulty of mounting a differential power analysis attack on the hardware. Further investigation of the correlation between CLB outputs and the key showed that a tradeoff exists between the amount of space required for decorrelation versus the amount of decorrelation that is desired, allowing a designer to determine the amount of correlation that can be removed for available space. Filtering of glitches on CLB output signals slightly reduced the amount of correlation each CLB had. Finally, a decorrelation circuit was proposed and shown capable of decorrelating flip-flop outputs of a CLB, which account for less than 10% of the CLB outputs signals.
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7

Graf, Jonathan. "A Key Management Architecture for Securing Off-Chip Data Transfers on an FPGA." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/34063.

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Data security is becoming ever more important in embedded and portable electronic devices. The sophistication of the analysis techniques used by attackers is amazingly advanced. Digital devices' external interfaces to memory and communications interfaces to other digital devices are vulnerable to malicious probing and examination. A hostile observer might be able to glean important details of a device's design from such an interface analysis. Defensive measures for protecting a device must therefore be even more sophisticated and robust. This thesis presents an architecture that acts as a secure wrapper around an embedded application on a Field Programmable Gate Array (FPGA). The architecture includes functional units that serve to authenticate a user over a secure serial interface, create a key with multiple layers of security, and encrypt an external memory interface using that key. In this way, the wrapper protects all of the digital interfaces of the embedded application from external analysis. Cryptographic methods built into the system include an RSA-related secure key exchange, the Secure Hash Algorithm, a certificate storage system, and the Data Encryption Standard algorithm in counter mode. The principles behind the encrypted external memory interface and the secure authentication interface can be adjusted as needed to form a secure wrapper for a wide variety of embedded FPGA applications.
Master of Science

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8

Joshi, Yogesh. "Hardware encryption of AES algorithm on Android platform." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1342731146.

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Huang, Jian Li Hao. "FPGA implementations of elliptic curve cryptography and Tate pairing over binary field." [Denton, Tex.] : University of North Texas, 2007. http://digital.library.unt.edu/permalink/meta-dc-3963.

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Abraham, Arya. "It is I: An Authentication System for a Reconfigurable Radio." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/34353.

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The security of a radio system hinges on its ability to effectively authenticate a user. This work proposes a two-factor authentication scheme using a token and a biometric. The users' access rights are determined during authentication and the users are served only those channels of data that they are privileged to receive. The strengths and the weaknesses of the implementation in reconfigurable hardware are identified. The capabilities of the scheme are put into perspective by comparing it to a high-end authentication system and by evaluating the use of standardized APIs and low-end authentication devices. Modifications to the system are suggested to improve the level of security the scheme provides. Finally, a baseline study is carried out to measure the data processing performance of a radio developed in reconfigurable hardware, which uses the proposed authentication scheme.
Master of Science

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Book chapters on the topic "FPGA Encryption"

1

Muehlberghuber, Michael, Christoph Keller, Frank K. Gürkaynak, and Norbert Felber. "FPGA-Based High-Speed Authenticated Encryption System." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 1–20. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_1.

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Akman, Yasin, and Tarık Yerlikaya. "Encryption Time Comparison of AES on FPGA and Computer." In Advances in Intelligent Systems and Computing, 317–24. Heidelberg: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00951-3_30.

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Yu, Yan, Bingbing Song, Xiaozhen Liu, Qun Ding, and Ziheng Yang. "Design of Data Encryption Transmission System Based on FPGA." In Advances in Intelligent Systems and Computing, 293–99. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07773-4_29.

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Chana, Pushpinder Kaur, Preeti Gupta, and Sanjiv Kumar. "Efficient Advanced Encryption Standard with Elevated Speed and FPGA Implementation." In Nanoelectronics, Circuits and Communication Systems, 95–105. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2854-5_10.

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McLoone, Máire, and John V. McCanny. "Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm." In Field-Programmable Logic and Applications, 152–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_16.

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Suratwala, Darshit, and Ganesh Rahate. "A Comparative VHDL Implementation of Advanced Encryption Standard Algorithm on FPGA." In Machine Learning for Predictive Analysis, 343–51. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7106-0_34.

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Saini, Rahul, Mayank Jain, Manish, and Kriti Suneja. "FPGA Based Design of Speech Encryption and Decryption for Secure Communication." In Communications in Computer and Information Science, 37–49. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-9671-1_3.

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Khazaal, Yasmine Mustafa, Khamis A. Zidan, and Fadhil Sahib Hasan. "FPGA Hardware Image Encryption Co-simulation Utilizing Hybrid LFSR and Chaos Maps." In Intelligent Systems and Networks, 487–98. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2094-2_59.

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9

Kerins, Tim, Emanuel Popovici, and William Marnane. "Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes." In Field Programmable Logic and Application, 74–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_10.

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Soudan, Bassel, Wael Adi, and Abdulrahman Hanoun. "IP Protection of FPGA Cores Through a Novel Public/Secret-Key Encryption Mechanism." In Secure System Design and Trustable Computing, 369–89. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14971-4_11.

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Conference papers on the topic "FPGA Encryption"

1

Leong, M. P., S. Z. M. Naziri, and S. Y. Perng. "Image encryption design using FPGA." In 2013 International Conference on Electrical, Electronics and System Engineering (ICEESE). IEEE, 2013. http://dx.doi.org/10.1109/iceese.2013.6895037.

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2

Trimberger, Stephen, Jason Moore, and Weiguang Lu. "Authenticated encryption for FPGA bitstreams." In the 19th ACM/SIGDA international symposium. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/1950413.1950432.

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Hiremath, Sujatha, and M. S. Suma. "Advanced Encryption Standard Implemented on FPGA." In 2009 Second International Conference on Computer and Electrical Engineering. IEEE, 2009. http://dx.doi.org/10.1109/iccee.2009.231.

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Abdellatif, Karim M., R. Chotin-Avot, and H. Mehrez. "Protecting FPGA bitstreams using authenticated encryption." In 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS). IEEE, 2013. http://dx.doi.org/10.1109/newcas.2013.6573635.

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Priya, S. Sridevi Sathya, P. Karthigai Kumar, N. M. SivaMangai, and V. Rejula. "FPGA implementation of efficient AES encryption." In 2015 International Conference on Innovations in Information,Embedded and Communication Systems (ICIIECS). IEEE, 2015. http://dx.doi.org/10.1109/iciiecs.2015.7193081.

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Bevi, A. Ruhan, S. S. V. Sheshu, and S. Malarvizhi. "FPGA based pipelined architecture for RC5 encryption." In 2012 Second International Conference on Digital Information and Communication Technology and it's Applications (DICTAP). IEEE, 2012. http://dx.doi.org/10.1109/dictap.2012.6215353.

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Kouser, Zabina, Manish Singhal, and Amit M. Joshi. "FPGA implementation of advanced Encryption Standard algorithm." In 2016 International Conference on Recent Advances and Innovations in Engineering (ICRAIE). IEEE, 2016. http://dx.doi.org/10.1109/icraie.2016.7939594.

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Kosug, Makiko, Masahiro Yasuda, and Akashi Satoh. "FPGA implementation of authenticated encryption algorithm Minalpher." In 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE). IEEE, 2015. http://dx.doi.org/10.1109/gcce.2015.7398679.

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Peng, GuanLi, and SongBai Zhu. "FPGA Implementation of AES Encryption Optimization Algorithm." In 2021 International Conference on Intelligent Transportation, Big Data & Smart City (ICITBS). IEEE, 2021. http://dx.doi.org/10.1109/icitbs53129.2021.00165.

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Bevi, A. Ruhan, S. S. V. Sheshu, and S. Malarvizhi. "FPGA based sliding window architecture for RC5 encryption." In the International Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2345396.2345496.

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