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Denning, Daniel. "Encryption systems for FPGA computing." Thesis, University of Glasgow, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438606.
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Sampath, Sowrirajan. "FPGA based Hardware Implementation of Advanced Encryption Standard." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736.
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KRISHNAN, AKHIL. "HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392.
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Svensson, Christian. "High-Speed Storage Encryption over Fibre Channel." Thesis, Linköpings universitet, Datorteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97043.
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This thesis focused on testing whether persistent encryption of Fibre Channel is doable and what kind of security it provides. It has been shown that intercepting, analysing and modifying Fibre Channel traffic is possible without any noticeable performance loss as long as latency is kept within certain boundaries. If latency are outside those boundaries extreme performance loss are to be expected. This latency demand puts further restrictions on the cryptography to be used. Two platforms were simulated, implemented and explained. One for intercepting and modifying Fibre Channel and one for analysing Fibre Channel traffic using Linux and Wireshark.
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Van, Dyken Jason Daniel. "Schemes to reduce power in FPGA implementations of the advanced encryption standard." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Fall2007/J_Van_Dyken_111307.pdf.
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McDaniel, Larry T. III. "An Investigation of Differential Power Analysis Attacks on FPGA-based Encryption Systems." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/33451.
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Hardware devices implementing cryptographic algorithms are finding their way into many applications. As this happens, the ability to keep the data being processed or stored on the device secure grows more important. Power analysis attacks involve cryptographic hardware leaking information during encryption because power consumption is correlated to the key used for encryption. Power analysis attacks have proven successful against public and private key cryptosystems in a variety of form factors. The majority of the countermeasures that have been proposed for this attack are intended for software implementations on a microcontroller. This project focuses on the development of a VHDL tool for investigating power analysis attacks on FPGAs and exploring countermeasures that might be used.
The tool developed here counted the transitions of CLB output signals to estimate power and was used to explore the impact of possible gate-level countermeasures to differential power analysis. Using this tool, it was found that only a few nodes in the circuit have a high correlation to bits of the key. This means that modifying only a small portion of the circuit could dramatically increase the difficulty of mounting a differential power analysis attack on the hardware. Further investigation of the correlation between CLB outputs and the key showed that a tradeoff exists between the amount of space required for decorrelation versus the amount of decorrelation that is desired, allowing a designer to determine the amount of correlation that can be removed for available space. Filtering of glitches on CLB output signals slightly reduced the amount of correlation each CLB had. Finally, a decorrelation circuit was proposed and shown capable of decorrelating flip-flop outputs of a CLB, which account for less than 10% of the CLB outputs signals.Master of Science
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Graf, Jonathan. "A Key Management Architecture for Securing Off-Chip Data Transfers on an FPGA." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/34063.
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Data security is becoming ever more important in embedded and portable electronic devices. The sophistication of the analysis techniques used by attackers is amazingly advanced. Digital devices' external interfaces to memory and communications interfaces to other digital devices are vulnerable to malicious probing and examination. A hostile observer might be able to glean important details of a device's design from such an interface analysis. Defensive measures for protecting a device must therefore be even more sophisticated and robust.
This thesis presents an architecture that acts as a secure wrapper around an embedded application on a Field Programmable Gate Array (FPGA). The architecture includes functional units that serve to authenticate a user over a secure serial interface, create a key with multiple layers of security, and encrypt an external memory interface using that key. In this way, the wrapper protects all of the digital interfaces of the embedded application from external analysis. Cryptographic methods built into the system include an RSA-related secure key exchange, the Secure Hash Algorithm, a certificate storage system, and the Data Encryption Standard algorithm in counter mode. The principles behind the encrypted external memory interface and the secure authentication interface can be adjusted as needed to form a secure wrapper for a wide variety of embedded FPGA applications.Master of Science
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Joshi, Yogesh. "Hardware encryption of AES algorithm on Android platform." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1342731146.
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Huang, Jian Li Hao. "FPGA implementations of elliptic curve cryptography and Tate pairing over binary field." [Denton, Tex.] : University of North Texas, 2007. http://digital.library.unt.edu/permalink/meta-dc-3963.
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Abraham, Arya. "It is I: An Authentication System for a Reconfigurable Radio." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/34353.
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The security of a radio system hinges on its ability to effectively authenticate a user. This work proposes a two-factor authentication scheme using a token and a biometric. The users' access rights are determined during authentication and the users are served only those channels of data that they are privileged to receive. The strengths and the weaknesses of the implementation in reconfigurable hardware are identified. The capabilities of the scheme are put into perspective by comparing it to a high-end authentication system and by evaluating the use of standardized APIs and low-end authentication devices. Modifications to the system are suggested to improve the level of security the scheme provides. Finally, a baseline study is carried out to measure the data processing performance of a radio developed in reconfigurable hardware, which uses the proposed authentication scheme.Master of Science
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Novotňák, Jiří. "Hardwarová akcelerace šifrování síťového provozu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237117.
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The aim of this thesis is to draft and implement high-speed encryptor of network trafic with throughput 10Gb/s in one way. It has been implementated for FPGA Xilinx Virtex5vlx155t placed on card COMBOv2-LXT. The encryption is based on AES algorithm using 128 bit key length. The security protokol is ESP in version for protokol IPv4. Design is fully synthesizable with tool Xilinx ISE 11.3, however it is not tested on real hardware. Tests in simulation works fine.
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Vetter, Jeff S., and Travis Cribbet. "THE DESIGN AND DEVELOPMENT OF THE PROTOTYPE ENHANCED FLIGHT TERMINATION SYSTEM." International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/605564.
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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, NevadaRange Safety Systems are used for destruction of a vehicle should a malfunction cause the vehicle to veer off course. All vehicles launched into space require implementation of a Range Safety System. For years the IRIG receivers have been used with relatively good success. Unfortunately, the IRIG receivers do not provide a high level of security. High alphabet receivers were later developed for use on the big launchers (Atlas, Delta, Titan, etc) and the manned missions (Shuttle) to provide added security. With the IRIG based system, several problems have occurred resulting in the loss millions of dollars worth of equipment. Due to the problems that have occurred it has become apparent that there is a need for a more secure, low cost, type of range safety receiver. This paper describes the design and development of the prototype EFTS system. Mission critical parameters are discussed including selection of the encryption and forward error correction algorithms. Actual measured performance including message error rate characteristic is presented.
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Bengtz, Gustaf. "Analysis of new and alternative encryption algorithms and scrambling methods for digital-tv and implementation of a new scrambling algorithm (AES128) on FPGA." Thesis, Linköpings universitet, Institutionen för systemteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111112.
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This report adresses why the currently used scrambling standard CSA needs a replacement. Proposed replacements to CSA are analyzed to some extent, and an alternative replacement (AES128) is analyzed. One alternative being the CSA3, and the other being the CISSA algorithm. Both of the proposed algorithms use the AES algorithm as a base. The CSA3 combines AES128 with a secret cipher, the XRC, while CISSA uses the AES cipher in a feedback mode. The different utilizations makes CSA3 hardware friendly and CISSA software friendly. The implementation of the Advanced Encryption Standard (AES) is analyzed for a 128 bit key length based design, and a specific implementation is presented.
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Adamo, Oluwayomi Bamidele. "VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5393/.
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This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or scanners etc. To address such issues, a novel approach and its architecture in the framework of a digital camera, conceptualized as an SDC is presented. The SDC inserts biometric data into passport image with the aid of watermarking and encryption processes. The VLSI (very large scale integration) architecture of the functional units of the SDC such as watermarking and encryption unit is presented. The result of the hardware implementation of Rijndael advanced encryption standard (AES) and a discrete cosine transform (DCT) based visible and invisible watermarking algorithm is presented. The prototype chip can carry out simultaneous encryption and watermarking, which to our knowledge is the first of its kind. The encryption unit has a throughput of 500 Mbit/s and the visible and invisible watermarking unit has a max frequency of 96.31 MHz and 256 MHz respectively.
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Huang, Jian. "FPGA Implementations of Elliptic Curve Cryptography and Tate Pairing over Binary Field." Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc3963/.
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Elliptic curve cryptography (ECC) is an alternative to traditional techniques for public key cryptography. It offers smaller key size without sacrificing security level. Tate pairing is a bilinear map used in identity based cryptography schemes. In a typical elliptic curve cryptosystem, elliptic curve point multiplication is the most computationally expensive component. Similarly, Tate pairing is also quite computationally expensive. Therefore, it is more attractive to implement the ECC and Tate pairing using hardware than using software. The bases of both ECC and Tate pairing are Galois field arithmetic units. In this thesis, I propose the FPGA implementations of the elliptic curve point multiplication in GF (2283) as well as Tate pairing computation on supersingular elliptic curve in GF (2283). I have designed and synthesized the elliptic curve point multiplication and Tate pairing module using Xilinx's FPGA, as well as synthesized all the Galois arithmetic units used in the designs. Experimental results demonstrate that the FPGA implementation can speedup the elliptic curve point multiplication by 31.6 times compared to software based implementation. The results also demonstrate that the FPGA implementation can speedup the Tate pairing computation by 152 times compared to software based implementation.
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Lien, E.-Jen. "EFFICIENT IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOGRAPHY IN RECONFIGURABLE HARDWARE." Case Western Reserve University School of Graduate Studies / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=case1333761904.
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Kožený, Petr. "Implementace šifrovacích algoritmů v jazyku VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235444.
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This thesis deals with design and implementation of AES and DES encryption architectures for embedded systems. Architectures are implemented in VHDL language and design for FPGA technology. The proposed implementations are mapped on the Xilinx Spartan 3 technology. Both architectures are applied in simple ECB (Electronic Codebook) scheme with cache memories. A maximum throughput of design DES architecture 370 Mbps is achived with clock frequency of 104 MHz. The throughput of AES architecture at the maximum clock frequency of 118 MHz is 228 Mbps. Compared to software implementations for embedded systems, we achieve significantly higher throughput for both architectures.
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Cherif, Zouha. "Modelling and characterization of physically unclonable functions." Thesis, Saint-Etienne, 2014. http://www.theses.fr/2014STET4005/document.
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Les fonctions non clonables physiquement, appelées PUF (Physically Unclonable Functions), représentent une technologie innovante qui permet de résoudre certains problèmes de sécurité et d’identification. Comme pour les empreintes humaines, les PUF permettent de différencier des circuits électroniques car chaque exemplaire produit une signature unique. Ces fonctions peuvent être utilisées pour des applications telles que l’authentification et la génération de clés cryptographiques. La propriété principale que l’on cherche à obtenir avec les PUF est la génération d’une réponse unique qui varie de façon aléatoire d’un circuit à un autre, sans la possibilité de la prédire. Une autre propriété de ces PUF est de toujours reproduire, quel que soit la variation de l’environnement de test, la même réponse à un même défi d’entrée. En plus, une fonction PUF doit être sécurisée contre les attaques qui permettraient de révéler sa réponse. Dans cette thèse, nous nous intéressons aux PUF en silicium profitant des variations inhérentes aux technologies de fabrication des circuits intégrés CMOS. Nous présentons les principales architectures de PUF, leurs propriétés, et les techniques mises en œuvre pour les utiliser dans des applications de sécurité. Nous présentons d’abord deux nouvelles structures de PUF. La première structure appelée “Loop PUF” est basée sur des chaînes d’éléments à retard contrôlés. Elle consiste à comparer les délais de chaînes à retard identiques qui sont mises en série. Les points forts de cette structure sont la facilité de sa mise en œuvre sur les deux plates-formes ASIC et FPGA, la grande flexibilité pour l’authentification des circuits intégrés ainsi que la génération de clés de chiffrement. La deuxième structure proposée “TERO PUF” est basée sur le principe de cellules temporairement oscillantes. Elle exploite la métastabilité oscillatoire d’éléments couplés en croix, et peut aussi être utilisée pour un générateur vrai d’aléas (TRNG). Plus précisément, la réponse du PUF profite de la métastabilité oscillatoire introduite par une bascule SR lorsque les deux entrées S et R sont connectées au même signal d’entrée. Les résultats expérimentaux montrent le niveau de performances élevé des deux structures de PUF proposées. Ensuite, afin de comparer équitablement la qualité des différentes PUF à retard, nous proposons une méthode de caractérisation spécifique. Elle est basée sur des mesures statistiques des éléments à retard. Le principal avantage de cette méthode vient de sa capacité à permettre au concepteur d’être sûr que la fonction PUF aura les performances attendues avant sa mise en œuvre et sa fabrication. Enfin, en se basant sur les propriétés de non clonabilité et de l’imprévisibilité des PUF, nous présentons de nouvelles techniques d’authentification et de génération de clés de chiffrement en utilisant la “loop PUF” proposée. Les résultats théoriques et expérimentaux montrent l’efficacité des techniques introduites en termes de complexité et de fiabilitéPhysically Unclonable Functions, or PUFs, are innovative technologies devoted to solve some security and identification issues. Similarly to a human fingerprint, PUFs allows to identify uniquely electronic devices as they produce an instance-specific signature. Applications as authentication or key generation can take advantage of this embedded function. The main property that we try to obtain from a PUF is the generation of a unique response that varies randomly from one physical device to another without allowing its prediction. Another important property of these PUF is to always reproduce the same response for the same input challenge even in a changing environment. Moreover, the PUF system should be secure against attacks that could reveal its response. In this thesis, we are interested in silicon PUF which take advantage of inherent process variations during the manufacturing of CMOS integrated circuits. We present several PUF constructions, discuss their properties and the implementation techniques to use them in security applications. We first present two novel PUF structures. The first one, called “Loop PUF” is a delay based PUF which relies on the comparison of delay measurements of identical serial delay chains. The major contribution brought by the use of this structure is its implementation simplicity on both ASIC and FPGA platforms, and its flexibility as it can be used for reliable authentication or key generation. The second proposed structure is a ring-oscillator based PUF cells “TERO PUF”. It exploits the oscillatory metastability of cross-coupled elements, and can also be used as True Random Number Generator (TRNG). More precisely, the PUF response takes advantage from the introduced oscillatory metastability of an SR flip-flop when the S and R inputs are connected to the same input signal. Experimental results show the high performance of these two proposed PUF structures. Second, in order to fairly compare the quality of different delay based PUFs, we propose a specific characterization method. It is based on statistical measurements on basic delay elements. The main benefit of this method is that it allows the designer to be sure that the PUF will meet the expected performances before its implementation and fabrication. Finally, Based on the unclonability and unpredictability properties of the PUFs, we present new techniques to perform “loop PUF” authentication and cryptographic key generation. Theoretical and experimental results show the efficiency of the introduced techniques in terms of complexity and reliability
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Ramsey, Glenn. "Hardware/software optimizations for elliptic curve scalar multiplication on hybrid FPGAs /." Online version of thesis, 2008. http://hdl.handle.net/1850/7765.
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Moussa, Ali Abdellatif Karim. "Chiffrement authentifié sur FPGAs de la partie reconfigurable à la partie static." Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066660/document.
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Les systèmes de communication ont besoin d'accéder, stocker, manipuler, ou de communiquer des informations sensibles. Par conséquent, les primitives cryptographiques tels que les fonctions de hachage et le chiffrement par blocs sont déployés pour fournir le cryptage et l'authentification. Récemment, des techniques ont été inventés pour combiner cryptage et d'authentification en un seul algorithme qui est appelé authentifiés Encryption (AE). La combinaison de ces deux services de sécurité dans le matériel de meilleures performances par rapport aux deux algorithmes séparés puisque l'authentification et le cryptage peuvent partager une partie du calcul. En raison de la combinaison de la programmation de l'exécution d'matériel personnalisé, FPGA deviennent plus communs comme cible d'une mise en œuvre de ces algorithmes. La première partie de cette thèse est consacrée aux architectures d'algorithmes AE, AES-GCM et AEGIS-128 à base de FPGA efficaces et à grande vitesse, afin d'être utilisé dans la partie reconfigurable FPGA pour soutenir les services de sécurité des systèmes de communication. Notre focalisation sur l'état de l'art conduit à la mise en place d'architectures à haute vitesse pour les applications lentes touches changeantes comme les réseaux privés virtuels (VPN). En outre, nous présentons un procédé efficace pour mettre en oeuvre le GF($2^{128}$) multiplicateur, qui est responsable de la tâche d'authentification en AES-GCM, pour supporter les applications à grande vitesse. En outre, un système efficace AEGIS-128 est également mis en œuvre en utilisant seulement cinq tours AES. Nos réalisations matérielles ont été évaluées à l'aide Virtex-5 et Virtex-4 FPGA. La performance des architectures présentées (Thr. / Parts) surpasse ceux signalés précédemment.La deuxième partie de la thèse présente des techniques pour des solutions à faible coût afin de garantir la reconfiguration du FPGA. Nous présentons différentes gammes de mises en œuvre à faible coût de AES-GCM, AES-CCM, et AEGIS-128, qui sont utilisés dans la partie statique du FPGA afin de décrypter et authentifier le bitstream FPGA. Architectures ASIC présentées ont été évaluées à l'aide de 90 et 65 technologies nm et présentent de meilleures performances par rapport aux travaux antérieursCommunication systems need to access, store, manipulate, or communicate sensitive information. Therefore, cryptographic primitives such as hash functions and block ciphers are deployed to provide encryption and authentication. Recently, techniques have been invented to combine encryption and authentication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces better performance compared to two separated algorithms since authentication and encryption can share a part of the computation. Because of combining the programmability with the performance ofcustom hardware, FPGAs become more common as an implementation target for such algorithms. The first part of this thesis is devoted to efficient and high-speed FPGA-based architectures of AE algorithms, AES-GCM and AEGIS-128, in order to be used in the reconfigurable part of FPGAs to support security services of communication systems. Our focus on the state of the art leads to the introduction of high-speed architectures for slow changing keys applications like Virtual Private Networks (VPNs). Furthermore, we present an efficient method for implementing the GF($2^{128}$) multiplier, which is responsible for the authentication task in AES-GCM, to support high-speed applications. Additionally, an efficient AEGIS-128is also implemented using only five AES rounds. Our hardware implementations were evaluated using Virtex-5 and Virtex-4 FPGAs. The performance of the presented architectures (Thr./Slices) outperforms the previously reported ones.The second part of the thesis presents techniques for low cost solutions in order to secure the reconfiguration of FPGAs. We present different ranges of low cost implementations of AES-GCM, AES-CCM, and AEGIS-128, which are used in the static part of the FPGA in order to decrypt and authenticate the FPGA bitstream. Presented ASIC architectures were evaluated using 90 and 65 nm technologies and they present better performance compared to the previous work
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Smékal, David. "Zabezpečení vysokorychlostních komunikačních systémů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-220420.
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The diploma thesis deals with 128–bit AES data encryption and its implementation in FPGA network card using VHDL programming language. The theoretical part explains AES encryption and decryption, its individual steps and operating modes. Further was described the VHDL programming language, development environment Vivado, FPGA network card Combo–80G and configurable framework NetCOPE. The practical part is the implementation of AES–128 in VHDL. A simulation was used to eliminate errors, then the synthesis was performed. These steps were made using Vivado software. Last step of practical part was testing of synthesized firmware on COMBO–80G card. Total of 4 projects were implemented in FPGA card. Two of them were AES encryption and decryption with ECB mode and another two describe the encryption and decryption with CBC mode.
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Wang, Chin-Yuan, and 王群元. "FPGA Implementation of Chaos Algorithm for Image Encryption." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/14013934425841318521.
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碩士國立成功大學
工程科學系碩博士班
95
A FPGA-based image capture system with chaotic encryption is developed in this thesis. The immediate image is captured via the COMS sensor, and then encrypted and decrypted by FPGA module. The Logistic map is employed as the encryption algorithm, which designed by the IEEE 754 floating point module to improve the accuracy of the result. For testing the feasibility of this system, the solutions of encryption and decryption are presented and valided on PC. It has been shown that this system can work effectively for image encryption and decryption operations.
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Chen-yu-ta and 陳育達. "The FPGA Application Of Encryption Using Hex Hyperchaotic." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65107127765022762018.
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碩士明新科技大學
電子工程研究所
97
In this paper, we use the characteristics of Chaos to encrypt/decrypt data transfer in cyberspace since there are a lot of studies and applications on cryptography by Hyperchaotic theories recently. We realize the algorithm for encrypting/decrypting the files and data transferring by a Altra EP2C5 FPGA (Field Programmable Gate Array). The FPGA can be programmed by Verilog and easy to be modified. Encrypting/Decrypting by hardware, in contrast with software, is not easy copied and can achieve the requests for keeping secrecy. This paper can be divide into three parts, and they are the Altra FPGA(EP2C5), the OTI 6889 MCU(the micro controller) and the chatting rooms in cyberspace(Sever, Cline). Also, BCB(BorlandC++) is used to create the functions for chatting and transferring files on internet. In this thesis, all transferring in cyberspace, including the strings and the files, are encrypted and decrypted by the FPGA for maintaining secrecy.
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GAO, ZHI-MING, and 高志名. "Design FPGA Prototype for Video Encryption and Decryption." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/42443168945074536984.
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碩士中華科技大學
電子工程研究所碩士班
101
With the development of video camera technology, the portable video camera such as digital cameras, car camera recorders, smart phones are widely used. Nowadays, with video camera lens continuous progress, electronic products have multi-media video functions such that we can share images more conveniently. ”Every Solution Breeds the New Problems.” With that powerful device, the information security and personal privacy are becoming the huge problems that we should handle. Therefore, the real time image protection is very important. In this thesis, a video image development platform based on real time image protection is studied. The real time image uses encryption and decryption algorithm and mode structure to perform the image data security protection. The traditional security protection is by software. its complication of security level demand and encryption and decryption algorithm adds much load to the processor and it will reduce the efficiency of the processor. In addition, the software encryption or decryption has the security risk, it is easier to be attacked. Therefore, this study uses FPGA hardware chip to achieve the encryption and decryption algorithm and also combine the webcam as the hardware protection. Other than the upgrade of hardware security, it also integrates the video system as a platform. The hardware chip can perform AES cipher and 4 types of operation mode (ECB、CBC、CFB、OFB) and also hybrid mode. It can achieve the video data security protection. Furthermore, this study presents a defect of the ECB mode structure to bring up hybrid operation mode of ECB+CBC, also to improve weakness of the ECB mode structure. Besides, with hardware mode structure for the whole security protection, and provided for studying the design of video image development platform. Keywords: FPGA Prototype, Advanced Encryption Standard (AES), Video Security
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Ni, Wan-Sheng, and 倪萬昇. "AN EFFICIENT FPGA IMPLEMENTATION FOR ADVANCED ENCRYPTION STANDARD ALGORITHM." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/24889035951953243806.
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碩士大同大學
電機工程研究所
91
This thesis intends to derive a high speed and low-area architecture to implement AES algorithm. Reprogrammable devices such as Field Programmable Gate Arrays are highly attractive options for hardware implementations of encryption algorithm. We propose a sequential design which achieves the requirements of low area and high data rate in CLB-based FPGA. We present a method to integrate the AES encrypter and the AES decrypter into a full functional AES coengine. We also devised a pipeline design that unroll the 10 AES rounds and pipeline them in order to optimized the frequency and throughput results. The proposed architecture is suited for hardware-critical applications such as smart card, PDA, and mobile phone, etc.
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Wang, Ting-Fu, and 王廷富. "An Efficient FPGA Implementation of Advanced Encryption Standard Chip." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/62239123014484495728.
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碩士大同大學
通訊工程研究所
97
In this thesis, we propose an efficient Field Programmable Gate Arrays (FPGA) to implement Advanced Encryption Standard (AES) algorithm. The proposed design is based on the pipelined architecture that unrolls the 10 AES rounds to ensure the higher throughput, easer hardware architecture and optimized frequency. This implementation includes encryptor and decryptor which fit the most embedded applications, such as wireless devices, smart card and so on. We use Verilog, Xilinx ISE and ModelSim simulator to implement the chip design.
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HUANG, SIH-JIE, and 黃思傑. "Design and Analysis of FPGA-Base Chaotic Encryption System." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/u6w593.
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碩士國立臺灣科技大學
自動化及控制研究所
105
In the thesis scheme, we design a three-dimensional chaotic system and prove thebehavior of chaos by phase portraits and Lyapunov exponent. And, the continuous-time chaoticsystem is transformed into discrete-time chaotic system by Euler’ method. Finally, the discretetimechaotic system is implemented phase portraits on the oscilloscope via Altera FPGA DE2-115. A cryptographic system for RGB image security for threedimensional chaotic system is proposed. There are three features in our encryption system. First, we use the information of plaintext image to produce the initial conditions of chaotic system. Second, the image permutation process shuffles the position of pixels in the plaintext image among RGB channels individually. Third, in the diffusion process, the pixels information in the shuffled image are concealed by the XOR operation. And, we implemented the three-dimensional chaotic encryption system via Altera FPGA DE2-115. We can get the cipher image through the FPGA and simulate the image by matlab. In the security analysis such as histogram analysis, correlation coefficient analysis, information entropy analysis, differential attack analysis (NPCR, UACI) are performed. Results of various security analysis confirm that the proposed three-dimensional has high security and it is suitable for practical RGB image encryption.
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Lu, Han-Ting, and 呂漢廷. "3D-bitwise Image Encryption Scheme’s Improvement and its FPGA Implementation." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/a2s6b4.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
106
In this thesis, we improved a bitwise-based image encryption algorithm and implemented a encryption and transmission system with Altera FPGA DE2-115, and optimized it through FPGA's pipeline feature. We use a three-dimension chaotic system to generate the keys needed for the encryption process. There are two features in our encryption algorithm. First, we proposed an algorithm to improve the existing permutation algorithm to make it more in common use. Second, we optimize the XOR methods used in ordinary encryption algorithms. Use FPGA to design the corresponding circuit, through the highly parallelized and pipelined feature of FPGA, It can improve the efficiency of the algorithm a lot. In the analysis of cryptographic security. We used histogram analysis, correlation coefficient analysis, entropy analysis, and variance analysis, Besides, we also introduced local entropy analysis to verify the effectiveness of our encryption algorithm. Through we proposed an implementation method of the local entropy algorithm. From the above analysis, we can know that the image encryption algorithm we designed is not only highly versatile, but also has the advantages of high performance, and is very suitable for application in realistic systems.
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Groth, Toke Herholdt. "FPGA Optimization of Advanced Encryption Standard Algorithm for Biometric Images." Thesis, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-55427.
Full textAbstract:
This is a master thesis in the field of information security. The problem area addressed is how to efficiency implement encryption and decryption of biometric image data in a FPGA. The objective for the project was to implement AES (Advanced Encryption Standard ) encryption in a Xilinx Kintex-7 FPGA with biometric image data as the application. The method used in this project is Design Science Research Methodology, in total three design and development iterations were performed to achieve the project objectives. The end result is a FPGA platform designed for information security research with biometric image as application. The FPGA developed in this project, is the first fully pipelined AES encryption/decryption system to run physically in a Kintex-7 device. The encryption core was made by Dr. Qiang Liu and his team while the fully pipelined decryption core was designed in this project. The AES encryption/ decryptions was further optimized to support image application by adding Cipher-block chaining to both the encryption and decryption. The performance achieved for the system was 40 GB/s throughput, 5.27 Mb/slice efficiency with a power performance of 286 GB/W. The FPGA platform developed in this project is not only limited to AES, other cryptography standards can be implemented on the platform as well.Validerat; 20140619 (global_studentproject_submitter)
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Liang, Shih-Chieh, and 梁仕杰. "Realization of Encryption Algorithms for Bluetooth and WLAN－Using FPGA." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/63781847713180557367.
Full textAbstract:
碩士國立中正大學
電機工程研究所
91
With the rapid growth of the wireless communications, security becomes as an important issue. Data encryption is one of the essential technologies when implementing the security. Bluetooth defines its encryption algorithm for data protection in its specification. WLAN (Wireless Local Area Network) will replace WEP (Wire Equivalent Privacy) encryption algorithm with AES (Advanced Encryption Standard) to become a new data encryption algorithm. In this thesis, we implement Bluetooth and WLAN encryption algorithms via the Xilinx FPGA (Field Programmable Gate Array) board. The design entry of the FPGA uses VHDL (Very High Speed Integrated Circuit Hardware Description Language) because of its flexibility and portability. As a result, we could optimize our designs according to different environment variables and satisfy the demands in reality.
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Wu, Hou-Cheng, and 吳厚呈. "Implementation of Encryption Algorithm and Wireless Image Transmission System on FPGA." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/gv64y7.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
106
This thesis proposes an encryption algorithm. The key of the algorithm is generated based on the chaotic system. To this end, we designed a four-dimensional chaotic system and discussed the differences caused by compiling the chaotic system in different programming languages. Then we verified the characteristics of the chaotic system with phase portraits and Lyapunov exponent. After verification, we use the Euler's method to obtain the discrete-time signals of the chaotic system. The key generator generates two key sequences according to the discrete-time signal of the chaotic system and the characteristic value of the plaintext file. These key sequences are respectively used in XOR operation and Bits Insertion operation in the encryption algorithm to encrypt the plaintext file. Next, we implement the encryption algorithm and wireless image transmission system to the FPGA-based SOPC system. The hardware used is a pair of Altera DE2-115 motherboard and RFS daughter card. Here, we optimize the key generator and implemented it as an independent circuit. The independent circuit transmits the key to the SOPC system through the parallel I/O port. In SOPC system we designed two modes: Send Mode, Receive Mode. In Send Mode, system read the image file from the SD Card on the motherboard, and then call the encryption algorithm to encrypt the image file. After the image is encrypted, the system write the ciphertext into the SD Card on the mother board, and then the ciphertext is transmitted to the specified IP Port through the daughter card. In Receive Mode, system receive the ciphertext from the specified IP Port through the daughter card, and then call the encryption algorithm to decrypt the ciphertext. After the ciphertext is decrypted, the system write the plaintext to the SD card on the motherboard. In addition, after the system reads in, receives images, and encrypts and decrypts files, the processed data is instantly displayed via the VGA port. Finally, we verify the security of the encryption system by performing histogram analysis, correlation analysis, differential attack analysis, and entropy analysis on multiple ciphertexts. And proposes the future improvement direction of SOPC encrypted transmission system based on FPGA in this thesis.
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Barakat, Mohamed L. "Hardware Realization of Chaos Based Symmetric Image Encryption." Thesis, 2012. http://hdl.handle.net/10754/234953.
Full textAbstract:
This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.
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Chien, Yu-Sheng, and 簡育勝. "FPGA Implementation and Design of A hybrid Chaos-AES Color Image Encryption Algorithm." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/fwgz2v.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
107
In this thesis, we design an image encryption algorithm based on four-dimensional chaotic system to generate key and improve advanced encryption standard, and implement the encryption and transmission system with Altera FPGA DE10-Standard. The encryption algorithm is optimized by using the pipeline and parallel computing features of FPGA. First, the phase portraits analysis, equilibrium point analysis and Lyapunov exponent are used to verify the characteristics of the chaotic system. The verified chaotic system is used as a key generator for the encryption algorithm. In the improved advanced encryption standard, ShiftRows and SubByres are modified with Spin-Sort and Cubic S-Box, and the round of encryption is reduced. Next, we implement the encryption algorithm and the wired image transmission system to the ARM-based SoC-FPGA. The HPS software runs on Linux and is used to control the FPGA encryption algorithm and image transmission. After complete image encryption, use Socket to transmit to the receive side. Then decrypt the image and display it instantly through the VGA port. In the analysis of cryptographic security, we perform histogram analysis, correlation coefficient analysis, difference analysis and entropy analysis. The entropy analysis includes global and local. The results from the encryption security analysis show that the proposed image encryption algorithm is safe and effective.
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Hammad, Issam. "Efficient Hardware Implementations For The Advanced Encryption Standard Algorithm." 2010. http://hdl.handle.net/10222/13110.
Full textAbstract:
This thesis introduces new efficient hardware implementations for the Advanced Encryption Standard (AES) algorithm. Two main contributions are presented in this thesis, the first one is a high speed 128 bits AES encryptor, and the second one is a new 32 bits AES design. In first contribution a 128 bits loop unrolled sub-pipelined AES encryptor is presented. In this encryptor an efficient merging for the encryption process sub-steps is implemented after relocating them. The second contribution presents a 32 bits AES design. In this design, the S-BOX is implemented with internal pipelining and it is shared between the main round and the key expansion units. Also, the key expansion unit is implemented to work on the fly and in parallel with the main round unit. These designs have achieved higher FPGA (Throughput/Area) efficiency comparing to previous AES designs.
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Lee, Jian-De, and 李建德. "Chaos Synchronization of New Shimizu–Morioka System and Implementation on Image Encryption via FPGA." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/93917278119731491039.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
104
The new Shimizu–Morioka chaotic system is presented in this study. We use techniques include phase portraits, divergence computing, power spectrum analysis, equilibrium point analysis and Lyapunov exponent to analysis and understanding of the dynamical behaviors of the chaotic system. Furthermore, we simulate the real circuit and chaos synchronization of numerical analysis. In control theory, we utilize backstepping control, adaptive control, GYC partial region stability theory and BGYC synchronization control to make a slave system be synchronized with the new Shimizu–Morioka chaotic system. After validating the proposed model and controller, the chaotic synchronization and encryption are implemented with FPGA board. We implement the chaotic signal circuits by using FPGA board and implement these chaotic signals for image secure encryption algorithm. In addition, we successfully utilize the synchronization of the coupled control with the new Shimizu–Morioka system for the image encryption algorithm on FPGA. We change the master chaotic system to digital signals and use them to encrypt the image and use the digital signals of the synchronized slave system to decrypt the image in this study.
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Sun, Guo Jhih, and 孫國智. "The Design and Implementation of an Improved Twofish Encryption/Decryption Chip Using FPGA Devices." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/00479625818433359228.
Full textAbstract:
碩士國立臺北大學
通訊工程研究所
94
In the recent years, the Internet becomes so popular in the world such that the required bandwidth is growing rapidly and the encryption/decryption of digital data becomes very important. In 1997, NIST (National Institution of Standard and Technology) announced the AES (Advanced Encryption Standard) program to replace DES (Data encryption Standard), and Twofish is one of five schemes that meet the design criteria for AES and an improved Twofish cryptosystem algorithm with much higher security is proposed recently. In this thesis, we would like to realize this Improved Twofish encryption/ decryption chip with an FPGA (Field Programmable Gate Array) Stratix EP1S80 DSP manufactured by Altera Co. since Twofish has the smallest area with hardware implementation. Sixteen Rijndael-like S-boxes were generated mathematically, then we add a pseudo random number generator to determine the S-box should be applied in each round. This can enhance the security to against attacks. The method in our design is hierarchical bottom-up, and the chip performs data encryption, decryption, pseudo random number generation, and key generation in a single hardware unit. The Improved Twofish was implemented by using Verilog HDL (Hardware Design Language) simulation with ModelSim, and compiled with FPGA Compile II. The design of our chip requires 13813 logic elements and its average baud rate can reach 100.16 Mbps under a 31.3 MHz clock.
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Grabowski, James Steven. "An FPGA implementation of the advanced encryption standard with support for counter and feedback modes." Thesis, 2007. http://spectrum.library.concordia.ca/975562/1/MR34745.pdf.
Full textAbstract:
The Advanced Encryption Standard (AES) is a symmetric key block cipher approved by the National Institute of Standards and Technology (NIST). AES replaced the Data Encryption Standard (DES) as a standard encryption algorithm within the United States government. It is widely used in both software and hardware applications and transactions. Different confidentiality modes of operation allow a symmetric key block cipher to provide additional data confidentiality by altering the output in respect to previously processed input data. These modes include Cipher Block Chaining, Cipher Feedback, Output Feedback and Counter modes. Electronic Codebook (ECB) mode does not enhance the confidentiality of the original cipher. This thesis presents an implementation of AES on a field-programmable gate array (FPGA). The design improves upon similar implementations that only employ ECB mode by supporting all five confidentiality modes of operation. The unified design supports all applicable key sizes and offers competitive throughput and resource utilization compared to designs lacking additional confidentiality modes. The design occupies 7452 slices of a Xilinx Virtex-II Pro XC2VP50 and features a maximum clock speed of 56.3 MHz. Throughputs up to 480.427 Mbps, 423.906 Mbps and 379.284 Mbps for 128-bit, 192-bit and 256-bit keys are produced for all five modes of operation. A straightforward level of key agility allows encryption and decryption operations to proceed uninterrupted at the expense of throughput. This feature is ideal when it is necessary to change the key for each block of data. A physical hardware prototype of the design is employed as further demonstration of the design's functional abilities.
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Wang, Yi-Yuan, and 王億源. "Integrated Design and Realization of WEP、Triple-DES and AES Encryption/Decryption Algorithm - Using FPGA." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/29647469065444316594.
Full textAbstract:
碩士國立中正大學
通訊工程研究所
92
With the rapid growth of wireless communication, security has become an important issue. Data encryption is one of the essential technologies that is used for implementing security. Although the Data Encryption Standard (DES) is widely used for information security, it does not make information secure enough at present. In addition, wired Equivalent Privacy (WEP) is used for authentication and data privacy in popular Wireless Local Area Network (WLAN). However, it is also susceptible to security attacks [1][2]. The Triple Data Encryption Standard (Triple-DES) and the Advanced Encryption Standard (AES) have been adopted by the National Institute of Standards and Technology (NIST) as the new data encryption/decryption standards. In this thesis, we integrate Wired Equivalent Privacy (WEP), Triple Data Encryption Standard (Triple-DES) and Advance Encryption Standard (AES) algorithms in a Xilinx Field Programmable Gate Array (FPGA) board to form a single chip solution for triple-mode encryption/decryption algorithms. In addition, in the design flow, we use the internal memory blocks of the Virtex-II chip in the sub-module architecture to effectively reduce the required gate count.
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Chang, Teng-Chieh, and 張登傑. "Control and Synchronization of New LC Chaotic System and its Image Encryption via FPGA Implementation." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/44311680436615115432.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
103
The new LC chaotic system is presented in this study by adding a feedback control to smooth quadratic autonomous chaotic system which is discovered. We also discuss the dynamical behaviors of the new LC chaotic system by applying various techniques. These techniques include phase portraits, divergence computing, power spectrum analysis, bifurcation diagrams and Lyapunov exponent diagrams. In the part of control theory, by applying GYC partial region stability theory, active pinning control synchronization and reduce pinning controller factor of chaotic system is accomplished. The synchronization of chaotic system using adaptive complex feedback control in complex networks is proposed. In addition, an Image encryption algorithm on FPGA using the new LC chaotic system is achieved. We also discuss histogram analysis, information entropy analysis and differential attack analysis in this study.
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Lee, Chi-Feng, and 李其峰. "Control and Synchronization of New Genesio Chaotic System and its FPGA Implementation on Image Encryption." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/41802294665393492288.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
103
The chaotic system is proposed in this study by adding a feedback control to the Genesio chaotic system. We discuss the dynamical behaviors of the new Genesio chaotic system by applying various techniques. These techniques include phase portraits, equilibrium point analysis, divergence computing, power spectrum analysis, bifurcation diagrams and Lyapunov exponent diagrams. We also generate the chaotic signals of the new Genesio system on realized circuit board. In control theory, we utilize the adaptive control, the sliding mode control to complete synchronization. We also control the new Genesio chaotic system by the adaptive sliding mode control. Besides, we also use unidirectional and mutual control to make a slave system be synchronized with the new Genesio system. We implement the chaotic signal circuits by using FPGA board and implement these chaotic signals for image secure encryption algorithm. In addition, we successfully utilize the synchronization of the coupled control with the new Genesio system for the image encryption algorithm on FPGA. We change the maser chaotic system to digital signals and use them to encrypt the image and use the digital signals of the synchronized slave system to decrypt the image in this study.
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"Implementation of an FPGA based accelerator for virtual private networks." 2002. http://library.cuhk.edu.hk/record=b5895989.
Full textAbstract:
Cheung Yu Hoi Ocean.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 65-70).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Aims --- p.2
Chapter 1.3 --- Contributions --- p.3
Chapter 1.4 --- Thesis Outline --- p.3
Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4
Chapter 2.1 --- Introduction --- p.4
Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4
Chapter 2.3 --- Secure Virtual Private Network --- p.6
Chapter 2.4 --- LibDES --- p.9
Chapter 2.5 --- FreeS/WAN --- p.9
Chapter 2.6 --- Commercial VPN solutions --- p.9
Chapter 2.7 --- Summary --- p.11
Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12
Chapter 3.1 --- Introduction --- p.12
Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12
Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14
Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16
Chapter 3.3 --- The IDEA Algorithm --- p.17
Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20
Chapter 3.3.2 --- Previous work on IDEA --- p.21
Chapter 3.4 --- Block Cipher Modes of operation --- p.23
Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23
Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25
Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27
Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27
Chapter 3.6 --- Pilchard --- p.30
Chapter 3.6.1 --- Memory Cache Control Mode --- p.31
Chapter 3.7 --- Electronic Design Automation Tools --- p.32
Chapter 3.8 --- Summary --- p.33
Chapter 4 --- Implementation
Chapter 4.1 --- Introduction --- p.36
Chapter 4.1.1 --- Hardware Platform --- p.36
Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36
Chapter 4.1.3 --- Pilchard Software --- p.38
Chapter 4.2 --- DES in ECB mode --- p.39
Chapter 4.2.1 --- Hardware --- p.39
Chapter 4.2.2 --- Software Interface --- p.40
Chapter 4.3 --- DES in CBC mode --- p.42
Chapter 4.3.1 --- Hardware --- p.42
Chapter 4.3.2 --- Software Interface --- p.42
Chapter 4.4 --- Triple-DES in CBC mode --- p.45
Chapter 4.4.1 --- Hardware --- p.45
Chapter 4.4.2 --- Software Interface --- p.45
Chapter 4.5 --- IDEA in ECB mode --- p.48
Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48
Chapter 4.5.2 --- Hardware --- p.48
Chapter 4.5.3 --- Software Interface --- p.50
Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51
Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52
Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53
Chapter 4.9 --- Summary --- p.54
Chapter 5 --- Results --- p.55
Chapter 5.1 --- Introduction --- p.55
Chapter 5.2 --- Benchmarking environment --- p.55
Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56
Chapter 5.3.1 --- Performance of Triple-DES core --- p.55
Chapter 5.3.2 --- Performance of IDEA core --- p.58
Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59
Chapter 5.4.1 --- Triple-DES --- p.59
Chapter 5.4.2 --- IDEA --- p.60
Chapter 5.5 --- Summary --- p.61
Chapter 6 --- Conclusion --- p.62
Chapter 6.1 --- Future development --- p.63
Bibliography --- p.65
42
Chang, Yi-Chung, and 張逸仲. "Development of Image Encryption and Decryption Processor by Using Chaotic Signal and Its FPGA Experimental Verification." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/zr7rj7.
Full textAbstract:
碩士國立臺灣科技大學
自動化及控制研究所
105
With the rapid development of information technology, portable data storage devices, Internet and cloud services have become a part of human daily life. For the digitization of personal information, information security has become a significant issue, in which data encryption is one of the popular research object. In this study, a parallel port transmission technique based on four-dimensional chaotic system is proposed for the security of hardware communication. Applying the Matlab to analyze the new 4D chaotic system’s properties which include 2D phase portraits, symmetry and invariance, divergence analysis, equilibrium analysis and Lyapunov exponent diagrams. First, through the two-dimensional phase portraits, divergence analysis, equilibrium analysis and Lyapunov exponent diagram, the new four-dimensional chaotic system is simulated and confirmed that its chaotic properties can be used to generate chaotic sequences through the Euler’s method as the shuffle sequence. In cryptography, confusion and diffusion operations are the main methods for designing the encryption algorithm. In this experiment, all the encryption operation is performed by generating chaotic sequence. In the confusion phase, the characteristic of chaotic pseudorandom sequence is used to shuffle the data content by bit-level permutation. Next, the pixel characters are also substituted by using chaotic pseudorandom number in diffusion phase. All the function for cryptosystem is implemented by Altera DE2-115 FPGA which supports the chaotic secure on parallel transmission. In order to analyze the security of proposed encryption algorithm, a BMP color image will be encrypted and accessed through FPGA. Finally, result of the Matlab analysis, we can get the conclusion of the new 4D chaotic system is a high security and simple-design for a cryptosystem.
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Πρίφτης, Αθανάσιος. "Διαφορική ανάλυση ισχύος μιας DES υλοποίησης σε FPGA." Thesis, 2006. http://nemertes.lis.upatras.gr/jspui/handle/10889/1428.
Full textAbstract:
Από τότε που ολοένα και περισσότερα εμπιστευτικά δεδομένα ανταλλάσσονται με ηλεκτρονικό τρόπο η ανάγκη για προστασία των δεδομένων αυτών γίνεται ολοένα και μεγαλύτερη. Στις πραγματικές εφαρμογές όπου χρησιμοποιούνται συστήματα κρυπτογραφίας παρατηρούνται νέες τεχνικές επίθεσης πέρα από αυτές που στηρίζονται στην μαθηματική ανάλυση. Εφαρμογές τόσο σε υλικό όσο και σε λογισμικό, παρουσιάζουν ένα αχανές πεδίο από επιθέσεις. Οι Side-Channel-Attacks εκμεταλλεύονται πληροφορίες που διαρρέουν από μια συσκευή κρυπτογράφησης. Μάλιστα από την μέρα που εμφανίστηκε μία συγκεκριμένη μέθοδος επίθεσης, προσελκύει ολοένα και μεγαλύτερο ενδιαφέρον. Πρόκειται για την Διαφορική Ανάλυση Ισχύος (Differential Power Analysis (DPA)) που πρωτοπαρουσιάστηκε από την Cryptography Research. Η DPA χρησιμοποιεί την πληροφορία που διαρρέει από μια συσκευή κρυπτογράφησης, και πρόκειται για την κατανάλωση ισχύος. Μία λιγότερο δυνατή παραλλαγή της DPA είναι η Simple Power Analysis (SPA), που παρουσιάστηκε επίσης από την Cryptography Research.
Βασικός στόχος της DPA είναι να μετρηθεί με ακρίβεια η κατανάλωση ισχύος του συστήματος. Έπειτα απαιτείται η γνώση του αλγόριθμου που εκτελείται από την συσκευή, ενώ τέλος απαραίτητο είναι ένα σύνολο από γνωστά κρυπτογραφήματα ή αυθεντικά μηνύματα. Η στρατηγική της επίθεσης απαιτεί την μέτρηση πολλών δειγμάτων και στην συνέχεια την διαίρεσή τους σε δύο ή περισσότερα σύνολα με βάση ενός κανόνα . Εν συνεχεία στατιστικές μέθοδοι χρησιμοποιούνται για την επιβεβαίωση του κανόνα αυτού. Αν και μόνο αν ο κανόνας αυτός είναι σωστός τότε μπορούμε να παρατηρήσουμε αξιοπρόσεκτες τιμές στην στατιστική ανάλυση.
Σκοπός της εργασίας αυτής είναι να καθορίσουμε με περισσότερες λεπτομέρειες την DPA, να αναπτύξουμε ένα περιβάλλον που θα πραγματοποιεί την επίθεση αυτή, σε μια υλοποίηση του DES (Data Encryption Standard) αλγόριθμου κρυπτογράφησης με την χρήση FPGA Board και να γίνει πειραματική εκτίμηση.-
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Kenney, David. "Energy Efficiency Analysis and Implementation of AES on an FPGA." Thesis, 2008. http://hdl.handle.net/10012/4170.
Full textAbstract:
The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements.
Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all.
This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation.
The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.
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Fu, Xiaoquan. "Design and verification of the data encryption standard for ASICS and FPGAS." 2003. http://etd.utk.edu/2003/FuXiaoquan.pdf.
Full textAbstract:
Thesis (M.S.)--University of Tennessee, Knoxville, 2003.Title from title page screen (viewed Sept. 24, 2003). Thesis advisor: Donald W. Bouldin. Document formatted into pages (viii, 94 p. : ill. (some col.). Vita. Includes bibliographical references (p. 57-59).