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Journal articles on the topic 'FPGA Encryption'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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1

Mahmood, Zainab H., and Mahmood K. Ibrahem. "HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV." Iraqi Journal of Information & Communications Technology 2, no. 2 (November 1, 2019): 44–57. http://dx.doi.org/10.31987/ijict.2.2.69.

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

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2

Yang, Cheng-Hsiung, and Yu-Sheng Chien. "FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm." Symmetry 12, no. 2 (January 22, 2020): 189. http://dx.doi.org/10.3390/sym12020189.

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In this paper, we propose an image encryption algorithm based on four-dimensional chaotic system to generate key and improve advanced encryption standard. The encryption algorithm is optimized by using the pipeline and parallel computing features of Field Programmable Gate Array (FPGA). First, the chaotic system is used as a key generator for the encryption algorithm. Next, in the improved advanced encryption standard, ShiftRows and SubByres are modified with Spin-Sort and Cubic S-Box, and the round of encryption is reduced. We implement the encryption algorithm and the wired image transmission system to the ARM-based SoC-FPGA. The HPS software runs on Linux and is used to control the FPGA encryption algorithm and image transmission. Finally, the results from the encryption security analysis show that the proposed image encryption algorithm is safe and effective.

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3

Nayak, Nikhilesh, Akshay Chandak, Nisarg Shah, and B. Karthikeyan. "Encryption and decryption using FPGA." IOP Conference Series: Materials Science and Engineering 263 (November 2017): 052030. http://dx.doi.org/10.1088/1757-899x/263/5/052030.

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4

Gong, Yanping, Fengyu Qian, and Lei Wang. "Masked FPGA Bitstream Encryption via Partial Reconfiguration." International Journal of High Speed Electronics and Systems 28, no. 03n04 (September 2019): 1940022. http://dx.doi.org/10.1142/s0129156419400226.

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Field Programmable Gate Arrays (FPGA), as one of the popular circuit implementation platforms, provide the flexible and powerful way for different applications. IC designs are configured to FPGA through bitstream files. However, the configuration process can be hacked by side channel attacks (SCA) to acquire the critical design information, even under the protection of encryptions. Reports have shown many successful attacks against the FPGA cryptographic systems during the bitstream loading process to acquire the entire design. Current countermeasures, mostly random masking methods, are effective but also introduce large hardware complexity. They are not suitable for resource-constrained scenarios such as Internet of Things (IoT) applications. In this paper, we propose a new secure FPGA masking scheme to counter the SCA. By utilizing the FPGA partial reconfiguration feature, the proposed technique provides a light-weight and flexible solution for the FPGA decryption masking.

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5

Kumar Sahu, Sushanta, and Manoranjan Pradhan. "FPGA Implementation of RSA Encryption System." International Journal of Computer Applications 19, no. 9 (April 30, 2011): 10–12. http://dx.doi.org/10.5120/2391-3173.

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6

., Kumar Anubhav Tiwari. "FPGA BASED ENCRYPTION DESIGN USING VHDL." International Journal of Research in Engineering and Technology 03, no. 22 (June 25, 2014): 148–51. http://dx.doi.org/10.15623/ijret.2014.0322032.

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7

Hasan, Hind Ali Abdul, Safaa Maijd Mohammed, and Noor Hayder Abdul Ameer. "ADVANCED ENCRYPTION STANDARD USING FPGA OVERNETWORK." EUREKA: Physics and Engineering, no. 1 (January 29, 2021): 32–39. http://dx.doi.org/10.21303/2461-4262.2021.001613.

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The increase number of eavesdropping or cracker to attack the information and hack the privacy of people. So, the essential issue is making system capable of ciphering information with rapid speed. Due to the advance in computer eavesdropping and cracker that made them to analysis the way of ciphering in rapid speed way. The development in the computer especially in the rapid processer in the last decade create the breaching of any system is a matter of time. Owing to most of breaching ways are based on analysis of system that requireы to be breached and to try brute force on that system to crack it. However, the lacking of influential processers that are capable of breaching system since earlier processors are limit to number of instructions. It can be done in second, which was not sufficient trying to break the system using brute force. In addition, the time required is far away from getting valuable messages in the time that needed. So, the research gives the focus on performing rapid system for ciphering the information rapidly and changing the ciphering every few milliseconds. The changing of ciphering in every millisecond helps system form preventing the eavesdropping and cracker from imposing brute force on the system and hacking the messages and images. The system that created is based on Advanced Encryption Standard (AES), which is it very best performing algorithm in ciphering and deciphering since it doesn’t need complex mathematical formula. The research is about designing system that capable of performing AES by using high processer designed on Field programmable gate Area (FPGA). The ciphering of AES using FPGA helps minimize the time required to cipher the information. Also, the research will focus on ciphering and deciphering of images by AES using FPGA

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8

Zhao, Jin Hui, and Xiao Hong Wang. "Model of Video Encryption Based on FPGA." Advanced Materials Research 791-793 (September 2013): 1497–500. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.1497.

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On the Internet, most of media information is transmitted in plaintext. Some others can easily tamper or intercut the information, so there are threats to those information transmitted in plaintext. This paper designs a model of video encryption which uses AES algorithm and the model is based on FPGA platform. The model does the encryption in paralleling on XUPV5-110T development board. The encryption model can ensure the security and integrity of media information during the transmission process between a certain links on the network.

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9

Zeng, Rong, Xiu Li Huang, and Ya Dong Chen. "A High Rate Parallel Operation Encryption Card Design Base on FPGA." Applied Mechanics and Materials 668-669 (October 2014): 783–86. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.783.

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A design of encryption cards controlling multiple cipher chips’ high-rate parallel operation based on FPGA is proposed in this paper. According to the design method, we can achieve that multiple encryption card operates encryption in parallel way, which can improve the encryption and decryption rate of the encryption card without enhancing the performance of encryption chip, moreover, increase the key generation rate and management level of the key management system.

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10

Tang, Hong Wei. "32-bit Datapath AES IP Core Based on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 1848–51. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1848.

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This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.

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11

Trang, Hoang, and Nguyen Van Loi. "Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm." International Journal of Distributed Systems and Technologies 4, no. 1 (January 2013): 56–77. http://dx.doi.org/10.4018/jdst.2013010105.

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This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the authors’ proposals, they are found to be very simple in FPGA-based architecture implementation, better in low latency, and small area, but large in memory, moderate throughput.

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12

Silva, Diego Augusto, Duarte Lopes Oliveira, and Gracieth Cavalcanti Batista. "Design of DES encryption algorithm as bundleddata asynchronous pipeline using FPGA." Revista Brasileira de Aplicações de Vácuo 39, no. 3 (December 28, 2020): 260–70. http://dx.doi.org/10.17563/rbav.v39i3.1179.

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Currently, digital systems that are able to meet major security restrictions are increasingly being demanded, both in the military and in commercial areas. Data security can be achieved by cryptographic algorithms. An important encryption algorithm known as data encryption standard (DES) was implemented in field programmable gate array (FPGA) in different synchronous architectures. In this paper, we have proposed the implementation of the DES algorithm in FPGA, in the asynchronous pipeline style. Compared to the implementation in FPGA using two different project styles, the proposed asynchronous obtained the average increase of 14.9% in throughput and the average reduction of 66.3% in latency.

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13

Mokhtar, M. Amr. "High Performance Data Encryption based on Advanced Encryption Standard using FPGA." IOSR Journal of Computer Engineering 16, no. 6 (2014): 07–13. http://dx.doi.org/10.9790/0661-16650713.

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14

LIN, XIN, WEIHUI SHI, and YONGXIANG DU. "INTERACTIVE DATA ENCRYPTION STRATEGY FOR DISTRIBUTED SIMULATION SYSTEM." International Journal of Modeling, Simulation, and Scientific Computing 04, no. 04 (September 12, 2013): 1342005. http://dx.doi.org/10.1142/s1793962313420051.

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The distributed simulation system interoperation can be divided into six levels. Interactive data encryption can be completed in each level, lead to six encryption strategies: data field encryption, data package encryption, program module encryption, simulation application encryption, simulation node encryption, and simulation system encryption. There are four basic Encryption/decryption realization modes: serial modes with software or hardware realization, parallel modes based on embedded processor or FPGA/ASIC system. Large and Complex distributed simulation system may employ one or several encryption strategies and realization modes.

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15

B, Lakshmi, Kirubakaran E, and Prabakar T.N. "FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION." ICTACT Journal on Communication Technology 01, no. 03 (September 1, 2010): 150–56. http://dx.doi.org/10.21917/ijct.2010.0022.

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16

Prasetio, Barlian Henryranu, Eko Setiawan, and Adharul Muttaqin. "Image Encryption using Simple Algorithm on FPGA." TELKOMNIKA (Telecommunication Computing Electronics and Control) 13, no. 4 (December 1, 2015): 1153. http://dx.doi.org/10.12928/telkomnika.v13i4.1787.

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17

Ruan, Wei Hua, and Qing Sheng Hu. "A Kind of Logarithmic Function Hardware Encryptor and Decryptor." Applied Mechanics and Materials 427-429 (September 2013): 2956–59. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.2956.

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This paper presents the realization of a kind of hardware encryptor and decryptor, which is based on Logarithmic Function principle. It shows how to design the encryption circuit and the decryption circuit by the sequential circuit. It had been designed in VHDL and simulated by Modelsim software, and then synthesized as well as realized on the FPGA chip EP2C5T144 by QuartusII software, last finished the test.

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18

Oukili, Soufiane, and Seddik Bri. "High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 298. http://dx.doi.org/10.11591/ijece.v6i1.8388.

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<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

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19

Oukili, Soufiane, and Seddik Bri. "High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 298. http://dx.doi.org/10.11591/ijece.v6i1.pp298-306.

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<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

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20

Zeebaree, Subhi R. M. "DES encryption and decryption algorithm implementation based on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (May 1, 2020): 774. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp774-781.

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Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept. The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

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21

Rabie, A., Kh El Shafie, A. Hammuoda, and M. Rohiem. "Data ecryption based on multi-order FrFT, and FPGA implementation of DES algorith." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (July 1, 2020): 141. http://dx.doi.org/10.11591/ijres.v9.i2.pp141-152.

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<span>Cryptography techniques need some algorithms for encryption of data. Most of available encryption techniques are used for textual data; a few of encryption methods are used for multimedia data; However, This Algorithms that are used for textual data may not be inefficient for multimedia, because it is size is greater than the text. Therefore, Cryptosystems need to find and develop a new encryption schemes for such data. The most popular symmetric key algorithms are Data Encryption Standard (DES). However, DES is may be not suitable for multimedia because it consumes times. Encryption and decryption of these data require different methods. In this paper a method for encryption/decryption data by using the nature of FrFT in signals analysis, based on multi-order Fractional Fourier Transform has been introduced. The security of the method used in the encryption work was taken into account to identify the different indicators to measure the security of the encryption Techniques. These indicators are: sensitivity proposed Techniques for the key, the complexity of the processes, and statistical analysis. The key is formed by combination of order of Fractional Fourier Transform. The encrypted data is obtained by the summation of different orders. Numerical simulation results are given to demonstrate this proposed method.</span>

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22

Abdullah, Hamsa A., and Hikmat N. Abdullah. "FPGA implementation of color image encryption using a new chaotic map." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 1 (January 1, 2019): 129. http://dx.doi.org/10.11591/ijeecs.v13.i1.pp129-137.

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<p>In this paper, an FPGA implementation of efficient image encryption algorithm using a chaotic map has been proposed. The proposed system consists of two phases image encryption technique. First phase consists of scrambling of pixel position and second phase consist of diffusion of bit value. In the first phase, original pixel values remain unchanged. In second phase, pixel values are modified. These modifications are done by using chaotic behavior of a recently developed chaotic map called Nahrain. A color image encryption using Nahrain chaotic map is simulated in software via Matlab, Altera Quartus Prime 17.0 Lite EditionI and ModelSim software tools then implemented in hardware via Cyclone V GX Starter Kit FPGA platform. The results show the feasibility and effectiveness of the cryptosystem. As a typical application, the image encryption/decryption is used to demonstrate and verify the operation of the cryptosystem hardware. Complete analysis on robustness of the method is investigated. Correlation, Encryption time, Decryption time and key sensitivity show that the proposed crypto processor offers high security and reliable encryption speed for real-time image encryption and transmission. To evaluate the performance, histogram, correlation, information entropy, number of pixel change rate (NPCR), and unified average changing intensity (UACI) measures are used for security analysis. The simulation results and security analysis have demonstrated that the proposed encryption system is robust and flexible. For example the amount of entropy obtained by the proposed algorithm is 7.9964, which is very close to its ideal amount: 8, and NPCR is 99.76 %, which is the excellent value to obtain. The hardware simulation results show that the number of pins that used of the proposed system reaches to 6% of total pins and Logic utilization (in ALMs) is 1%.</p>

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23

Nabil, Mohamed, Ashraf A. M. Khalaf, and Sara M. Hassan. "Design and implementation of pipelined and parallel AES encryption systems using FPGA." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (October 1, 2020): 287. http://dx.doi.org/10.11591/ijeecs.v20.i1.pp287-299.

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<p><span>The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the Advanced Encryption Standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.</span></p>

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24

M. Hassan, Sara, and Gihan G. Hamza. "Real-time FPGA implementation of concatenated AES and IDEA cryptography system." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 71. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp71-82.

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<span>The data encryption is one of the most critical issues in the communication system design. Nowadays, many encryption algorithms are being updated to keep pace with the remarkable progress in the communication field. The advanced encryption standard (AES) is a common algorithm that has proved its efficacy. The main drawback of AES is that it uses too simple algebraic structures, since every block is always encrypted in the same way that makes the hacking process possible if the hacker captures the key and the uses S-Box in the input stage. This especially applies to the unwired communication systems where chances of hacking exceed those found in the wired systems. The paper proposes a security enhancement method that is based on utilizing concatenated AES and international data encryption algorithm (IDEA) algorithms. Upon applying the proposed algorithm, the hacking process becomes a great challenge. The paper incorporates the real-time FPGA implementation of the proposed algorithm in the encryption and the decryption stages. Besides, the paper presents a clear analysis of the system’s performance.</span>

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25

Ahmed, Shakil, and Muhammad Naseem. "Efficient AES-XTS Pipelined Implementation on FPGA." Sir Syed University Research Journal of Engineering & Technology 4, no. 1 (December 19, 2014): 6. http://dx.doi.org/10.33317/ssurj.v4i1.56.

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In past years, it has been considered that only datacommunicated via networks need to be secured. This paradigmnow shifted towards securing data at rest. With its increasingsignificance, IEEE has introduced a mode of AdvancedEncryption Standard (AES) named as XTS-AES. Few of itsimplementations exist. This paper presents a high throughputand highly efficient fully unrolled pipelined design of AES-XTSon FPGA. The proposed implementation incorporates only oneAES core for both tweak value encryption as well as dataencryption. Further our proposed design calculates tweak valuein parallel to data encryption/decryption process. The resultshave achieved a throughput of 35.8 Gbps with an efficiency of 8.4Mbps/slice. This design offers the best result forThroughput/Area that is 4.641 Mbps/area.

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26

Rohiem, Alaa El Din, Kamel Hassan, and Ahmed El-Amin. "DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA." International Conference on Electrical Engineering 5, no. 5 (May 1, 2006): 1–24. http://dx.doi.org/10.21608/iceeng.2006.33547.

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27

Abdelwahab, Murtada Mohamed. "Encryption Implementation of Rock Cipher Based on FPGA." IOSR Journal of Engineering 4, no. 1 (January 2014): 14–20. http://dx.doi.org/10.9790/3021-04171420.

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28

Namdeo, Lokesh, and Himanshu Nautiyal. "Performance Analysis of Advanced Encryption Standard on FPGA." International Journal of Computer Applications 153, no. 6 (November 17, 2016): 47–51. http://dx.doi.org/10.5120/ijca2016912085.

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29

Mace, F., F. X. Standaert, and J. J. Quisquater. "FPGA Implementation(s) of a Scalable Encryption Algorithm." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 2 (2008): 212–16. http://dx.doi.org/10.1109/tvlsi.2007.904139.

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Cousins, David Bruce, Kurt Rohloff, and Daniel Sumorok. "Designing an FPGA-Accelerated Homomorphic Encryption Co-Processor." IEEE Transactions on Emerging Topics in Computing 5, no. 2 (April 1, 2017): 193–206. http://dx.doi.org/10.1109/tetc.2016.2619669.

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31

Liu, Cai-hong, Jin-shui Ji, and Zi-long Liu. "Implementation of DES Encryption Arithmetic based on FPGA." AASRI Procedia 5 (2013): 209–13. http://dx.doi.org/10.1016/j.aasri.2013.10.080.

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Mostafaa, H., S. M. Eisaa, H. H. Issaa, and N. H. Shaker. "Lightweight Hybrid Encryption System with FPGA Design Proposal." IOP Conference Series: Materials Science and Engineering 1051, no. 1 (February 1, 2021): 012023. http://dx.doi.org/10.1088/1757-899x/1051/1/012023.

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33

Renuka, G., V. Usha Shree, and P. Chandra Sekhar Reddy. "Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (October 1, 2018): 3544. http://dx.doi.org/10.11591/ijece.v8i5.pp3544-3549.

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Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

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34

Ma, Xiao Cong, Guang Hui Cai, Hong Chao Sun, and Hong Ye Li. "Design and Implementation of an Encryption/Decryption System Based on FPGA." Advanced Materials Research 1022 (August 2014): 368–71. http://dx.doi.org/10.4028/www.scientific.net/amr.1022.368.

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This paper designs an encryption and decryption system based on the FPGA. The system uses AES algorithm to encrypt and decrypt data. A pipeline IP core is designed with the reconfigurable technology complying with the Avalon bus interface specification. The IP core is applied to be a custom component on Nios II architecture so that the encryption and decryption processes through hardware can be controlled by software. Finally, the program is downloaded to the Altera DE2 development board and completes the testing of encryption and decryption processes. The system can be widely implemented in the field of data security.

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Visconti, Paolo, Ramiro Velazquez, Stefano Capoccia, and Roberto De Fazio. "High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (October 1, 2021): 4221. http://dx.doi.org/10.11591/ijece.v11i5.pp4221-4232.

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<p>In this research work, a fast and lightweight AES-128 cypher based on the Xilinx ZCU102 FPGA board is presented, suitable for 5G communications. In particular, both encryption and decryption algorithms have been developed using a pipelined approach, so enabling the simultaneous processing of the rounds on multiple data packets at each clock cycle. Both the encryption and decryption systems support an operative frequency up to 220 MHz, reaching 28.16 Gbit/s maximum data throughput; besides, the encryption and decryption phases last both only ten clock periods. To guarantee the interoperability of the developed encryption/decryption system with the other sections of the 5G communication apparatus, synchronization and control signals have been integrated. The encryption system uses only 1631 CLBs, whereas the decryption one only 3464 CLBs, ascribable, mainly, to the Inverse Mix Columns step. The developed cypher shows higher efficiency (8.63 Mbps/slice) than similar solutions present in literature.</p>

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Ahmed, Shakil, and Muhammad Naseem. "2 Efficient AES-XTS Pipelined Implementation on FPGA." Sir Syed Research Journal of Engineering & Technology 1, no. 1 (December 19, 2014): 6. http://dx.doi.org/10.33317/ssurj.v1i1.56.

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In past years, it has been considered that only datacommunicated via networks need to be secured. This paradigmnow shifted towards securing data at rest. With its increasingsignificance, IEEE has introduced a mode of AdvancedEncryption Standard (AES) named as XTS-AES. Few of itsimplementations exist. This paper presents a high throughputand highly efficient fully unrolled pipelined design of AES-XTSon FPGA. The proposed implementation incorporates only oneAES core for both tweak value encryption as well as dataencryption. Further our proposed design calculates tweak valuein parallel to data encryption/decryption process. The resultshave achieved a throughput of 35.8 Gbps with an efficiency of 8.4Mbps/slice. This design offers the best result forThroughput/Area that is 4.641 Mbps/area.

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Liang, Wei, Jian Bo Xu, Wei Hong Huang, and Li Peng. "The Design and Implementation of ECC High-Speed Encryption Engine Based on FPGA." Advanced Materials Research 459 (January 2012): 544–48. http://dx.doi.org/10.4028/www.scientific.net/amr.459.544.

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Network security technology ensures secure data transmission in network. Meanwhile, it brings extra overhead of security system in terms of cost and performance, which seriously affects the rapid development of existing high-speed encryption systems. The existing encryption technology cannot meet the demand of high security, low cost and high real-time. For solving above problems, an ECC encryption engine architecture based on scalable public key cipher and a high-speed configurable multiplication algorithm are designed. The algorithm was tested on FPGA platform and the experiment results show that the system has better computation speed and lower cost overhead. By comparing with other systems, our system has benefits in terms of hardware overhead and encryption time ratio

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Tlelo-Cuautle, Esteban, Jonathan Daniel Díaz-Muñoz, Astrid Maritza González-Zapata, Rui Li, Walter Daniel León-Salas, Francisco V. Fernández, Omar Guillén-Fernández, and Israel Cruz-Vega. "Chaotic Image Encryption Using Hopfield and Hindmarsh–Rose Neurons Implemented on FPGA." Sensors 20, no. 5 (February 28, 2020): 1326. http://dx.doi.org/10.3390/s20051326.

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Chaotic systems implemented by artificial neural networks are good candidates for data encryption. In this manner, this paper introduces the cryptographic application of the Hopfield and the Hindmarsh–Rose neurons. The contribution is focused on finding suitable coefficient values of the neurons to generate robust random binary sequences that can be used in image encryption. This task is performed by evaluating the bifurcation diagrams from which one chooses appropriate coefficient values of the mathematical models that produce high positive Lyapunov exponent and Kaplan–Yorke dimension values, which are computed using TISEAN. The randomness of both the Hopfield and the Hindmarsh–Rose neurons is evaluated from chaotic time series data by performing National Institute of Standard and Technology (NIST) tests. The implementation of both neurons is done using field-programmable gate arrays whose architectures are used to develop an encryption system for RGB images. The success of the encryption system is confirmed by performing correlation, histogram, variance, entropy, and Number of Pixel Change Rate (NPCR) tests.

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Adil Yazdeen, Abdulmajeed, Subhi R. M. Zeebaree, Mohammed Mohammed Sadeeq, Shakir Fattah Kak, Omar M. Ahmed, and Rizgar R. Zebari. "FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review." Qubahan Academic Journal 1, no. 2 (March 15, 2021): 8–16. http://dx.doi.org/10.48161/qaj.v1n2a38.

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In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.

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Li, You Guo. "Improved RSA Algorithm in Hardware Encryption." Applied Mechanics and Materials 543-547 (March 2014): 3610–13. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.3610.

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Montgomery algorithm will die N operation into shift operation, optimized Systolic array with fewer resources to achieve efficient Montgomery algorithm, and the application of power conversion technology to further improve the RSA encryption,decryption speed. In order to make full use of FPGA resources, this paper analyzes the impact of the Systolic array at different levels of granularity on the performance of the system, and gives the realization and S = key and encryption,decryption information are RSA encryption system of s hardware 1024 time results.

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Zheng, Hanzhong, Simin Yu, and Xiangqian Xu. "A Systematic Methodology for Multi-Images Encryption and Decryption Based on Single Chaotic System and FPGA Embedded Implementation." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/698608.

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A systematic methodology is developed for multi-images encryption and decryption and field programmable gate array (FPGA) embedded implementation by using single discrete time chaotic system. To overcome the traditional limitations that a chaotic system can only encrypt or decrypt one image, this paper initiates a new approach to designn-dimensional (n-D) discrete time chaotic controlled systems via some variables anticontrol, which can achieve multipath drive-response synchronization. To that end, the designedn-dimensional discrete time chaotic controlled systems are used for multi-images encryption and decryption. A generalized design principle and the corresponding implementation steps are also given. Based on the FPGA embedded hardware system working platform with XUP Virtex-II type, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed, and the related system design and hardware implementation results are demonstrated, with the related mathematical problems analyzed.

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Rajoriya, Parul, and Nilesh Mohota (Professor). "Fpga Implementation of Image Encryption and Decryption Using Aes Algorithm Along With Key Encryption." IOSR Journal of Electronics and Communication Engineering 12, no. 03 (June 2017): 40–50. http://dx.doi.org/10.9790/2834-1203024050.

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Shams, Rehan, Fozia Hanif Khan, Umair Jillani, and M. Umair. "3 Introducing Primality Testing Algorithm with an Implementation on 64 bits RSA Encryption Using Verilog." Sir Syed Research Journal of Engineering & Technology 1, no. 1 (December 20, 2018): 6. http://dx.doi.org/10.33317/ssurj.v1i1.68.

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A new structure to develop 64-bit RSA encryption engine on FPGA is being presented in this paper that can be used as a standard device in the secured communication system. The RSA algorithm has three parts i.e. key generation, encryption and decryption. This procedure also requires random generation of prime numbers, therefore, we are proposing an efficient fast Primality testing algorithm to meet the requirement for generating the key in RSA algorithm. We use right-to-left-binary method for the exponent calculation. This reduces the number of cycles enhancing the performance of the system and reducing the area usage of the FPGA. These blocks are coded in Verilog and are synthesized and simulated in Xilinx 13.2 design suit.

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Shams, Rehan, Fozia Hanif Khan, Umair Jillani, and M. Umair. "Introducing Primality Testing Algorithm with an Implementation on 64 bits RSA Encryption Using Verilog." Sir Syed University Research Journal of Engineering & Technology 2, no. 1 (December 20, 2018): 6. http://dx.doi.org/10.33317/ssurj.v2i1.68.

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A new structure to develop 64-bit RSA encryption engine on FPGA is being presented in this paper that can be used as a standard device in the secured communication system. The RSA algorithm has three parts i.e. key generation, encryption and decryption. This procedure also requires random generation of prime numbers, therefore, we are proposing an efficient fast Primality testing algorithm to meet the requirement for generating the key in RSA algorithm. We use right-to-left-binary method for the exponent calculation. This reduces the number of cycles enhancing the performance of the system and reducing the area usage of the FPGA. These blocks are coded in Verilog and are synthesized and simulated in Xilinx 13.2 design suit.

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Zhou, Xiabing, Bin Li, Yanrong Qi, and Wanying Dong. "Mimic Encryption Box for Network Multimedia Data Security." Security and Communication Networks 2020 (October 28, 2020): 1–24. http://dx.doi.org/10.1155/2020/8868672.

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With the rapid development of the Internet, the security of network multimedia data has attracted increasingly more attention. The moving target defense (MTD) and cyber mimic defense (CMD) approaches provide a new way to solve this problem. To enhance the security of network multimedia data, this paper proposes a mimic encryption box for network multimedia data security. The mimic encryption box can directly access the network where the multimedia device is located, automatically complete the negotiation, provide safe and convenient encryption services, and effectively prevent network attacks. According to the principles of dynamization, diversification, and randomization, the mimic encryption box uses a reconfigurable encryption algorithm to encrypt network data and uses IP address hopping, port number hopping, protocol camouflage, and network channel change to increase the attack threshold. Second, the mimic encryption box has a built-in pseudorandom number generator and key management system, which can generate an initial random key and update the key with the hash value of the data packet to achieve “one packet, one key.” Finally, through the cooperation of the ARM and the FPGA, an access control list can be used to filter illegal data and monitor the working status of the system in real time. If an abnormality is found, the feedback reconstruction mechanism is used to “clean” the FPGA to make it work normally again. The experimental results and analysis show that the mimic encryption box designed in this paper has high network encryption performance and can effectively prevent data leakage. At the same time, it provides a mimic security defense mechanism at multiple levels, which can effectively resist a variety of network attacks and has high security.

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Rosal, Edni Del, and Sanjeev Kumar. "A Fast FPGA Implementation for Triple DES Encryption Scheme." Circuits and Systems 08, no. 09 (2017): 237–46. http://dx.doi.org/10.4236/cs.2017.89016.

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Singh, Ashmi, Puran Gour, and Brij Bihari Soni. "Survey on FPGA-based Pipelined Architecture for RC5 Encryption." International Journal of Computer Applications 62, no. 4 (January 18, 2013): 28–31. http://dx.doi.org/10.5120/10069-4679.

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Madani, Mahdi, and Camel Tanougast. "FPGA implementation of an optimized A5/3 encryption algorithm." Microprocessors and Microsystems 78 (October 2020): 103212. http://dx.doi.org/10.1016/j.micpro.2020.103212.

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Oukili, Soufiane, and Seddik Bri. "High throughput FPGA Implementation of Advanced Encryption Standard Algorithm." TELKOMNIKA (Telecommunication Computing Electronics and Control) 15, no. 1 (March 1, 2017): 494. http://dx.doi.org/10.12928/telkomnika.v15i1.4713.

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Lakshmi, B., E. Kirubakaran, and T. N. Prabakar. "Design and Implementation of FPGA Based Dual key Encryption." International Journal of Computer Applications 3, no. 3 (June 10, 2010): 21–27. http://dx.doi.org/10.5120/714-1006.

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