Relevant bibliographies by topics / FPGA IP core implementation

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'FPGA IP core implementation'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "FPGA IP core implementation"

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Chhetri, Sujit Rokka, Bikash Poudel, Sandesh Ghimire, Shaswot Shresthamali, and Dinesh Kumar Sharma. "Implementation of Audio Effect Generator in FPGA." Nepal Journal of Science and Technology 15, no. 1 (February 3, 2015): 89–98. http://dx.doi.org/10.3126/njst.v15i1.12022.

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This paper describes the theory and implementation of audio effects such as echo, distortion and pitch-shift in Field Programmable Gate Array (FPGA). At first the mathematical formulation for generation of such effects is explained and then the algorithm is described for its implementation in FPGA using Very high speed integrated circuit hardware descriptive language (VHDL). The digital system being designed, which is synthesizable and reconfigurable, offers a great flexibility and scalability in designing and prototyping in FPGAs. The system is divided into three HDL blocks, each for echo, distortion, and pitch-shift effect generation, which are multiplexed in order to share the common ADC and DAC. The audio effect generator designed in this paper was successfully implemented in Spartan-3E FPGA utilizing the resources available effectively. There has been tremendous research being carried out in the field of IP core. Efficient IP cores designed to carry out digital signal processing are implemented in every modern device using configurable logics. This trend hasn’t yet been realized in Nepal. Through the design and implementation of audio effect generator, this paper also aims at bringing the field of IP core development to limelight among scholars of Nepal.DOI: http://dx.doi.org/10.3126/njst.v15i1.12022 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 89-98
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Ma, Cheng, and Ze Long He. "Implementation of FFT Algorithm Based on IP Core." Advanced Materials Research 981 (July 2014): 426–30. http://dx.doi.org/10.4028/www.scientific.net/amr.981.426.

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—In this paper, we propose a new way to implement the FFT Algorithm, which based on FPGA. At first we introduce the theory of FFT algorithm and its applications. Then the features of FFT IP core based on Altera FPGA is discussed. We elaborate the usage method of the customizable Altera FFT MegaCore function. A logic state machine is designed to create some command signals of this FFT IP core. Finally we use simulation tools Signal-Tap in quartus II inviroment to simulate and debug our FFT control module’s function. The result shows that this new control method of FFT IP core is feasible.
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Wang, Bin, Ju Long Lan, Yun Fei Guo, and Yuan Yang Zhang. "Design and Implementation of the Block Cipher-SMS4 IP Core." Advanced Materials Research 129-131 (August 2010): 881–85. http://dx.doi.org/10.4028/www.scientific.net/amr.129-131.881.

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Block ciphers play an essential role in securing the wireless communications. In this paper, an FPGA implementation of the new block cipher SMS4 is presented. The SMS4 Intellectual Property (IP) core includes a non-pipelined encryption/decryption data path with an on-the-fly key scheduler and supports both the Electronic Code Book (ECB) and Cipher Block Chaining (CBC) operation modes. Our result shows that the SMS4 IP core can achieve a high throughput using only a relatively small area. It is well suitable for the field of area restrained condition.
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Tămas, Tibor, and Sándor Tihamér Brassai. "Hardware Implementation of a Neuro-Fuzzy Controller Using High Level Synthesis Tool." MACRo 2015 1, no. 1 (March 1, 2015): 183–91. http://dx.doi.org/10.1515/macro-2015-0018.

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AbstractThe purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.
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Tolba, Mohammed F., Mohammed E. Fouda, Haneen G. Hezayyin, Ahmed H. Madian, and Ahmed G. Radwan. "Memristor FPGA IP Core Implementation for Analog and Digital Applications." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 8 (August 2019): 1381–85. http://dx.doi.org/10.1109/tcsii.2018.2882496.

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Zeng, Gui Gen, and Jiang Zhe Ren. "Design and Implementation of Configurable FFT/IFFT Soft-Core Based on FPGA." Applied Mechanics and Materials 241-244 (December 2012): 2901–9. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2901.

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As a Basic Transforming Operation between Time Field and Frequency Field, FFT Has Been Widely Used in Detection, Telecommunication, Signal Processing, Multimedia Communication Etc. the Implementation of the FFT Algorithms on FPGA Is Always the Hot Research Spots. in Order to Overcome the Shortcomings on the FPGA Resource Reusability Used in FFT Algorithm, this Article Discusses a New Configurable and High Efficient FFT/IFFT Soft-core Solution. the FFT/IFFT Soft-core Adopts Radix-22 Algorithm and Single-Path Delay Feedback (SDF) Pipeline Structure. its Configurable Factors Include: FFT/IFFT, FFT Points (2n, [3,12] ), Fixed-point Bit Width, Clock Delay of Complex Multiplier. the Design Takes FPGA Chip Stratix II EP2S130F780C4 as Hardware Platform, and the Complete Simulation and Synthesis Is Taken. the Maximum Operating Frequency Is up to 306.30MHz. if 300MHz Clock Frequency Used, 4096-point FFT Could Be Realized in 26.73us, and the Consumption of Memory Resources Is only 148Kbit. Compared with Altera FFT IP-core, Our FFT/IFFT Soft-core Has a Little Bit Longer Computing Time (0.6%). however, the LE Resource Consumption Is only 79% of Altera FFT IP-core. Platform, and the Complete Simulation and Synthesis Is Taken. the Maximum Operating Frequency Is up to 306.30MHz. if 300MHz Clock Frequency Used, 4096-point FFT Could Be Realized in 26.73us, and the Consumption of Memory Resources Is only 148Kbit. Compared with Altera FFT IP-core, Our FFT/IFFT Soft-core Has a Little Bit Longer Computing Time (0.6%). however, the LE Resource Consumption Is only 79% of Altera FFT IP-core.
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Xue, Zhao, Liu Quan, and Xiao Fei Wang. "IP Core Based on the Kalman Filter Algorithm in the FPGA Implementation." Advanced Materials Research 694-697 (May 2013): 1093–97. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.1093.

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This article discusses one-dimensional Kalman filter algorithm using FPGA hardware IP core implementation process. First of all, to program the FPGA matrix operations, implementation of double precision floating point. Then the Kalman filter algorithm programmed in MATLAB, to verify the correctness of the algorithm thinking. Finally the MATLAB language programming algorithm is converted into VHDL language. And call 64 a double precision floating point data algorithm realizes the design of 1-D Kalman filtration algorithm IP core, which make the Kalman filter meet the high precision as well as high speed to complete complex algorithm.
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Tang, Xia Qing, Xiang Liu, Jun Qiang Gao, and Bo Lin. "Design and Implementation of FPGA-Based High-Performance Floating Point Arithmetic Unit." Applied Mechanics and Materials 599-601 (August 2014): 1465–69. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.1465.

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Since FPGA processing data, the presence of fixed-point processing accuracy is not high, and IP Core floating point unit and there are some problems in the use of design risk. Based on the improved floating point unit and program optimization algorithm is designed to achieve single-precision floating-point add / subtract, multiply, and divide operations operator. IP Core for floating-point unit design and FPGA development software provides comparative results: both the maximum clock frequency and latency basically unchanged, while the former occupies less hardware resources, to complete a plus / minus, multiply, divide computation time required for the former than the latter were reduced by 46%, 37% and 57%. The program is downloaded to the FPGA chip to get the same results with the simulation results verify the correctness and feasibility of the design.
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Voronov, K. E., K. I. Sukhachev, and D. S. Vorobev. "Development of Control Module Based on a Computing IP-Core." Rocket-space device engineering and information systems 8, no. 1 (2021): 24–38. http://dx.doi.org/10.30894/issn2409-0239.2021.8.1.24.38.

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The article presents the result of the implementation of a synthesized microcontroller in integrated circuits of small FPGAs and a variant of building a control system for an onboard control module based on the developed solution. The possibility of creating a full-fledged microcontroller based on a type 5578TC034 FPGA and more capacious microcontrollers is shown. The description of the structure of the microcontroller, processor core and periphery is given. The processor instruction system is presented. Ip-modules of peripheral devices and some interfaces have been developed. A variant of creating a control system using the developed microcontroller is proposed. In the future, it is planned to increase the functionality of the synthesized microcontroller by optimizing ip-modules and adding new ones. When developing the control system, a domestic component base was used.
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Durai, Sharmila, and Rangarajan Parthasarathy. "Real Time Implementation of QFT-PUF Architecture for Data Secure System-on-Chip." Journal of Computational and Theoretical Nanoscience 14, no. 1 (January 1, 2017): 511–16. http://dx.doi.org/10.1166/jctn.2017.6355.

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System-on-chip (SoC) face major problem due to vulnerability of hack. The hacker target the cryptographic IP block in the architecture of SoC. However, PUF test wrapper provides the security for individual IP core. The individual IP core protection plays major problem in PUF test. We propose a novel method to protect the IP core with QFT-PUF authentication mechanism. QFT-PUF implement in PSOC-FPGA. The mechanism reduces the area and memory in architecture. The proposed method of key generation and their handling process drive from Quantum Fourier Transform. From the validation of QFT-PUF, Fault Acceptance Rate (FAR) increases then the Fault Rejection Rate (FRR).
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Dissertations / Theses on the topic "FPGA IP core implementation"

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Chandrasekaran, Shrutisagar. "Efficient FPGA implementation and power modelling of image and signal processing IP cores." Thesis, Brunel University, 2007. http://bura.brunel.ac.uk/handle/2438/7301.

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Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed.
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Fernando, Pradeep Ruben. "Genetic Algorithm Based Design and Optimization of VLSI ASICs and Reconfigurable Hardware." Scholar Commons, 2008. https://scholarcommons.usf.edu/etd/1963.

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Rapid advances in integration technology have tremendously increased the design complexity of very large scale integrated (VLSI) circuits, necessitating robust optimization techniques in many stages of VLSI design. A genetic algorithm (GA) is a stochastic optimization technique that uses principles derived from the evolutionary process in nature. In this work, genetic algorithms are used to alleviate the hardware design process of VLSI application specific integrated circuits (ASICs) and reconfigurable hardware. VLSI ASIC design suffers from high design complexity and a large number of optimization objectives requiring hierarchical design approaches and multi-objective optimization techniques. The floorplanning stage of the design cycle becomes highly important in hierarchical design methods. In this work, a multi-objective genetic algorithm based floorplanner has been developed with novel crossover operators to address the multi-objective floorplanning problem for VLSI ASICs. The genetic floorplanner achieves significant wirelength savings (>19% on average) with little or no increase in area ( < 3% penalty) over previous floorplanners that perform simultaneous area and wirelength minimization. Hardware implementation of genetic algorithms is gaining importance because of their proven effectiveness as optimization engines for real-time applications. Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid pre-defined system architecture, and lack of support for multiple fitness functions. A compact IP core that implements a general purpose GA engine has been designed to realize evolvable hardware in field programmable gate array devices. The designed GA core achieved a speedup of around 5.16x over an analogous software implementation. Novel reconfigurable analog architectures have been proposed to realize extreme environment analog electronics. In this work, a digital framework has been developed to realize self reconfigurable analog arrays (SRAA) where genetic algorithms are used to evolve the required analog functionality and compensate performance degradation in extreme environments. The framework supports two methods of compensation, namely, model based lookup and genetic algorithm based compensation and is scalable in terms of the number of fitness evaluation modules. The entire framework has been implemented as a digital ASIC in a leading industrystrength silicon-on-insulator (SOI) technology to obtain high performance and a small form factor.
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Hráček, Marek. "IP core pro řízení BLDC motorů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399455.

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This diploma thesis is about using vector control (or field-oriented control) of synchronous BLDC and PMSM motors on FPGAs. First part describes basic theory of these motors and how to control them. Then vector control is detailed and its parts as (or Clarke) and Park transformation. Rest of the thesis deals with the design of universal controller with adjustable accuracy in VHDL language. Data is separated from computing part which utilizes custom arithmetic-logic unit. In the last part of the thesis the design is tested in simulator using model of PMSM motor.
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Borslehag, Tobias. "Implementation of a Gigabit IP router on an FPGA platform." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5186.

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The computer engineering group at Linköping University has parts of their research dedicated to networks-on-chip and components used in network components and terminals. This research has among others resulted in the SoCBUS NOC and a flow based network protocol processor. The main objective of this project was to integrate these components into an IP router with two or more Gigabit Ethernet interfaces.

A working system has been designed and found working. It consists of three main components, the input module, the output module and a packet buffer. Due to the time constraint and the size of the project the packet buffer could not be designed to be as efficient as possible, thus reducing the overall performance. The SoCBUS also has negative impact on performance, although this could probably be reduced with a revised system design. If such a project is carried out it could use the input and output modules from this project, which connect to SoCBUS and can easily be integrated with other packet buffers and system designs.

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Rangoonwala, Sakina. "A Verilog 8051 Soft Core for FPGA Applications." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc11013/.

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The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.
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Nagalakshmi, Subramanya. "Study of FPGA implementation of entropy norm computation for IP data streams." [Tampa, Fla] : University of South Florida, 2008. http://purl.fcla.edu/usf/dc/et/SFE0002477.

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Davari, Mahdad. "Improving an FPGA Optimized Processor." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71190.

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This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.
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Souto, Maior de Lima Marilia. "ipProcess: um processo para desenvolvimento de IP-Cores com implementação em FPGA." Universidade Federal de Pernambuco, 2005. https://repositorio.ufpe.br/handle/123456789/2761.

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Made available in DSpace on 2014-06-12T16:01:00Z (GMT). No. of bitstreams: 2 arquivo7128_1.pdf: 2072446 bytes, checksum: b6bc5386371d917bd7613b206ac8e92f (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005
A demanda cada vez maior por produtos eletronicos e a crescente capacidade de integração dos chips direcionaram a metodologia de projeto de sistemas embarcados para sua completa integração em um único chip ( System-on-Chip, ou SoC). Essa metodologia baseia-se cada vez mais em componentes previamente projetados e verificados (IP-core ) como uma alternativa de disponibilizar os sistemas dentro dos prazos esperados, sem perder o time-to-market do mercado consumidor de eletrônicos. Neste trabalho, é proposto um processo de desenvolvimento de IP-cores baseado em técnicas de engenharia de software chamado ipPROCESS, como um mecanismo de facilitar e promover o desenvolvimento de IP-cores de alta qualidade. Tendo o foco na criação de componentes de qualidade, o ipPROCESS foi definido com base em técnicas de verificação funcional, de modelagem visual da arquitetura, de interface de comunicação e de documentação seguindo os padrões da indústria. O processo foi descrito utilizando o meta-modelo UML denominado SPEM com o objetivo de facilitar e acelerar o seu entendimento, assim como permitir alterações futuras e facilitar o gerenciamento de projetos baseados no processo proposto
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Eriksson, Mattias. "Design and Implementation of a Real-Time FFT-core for Frequency Domain Triggering." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-99374.

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To efficiently capture signal events when performing analog measurements, a competent toolbox is required. In this master thesis, a system for frequency domain triggering is designed and implemented. The implemented system provides advanced frequency domain trigger conditions, in order to ease the capture of a desired signal event. A real-time 1024-point pipelined feedforward FFT-core is implemented to transform the signal from the time domain to the frequency domain. The system is designed and synthesized for a Virtex-6 FPGA (XC6VLX240T) and is integrated into SP Devices’ digitizer ADQ1600. The implemented system is able to handle a continuous stream of 1.6GS/s at 16-bit. A small software API is developed that provides runtime configuration of the Triggering conditions.
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Mattson, Robert. "Evaluation of PicoBlaze and implementation of a network interface on a FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2398.

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The use of microcontrollers and FPGAs is getting more and more wide spread in electronic designs. A recent developmenthas been to implement microcontrollers onboard the FPGA, there are a lot of benefits but also disadvantages with this. Often the microcontroler requires a lot of resources in the expensive FPGA. This is where PicoBlaze, a microcontroller provided by Xilinx, fits in. It is designed with one main object, keep it as small and powerful as possible.

In this report PicoBlaze is evaluated and documented. Two implementations have been done. One smaller to show how to use PicoBlaze and one larger implementation of an Ethernet network interface. The function of the implementations have been verified on a experiment board utilizing a Virtex-II FPGA.

The conclusion is that PicoBlaze is a very powerful microcontroller in comparison to the resources it uses on the FPGA. It uses only a little more than 80 slices on a Virtex II FPGA. This is its main advantage, the disadvantages of PicoBlaze is its limited program memory and the limited address space.

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Books on the topic "FPGA IP core implementation"

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IPv6 Core Protocols Implementation (The Morgan Kaufmann Series in Networking). Morgan Kaufmann, 2006.

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Book chapters on the topic "FPGA IP core implementation"

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Liu, Boyang. "Research and Implementation of RSA IP Core Based on FPGA." In Data Processing Techniques and Applications for Cyber-Physical Systems (DPTA 2019), 1311–19. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1468-5_154.

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Deeksha Jain and Swati Shrivastava. "FPGA Implementation of UDP/IP Stack Using TSE IP Core and Transfer Data at 1 Gbps." In Proceeding of International Conference on Intelligent Communication, Control and Devices, 1103–11. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1708-7_131.

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Sun, JiangFeng, and Feng Chen. "Three IP Soft-Core Designs of ADC and FPGA Verification." In Communications in Computer and Information Science, 123–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31968-6_15.

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Kamat, Rajanish K., Santosh A. Shinde, Pawan K. Gaikwad, and Hansraj Guhilot. "Analog Front End and FPGA Based Soft IP Core for ECG Logger." In Harnessing VLSI System Design with EDA Tools, 51–91. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1864-7_3.

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Kopczynski, Maciej, Tomasz Grzes, and Jaroslaw Stepaniuk. "Generating Core in Rough Set Theory: Design and Implementation on FPGA." In Rough Sets and Intelligent Systems Paradigms, 209–16. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-08729-0_20.

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Liu, Boyang. "Real-Time Video Edge Enhancement IP Core Based on FPGA and Sobel Operator." In Advances in Intelligent Systems and Computing, 123–29. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-15235-2_19.

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Peng, Bo-Yuan, Yuan-Che Hsu, Yu-Jia Chen, Di-Chia Chueh, Chen-Mou Cheng, and Bo-Yin Yang. "Multi-core FPGA Implementation of ECC with Homogeneous Co-Z Coordinate Representation." In Cryptology and Network Security, 637–47. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-48965-0_42.

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Moon, Cheol-Hong, and Woo-Chun Jang. "Implementation of LED Array Color Temperature Controlled Lighting System Using RISC IP Core." In Emerging Intelligent Computing Technology and Applications, 753–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-04070-2_81.

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Wang, Jianye, Cang Liu, Peng Jing, and Chao Zhou. "Implement IP Core of the Conversion Between Fixed-point Format and Floating-point Format on FPGA." In Lecture Notes in Electrical Engineering, 975–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-34522-7_102.

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Saqib, Nazar A., Francisco Rodríguez-Henríquez, and Arturo Díaz-Pérez. "Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core." In Field Programmable Logic and Application, 303–12. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_30.

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Conference papers on the topic "FPGA IP core implementation"

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Zhang Juntao and Ma Wenbo. "Implementation of general CORDIC IP core based on FPGA." In 2011 IEEE International Conference on Computer Science and Automation Engineering (CSAE). IEEE, 2011. http://dx.doi.org/10.1109/csae.2011.5952751.

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Phan, Thi-Thanh-Dung, Van-Phuc Hoang, and Van-Lan Dao. "An efficient FPGA implementation of AES-CCM authenticated encryption IP core." In 2016 3rd National Foundation for Science and Technology Development Conference on Information and Computer Science (NICS). IEEE, 2016. http://dx.doi.org/10.1109/nics.2016.7725650.

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Rekha, R., and Karunakara P. Menon. "FPGA implementation of exponential function using cordic IP core for extended input range." In 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2018. http://dx.doi.org/10.1109/rteict42901.2018.9012611.

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Altuncu, Mehmet Ali, Mehmet Muzaffer Kosten, Metaet Ali Cavuslu, and Suhap Sahin. "FPGA-based implementation of basic image processing applications as low-cost IP core." In 2018 26th Signal Processing and Communications Applications Conference (SIU). IEEE, 2018. http://dx.doi.org/10.1109/siu.2018.8404175.

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Pradeep Fernando, Hariharan Sankaran, Srinivas Katkoori, Didier Keymeulen, Adrian Stoica, Ricardo Zebulum, and Ramesham Rajeshuni. "A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine." In Distributed Processing Symposium (IPDPS). IEEE, 2008. http://dx.doi.org/10.1109/ipdps.2008.4536534.

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Hassine, Siwar Ben Haj, Mehdi Jemai, and Bouraoui Ouni. "Design and FPGA implementation of ternary hardware IP core for square root function." In 2017 International Conference on Engineering & MIS (ICEMIS). IEEE, 2017. http://dx.doi.org/10.1109/icemis.2017.8273043.

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Israsena, Wattanawong, Meenakarn, Chupayak, Jewajinda, Duangtanoo, and Juakvont. "A TDMA/TDD processing unit IP core for WLL cell station targeting FPGA implementation." In 2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03. IEEE, 2003. http://dx.doi.org/10.1109/icasic.2003.1277333.

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Borcsok, Josef, Ali Hayek, Bashier Machmur, and Muhammad Umar. "Design and implementation of an IP-core based safety-related communication architecture on FPGA." In 2009 XXII International Symposium on Information, Communication and Automation Technologies. ICAT 2009. IEEE, 2009. http://dx.doi.org/10.1109/icat.2009.5348448.

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Wang Yaqin, Liu Xuebin, and Hu Bingliang. "Implementation of a LMS filter on FPGA employing extremeDSP and smart IP-core design." In Instruments (ICEMI). IEEE, 2011. http://dx.doi.org/10.1109/icemi.2011.6037920.

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Huang, Weihua, and Licheng Jia. "FPGA-based Matrix Keyboard Common IP Core Design and the Implementation Using Verilog HDL." In 2017 Second International Conference on Mechanical, Control and Computer Engineering (ICMCCE). IEEE, 2017. http://dx.doi.org/10.1109/icmcce.2017.53.

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