Dissertations / Theses: 'FPGA IP core implementation'

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Chandrasekaran, Shrutisagar. "Efficient FPGA implementation and power modelling of image and signal processing IP cores." Thesis, Brunel University, 2007. http://bura.brunel.ac.uk/handle/2438/7301.

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Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed.

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Fernando, Pradeep Ruben. "Genetic Algorithm Based Design and Optimization of VLSI ASICs and Reconfigurable Hardware." Scholar Commons, 2008. https://scholarcommons.usf.edu/etd/1963.

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Rapid advances in integration technology have tremendously increased the design complexity of very large scale integrated (VLSI) circuits, necessitating robust optimization techniques in many stages of VLSI design. A genetic algorithm (GA) is a stochastic optimization technique that uses principles derived from the evolutionary process in nature. In this work, genetic algorithms are used to alleviate the hardware design process of VLSI application specific integrated circuits (ASICs) and reconfigurable hardware. VLSI ASIC design suffers from high design complexity and a large number of optimization objectives requiring hierarchical design approaches and multi-objective optimization techniques. The floorplanning stage of the design cycle becomes highly important in hierarchical design methods. In this work, a multi-objective genetic algorithm based floorplanner has been developed with novel crossover operators to address the multi-objective floorplanning problem for VLSI ASICs. The genetic floorplanner achieves significant wirelength savings (>19% on average) with little or no increase in area ( < 3% penalty) over previous floorplanners that perform simultaneous area and wirelength minimization. Hardware implementation of genetic algorithms is gaining importance because of their proven effectiveness as optimization engines for real-time applications. Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid pre-defined system architecture, and lack of support for multiple fitness functions. A compact IP core that implements a general purpose GA engine has been designed to realize evolvable hardware in field programmable gate array devices. The designed GA core achieved a speedup of around 5.16x over an analogous software implementation. Novel reconfigurable analog architectures have been proposed to realize extreme environment analog electronics. In this work, a digital framework has been developed to realize self reconfigurable analog arrays (SRAA) where genetic algorithms are used to evolve the required analog functionality and compensate performance degradation in extreme environments. The framework supports two methods of compensation, namely, model based lookup and genetic algorithm based compensation and is scalable in terms of the number of fitness evaluation modules. The entire framework has been implemented as a digital ASIC in a leading industrystrength silicon-on-insulator (SOI) technology to obtain high performance and a small form factor.

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Hráček, Marek. "IP core pro řízení BLDC motorů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399455.

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This diploma thesis is about using vector control (or field-oriented control) of synchronous BLDC and PMSM motors on FPGAs. First part describes basic theory of these motors and how to control them. Then vector control is detailed and its parts as (or Clarke) and Park transformation. Rest of the thesis deals with the design of universal controller with adjustable accuracy in VHDL language. Data is separated from computing part which utilizes custom arithmetic-logic unit. In the last part of the thesis the design is tested in simulator using model of PMSM motor.

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Borslehag, Tobias. "Implementation of a Gigabit IP router on an FPGA platform." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5186.

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The computer engineering group at Linköping University has parts of their research dedicated to networks-on-chip and components used in network components and terminals. This research has among others resulted in the SoCBUS NOC and a flow based network protocol processor. The main objective of this project was to integrate these components into an IP router with two or more Gigabit Ethernet interfaces.

A working system has been designed and found working. It consists of three main components, the input module, the output module and a packet buffer. Due to the time constraint and the size of the project the packet buffer could not be designed to be as efficient as possible, thus reducing the overall performance. The SoCBUS also has negative impact on performance, although this could probably be reduced with a revised system design. If such a project is carried out it could use the input and output modules from this project, which connect to SoCBUS and can easily be integrated with other packet buffers and system designs.

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Rangoonwala, Sakina. "A Verilog 8051 Soft Core for FPGA Applications." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc11013/.

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The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.

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Nagalakshmi, Subramanya. "Study of FPGA implementation of entropy norm computation for IP data streams." [Tampa, Fla] : University of South Florida, 2008. http://purl.fcla.edu/usf/dc/et/SFE0002477.

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Davari, Mahdad. "Improving an FPGA Optimized Processor." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71190.

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This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.

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Souto, Maior de Lima Marilia. "ipProcess: um processo para desenvolvimento de IP-Cores com implementação em FPGA." Universidade Federal de Pernambuco, 2005. https://repositorio.ufpe.br/handle/123456789/2761.

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Made available in DSpace on 2014-06-12T16:01:00Z (GMT). No. of bitstreams: 2 arquivo7128_1.pdf: 2072446 bytes, checksum: b6bc5386371d917bd7613b206ac8e92f (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005
A demanda cada vez maior por produtos eletronicos e a crescente capacidade de integração dos chips direcionaram a metodologia de projeto de sistemas embarcados para sua completa integração em um único chip ( System-on-Chip, ou SoC). Essa metodologia baseia-se cada vez mais em componentes previamente projetados e verificados (IP-core ) como uma alternativa de disponibilizar os sistemas dentro dos prazos esperados, sem perder o time-to-market do mercado consumidor de eletrônicos. Neste trabalho, é proposto um processo de desenvolvimento de IP-cores baseado em técnicas de engenharia de software chamado ipPROCESS, como um mecanismo de facilitar e promover o desenvolvimento de IP-cores de alta qualidade. Tendo o foco na criação de componentes de qualidade, o ipPROCESS foi definido com base em técnicas de verificação funcional, de modelagem visual da arquitetura, de interface de comunicação e de documentação seguindo os padrões da indústria. O processo foi descrito utilizando o meta-modelo UML denominado SPEM com o objetivo de facilitar e acelerar o seu entendimento, assim como permitir alterações futuras e facilitar o gerenciamento de projetos baseados no processo proposto

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Eriksson, Mattias. "Design and Implementation of a Real-Time FFT-core for Frequency Domain Triggering." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-99374.

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To efficiently capture signal events when performing analog measurements, a competent toolbox is required. In this master thesis, a system for frequency domain triggering is designed and implemented. The implemented system provides advanced frequency domain trigger conditions, in order to ease the capture of a desired signal event. A real-time 1024-point pipelined feedforward FFT-core is implemented to transform the signal from the time domain to the frequency domain. The system is designed and synthesized for a Virtex-6 FPGA (XC6VLX240T) and is integrated into SP Devices’ digitizer ADQ1600. The implemented system is able to handle a continuous stream of 1.6GS/s at 16-bit. A small software API is developed that provides runtime configuration of the Triggering conditions.

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Mattson, Robert. "Evaluation of PicoBlaze and implementation of a network interface on a FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2398.

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The use of microcontrollers and FPGAs is getting more and more wide spread in electronic designs. A recent developmenthas been to implement microcontrollers onboard the FPGA, there are a lot of benefits but also disadvantages with this. Often the microcontroler requires a lot of resources in the expensive FPGA. This is where PicoBlaze, a microcontroller provided by Xilinx, fits in. It is designed with one main object, keep it as small and powerful as possible.

In this report PicoBlaze is evaluated and documented. Two implementations have been done. One smaller to show how to use PicoBlaze and one larger implementation of an Ethernet network interface. The function of the implementations have been verified on a experiment board utilizing a Virtex-II FPGA.

The conclusion is that PicoBlaze is a very powerful microcontroller in comparison to the resources it uses on the FPGA. It uses only a little more than 80 slices on a Virtex II FPGA. This is its main advantage, the disadvantages of PicoBlaze is its limited program memory and the limited address space.

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Walsh, Declan. "Design and implementation of massively parallel fine-grained processor arrays." Thesis, University of Manchester, 2015. https://www.research.manchester.ac.uk/portal/en/theses/design-and-implementation-of-massively-parallel-finegrained-processor-arrays(e0e03bd5-4feb-4d66-8d4b-0e057684e498).html.

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This thesis investigates the use of massively parallel fine-grained processor arrays to increase computational performance. As processors move towards multi-core processing, more energy-efficient processors can be designed by increasing the number of processor cores on a single chip rather than increasing the clock frequency of a single processor. This can be done by making processor cores less complex, but increasing the number of processor cores on a chip. Using this philosophy, a processor core can be reduced in complexity, area, and speed to form a very small processor which can still perform basic arithmetic operations. Due to the small area occupation this can be multiplied and scaled to form a large scale parallel processor array to offer a significant performance. Following this design methodology, two fine-grained parallel processor arrays are designed which aim to achieve a small area occupation with each individual processor so that a larger array can be implemented over a given area. To demonstrate scalability and performance, SIMD parallel processor array is designed for implementation on an FPGA where each processor can be implemented using four ‘slices’ of a Xilinx FPGA. With such small area utilization, a large fine-grained processor can be implemented on these FPGAs. A 32 × 32 processor array is implemented and fast processing demonstrated using image processing tasks. An event-driven MIMD parallel processor array is also designed which occupies a small amount of area and can be scaled up to form much larger arrays. The event-driven approach allows the processor to enter an idle mode when no events are occurring local to the processor, reducing power consumption. The processor can switch to operational mode when events are detected. The processor core is designed with a multi-bit data path and ALU and contains its own instruction memory making the array a multi-core processor array. With area occupation of primary concern, the processor is relatively simple and connects with its four nearest direct neighbours. A small 8 × 8 prototype chip is implemented in a 65 nm CMOS technology process which can operate at a clock frequency of 80 MHz and offer a peak performance of 5.12 GOPS which can be scaled up to larger arrays. An application of the event-driven processor array is demonstrated using a simulation model of the processor. An event-driven algorithm is demonstrated to perform distributed control of distributed manipulator simulator by separating objects based on their physical properties.

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Wyngaard, Janet Ruth. "An FPGA implementation of an investigative many-core processor, Fynbos : in support of a Fortran autoparallelising software pipeline." Doctoral thesis, University of Cape Town, 2014. http://hdl.handle.net/11427/13265.

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Includes bibliographical references.
In light of the power, memory, ILP, and utilisation walls facing the computing industry, this work examines the hypothetical many-core approach to finding greater compute performance and efficiency. In order to achieve greater efficiency in an environment in which Moore’s law continues but TDP has been capped, a means of deriving performance from dark and dim silicon is needed. The many-core hypothesis is one approach to exploiting these available transistors efficiently. As understood in this work, it involves trading in hardware control complexity for hundreds to thousands of parallel simple processing elements, and operating at a clock speed sufficiently low as to allow the efficiency gains of near threshold voltage operation. Performance is there- fore dependant on exploiting a new degree of fine-grained parallelism such as is currently only found in GPGPUs, but in a manner that is not as restrictive in application domain range. While removing the complex control hardware of traditional CPUs provides space for more arithmetic hardware, a basic level of control is still required. For a number of reasons this work chooses to replace this control largely with static scheduling. This pushes the burden of control primarily to the software and specifically the compiler, rather not to the programmer or to an application specific means of control simplification. An existing legacy tool chain capable of autoparallelising sequential Fortran code to the degree of parallelism necessary for many-core exists. This work implements a many-core architecture to match it. Prototyping the design on an FPGA, it is possible to examine the real world performance of the compiler-architecture system to a greater degree than simulation only would allow. Comparing theoretical peak performance and real performance in a case study application, the system is found to be more efficient than any other reviewed, but to also significantly under perform relative to current competing architectures. This failing is apportioned to taking the need for simple hardware too far, and an inability to implement static scheduling mitigating tactics due to lack of support for such in the compiler.

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Noumon, Allini Elie. "Caractérisation, évaluation et utilisation du jitter d'horloge comme source d'aléa dans la sécurité des données." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSES019.

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Cette thèse, financée par la DGA, est motivée par la problématique d’évaluation des TRNG pour des applications à très haut niveau de sécurité. Les standards actuels tels que AIS-31 n’étant pas suffisants pour ces types d’applications, la DGA propose une procédure complémentaire, validée sur les TRNG utilisant les oscillateurs en anneau (RO), qui vise à caractériser la source d’aléa des TRNG afin d’identifier les bruits électroniques présents dans celle-ci. Ces bruits se traduisent dans les circuits numériques par le jitter d’horloge générée dans les RO. Ils peuvent être caractérisés par leur densité spectrale de puissance reliée à la variance d’Allan temporelle qui permet, contrairement à la variance standard pourtant encore largement utilisée, de discriminer ces différents types de bruit (thermique, flicker principalement). Cette étude a servi de base à l’estimation de la part du jitter due au bruit thermique utilisé dans les modèles stochastiques décrivant la sortie des TRNG. Afin d’illustrer et de valider l’approche de certification DGA sur d’autres principes de TRNG que les RO, nous proposons une caractérisation de la PLL en tant que source d’aléa. Nous avons modélisé la PLL en termes de fonctions de transfert. Cette modélisation a conduit à l’identification de la source de bruit en sortie de la PLL, ainsi que de sa nature en fonction des paramètres physiques de la PLL. Cela a permis de proposer des recommandations quant au choix des paramètres afin de garantir une entropie maximale. Afin d’aider à la conception de ce type de TRNG, nous proposons également un outil de recherche des paramètres non physiques du générateur assurant le meilleur compromis sécurité/débit
This thesis, funded by the DGA, is motivated by the problem of evaluation of TRNG for applications with a very high level of security. As current standards such as AIS-31 are not sufficient for these types of applications, the DGA proposes a complementary procedure, validated on TRNG using ring oscillators (RO), which aims to characterize the source of randomness of TRNG in order to identify electronic noises present in it. These noises are manifested in the digital circuits by the clock jitter generated in the RO. They can be characterized by their power spectral density related to the time Allan variance which allows, unlike the standard variance which is still widely used, to discriminate these different types of noise (mainly thermal, flicker). This study was used as a basis for estimating the proportion of jitter due to thermal noise used in stochastic models describing the output of TRNG. In order to illustrate and validate the DGA certification approach on other principles of TRNG apart from RO, we propose a characterization of PLL as a source of randomness. We have modeled the PLL in terms of transfer functions. This modeling has led to the identification of the source of noise at the output of the PLL, as well as its nature as a function of the physical parameters of the PLL. This allowed us to propose recommendations on the choice of parameters to ensure maximum entropy. In order to help in the design of this type of TRNG, we also propose a tool to search for the non-physical parameters of the generator ensuring the best compromise between security and throughput

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Liu, Yuan-Shuang. "The FPGA implementation of a jitter measurement infrastructure IP." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2907200417284200.

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Lian, Chung-Jr, and 連崇志. "The Design and Implementation of JPEG Encoder IP Core." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/50590808946850040350.

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碩士
國立臺灣大學
電機工程學研究所
87
Data compression is important for the limited bandwidth and the cost of storage in the digital multimedia world. Recently, applications such as digital camera and scanner develop fast. The development of digital camera has entered the million-pixel era, and it still keeps moving ahead. For the scanners, not only the resolution is higher and higher, but the supported scannable paper size is also larger and larger. The transmission time is too long, and the cost for storage is too high due to such large amount of data. JPEG, a widely used still image compression and coding standard, is the best choice to solve these problems for its ability to provide high compression ratio and controllable trade-off between compression and image quality. The hardware implementation of JPEG codec for these applications, therefore, becomes a hot topic again. In this thesis, we design and implement a Baseline JPEG encoder IP Core. The design is highly modularized and optimized. Fully pipelined design makes it compact and efficient with low latency and high throughput. The main modules include Discrete Cosine Transform (DCT), Quantizer, Variable Length Coder (VLC), and Packer. The design is verified correct by Verilog and Timemill simulations. It is very practical that this IP can be integrated with other application systems, such as scanner and DSC (Digital Still Camera) applications, etc. Furthermore, every module, such as Discrete Cosine Transform, Quantizer, and Packer is also a reusable IP component independently, being able to applied to other related video standards, such as MPEG, and H.26X.

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Hsu, Han-Jen, and 許瀚仁. "Design and Implementation of Dual-mode DCT IP Core and Reconfigurable DSP Processor." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/69479246943881421764.

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碩士
國立中興大學
電機工程學系
91
In this thesis, we propose a cost-effective 2-D Discrete Cosine Transform IP Core with reconfigurable datapath. The chip can process 8 × 8 block of video sequence. Even-odd decomposition is suitable for VLSI implementation. The architecture includes of two types of reconfigurable processor to process even and odd data. We use two mode operations of reconfigurable datapaths to achieve high speed and low power consumption. The precision of wordlength can meet the requirement of CCITT standard. A prototype chip is implemented in Artisan 0.25μm cell library and fabricated by TSMC 0.25μm 1P5M technology. This chip includes a texture transpose memory, two DCT processors, pre-adder and the total transistor count is 77822. The die size is 1.38×1.38 mm2. The operation speed of post-layout simulation can reach 56 MHz. Static timing analysis is also used to verify the chip. The power consumption is 14.17mW@56 MHz and 7.89mW@28 MHz. Because of the approach of the decade of System-on-Chip (SOC), the traditional ASIC is inefficient to use. Though how to map different algorithms in the same hardware, to reduce the hardware cost and design time is more important. Reconfigurable computing is the latest research topic. In this thesis, we propose a Reconfigurable DSP processor to implement the algorithms of video processing and digital signal processing. Such as Discrete Cosine Transform (DCT), motion estimation, FIR filter, and Discrete Fourier Transform (DFT). The reconfigurable processor plays the role of co-processor in whole system to increase the performance of system.

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Chen, Cheng-huang, and 陳政煌. "FPGA Hardware Software Co-design for Implementation of Heterogeneous Multi-Core SoC platform." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/42481445910603088078.

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碩士
國立高雄第一科技大學
電腦與通訊工程所
99
For system implementation, hardware/software co-design becomes a key skill. The main techniques include software design for Embedded SoC., the Coding of system initial, specification models, Verilog/VHDL for circuit design, synthesis and verification. This study was on the basis of PAC Duo education platform SoC, which was developed by Industrial Technology Research Institute. We research FPGA board to expand SOC platforms through the AMBA AHB interface. This architecture consists of SoC and FPGA prototype to verify hardware and software platform. The main component of FPGA board is XC3S2000 series and its chip contains 2 million gate counts with 90 nano-process, and achieves 326MHZ clock rate and keeps the low cost superiority. Based on the architecture, this study completed the basic SIP package and verification, which control 7 segment LED and picture operation access of FPGA board via AMBA BUS of Soc. Continuously, the designed SIP Wrapper can download into FPGA to comply with the AMBA Bus Master / Slave framework.. Finally, we use ADS Program to run the application and system initialization to complete the prototype hardware and software system design and verification. We had successfully developed the software/hardware co-design system with FPGA and embedded SOC chips. The data can be transferred with synchronous control with real time demonstration.

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Capalija, Davor. "Microarchitecture and FPGA Implementation of the Multi-level Computing Architecture." Thesis, 2008. http://hdl.handle.net/1807/11134.

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We design the microarchitecture of the Multi-Level Computing Architecture (MLCA), focusing on its Control Processor (CP). The design of the microarchitecture of the CP faces us with both opportunities and challenges that stem from the coarse granularity of the tasks and the large number of inputs and outputs for each task instruction. Thus, we explore changes to standard superscalar microarchitectural techniques. We design the entire CP microarchitecture and implement it on an FPGA using SystemVerilog. We synthesize and evaluate the MLCA system based on a 4-processor shared-memory multiprocessor. The performance of realistic applications shows scalable speedups that are comparable to that of simulation. We believe that our implementation achieves low complexity in terms of FPGA resource usage and operating frequency. In addition, we argue that our design methodology allows the scalability of the CP as the entire system grows.

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Tsai, Ying-Ming, and 蔡穎銘. "Design and Implementation of the High-performance Low Power Multi-MPEG Bitstream Processing IP Core." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/01422315931757173981.

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碩士
國立中正大學
資訊工程研究所
92
Nowadays, the main data presentation of video is in digital form. As the development and requirements of the multimedia technologies and applications grows, a large mount of data is required to be stored and transmitted. Therefore, the digital data are compressed into bitstream according to the popular MPEG video compression techniques for efficient storage and communication. With respect to different video coding standards, the syntax of bitstreams are also different. So, to parse Multi-MPEG bitstreams efficiently is an important issue to meet real time requirements in various video applications. In this thesis, we propose a Multi-MPEG Bitstream Processing IP core. For achiecing both high performance and low power purposes, we propose a “Fast Aligning Response Shift (FARS)” approach in handling the bitstream parsing efficiently. Based on the UMC 0.18μm CMOS technology, we finish the proposed design in terms of behavioral simulation through C-language modeling, RTL modeling through Verilog, gate-level modeling through Synopsys and FPGA realization through Xilinx ISE. We find that the optimal working frequency in the proposed design achieves 65MHz. As compared with other designs, the proposed design not only outperforms others in terms of less hardware cost and higher processing speed, but also possesses much less power consumption than others (i.e. reducing 72% power consumption). The result of comparisons shows the good performance of the proposed design. About IP qualification of the proposed IP core, we use NOVAS nLint Code Checking tool to examine the RTL code, ModelSim CodeCoverage tool to examine the code coverage rate of the provided testbench, and Synopsys Formality tool to examine the formal functional verification. In addition, we also complete the system verification and FPGA verification of the proposed IP core.

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Yen, Shou-Te, and 顏守德. "A Rapid Prototyping Reconfigurable Computing System Design and Implementation with Its Application of AES IP Core." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/13659585936504632270.

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碩士
逢甲大學
資訊工程所
92
Reconfigurable computing architecture is the hardware structure of a kind of customer computer machine that is lain between general propose processor and ASIC. Have elasticity that software can be reconfigured and advantage that the hardware can be carried out with higher speed. Reconfigurable rapid prototyping system and have FPGA to realize that can reconfigure the architecture of computing. It is the operating platform which verifies the prototyping function and design environment. The rapid prototyping system with multi-FPGA can offer the merger of the board levels of multiple function core modules, or divide the result put within different chips after the large-scale circuit of emulation is designed and cut. In this thesis, develop a reconfigurable rapid prototyping system taking PCI as interface. Reconfigurable processing unit uses I/O coupling way and general propose processor to work in coordination and to accelerate the execution of the specific task. Use four FPGA chip in order to offer the hardware design environment under multi-FPGA structures systematically at the same time. This system except that the intact hardware is designed and implemented, but also include the setting-up of the driver with offer the application program interface which access the hardware. In order to prove that systematic function of rapid prototyping board is correct, design one IP Core to apply to this system in this thesis. We implement an Advanced Encryption Standard (AES) hardware circuit for this goal. The focal point designed lies in making optimization for algorithmic and architectural with AES suitability in reconfigurable computing with multi-FPGA system.

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Sá, José Ricardo Silva de. "Study on the FPGA implementation of the conversion of uncompressed High-Definition video signals for distribution over IP networks." Dissertação, 2016. https://repositorio-aberto.up.pt/handle/10216/89271.

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O transporte e distribuição de video UHD sobre formatos SDI convencionais perde alguma flexibilidade se não for aproveitada a crescente utilização e desenvolvimento das redes IP. Para a conversão entre plataformas, são necessários sistemas de alta performance em tempo real que garantam fielmente o funcionamento e conversão sem perdas. Estes sistemas são complexos e utilizam várias funcionalidades críticas e IP cores. Este trabalho visou efetuar um estudo acerca do uso de FPGAs na conversão de plataformas, validando e estudando os diferentes componentes, blocos e funcionalidades que devem e podem ser utilizados para que o vídeo possa ser processado dentro das melhores condições. Foi realizado um protótipo na fase final.

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Sá, José Ricardo Silva de. "Study on the FPGA implementation of the conversion of uncompressed High-Definition video signals for distribution over IP networks." Master's thesis, 2016. https://repositorio-aberto.up.pt/handle/10216/89271.

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Abstract:

O transporte e distribuição de video UHD sobre formatos SDI convencionais perde alguma flexibilidade se não for aproveitada a crescente utilização e desenvolvimento das redes IP. Para a conversão entre plataformas, são necessários sistemas de alta performance em tempo real que garantam fielmente o funcionamento e conversão sem perdas. Estes sistemas são complexos e utilizam várias funcionalidades críticas e IP cores. Este trabalho visou efetuar um estudo acerca do uso de FPGAs na conversão de plataformas, validando e estudando os diferentes componentes, blocos e funcionalidades que devem e podem ser utilizados para que o vídeo possa ser processado dentro das melhores condições. Foi realizado um protótipo na fase final.

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Rinzler, Daniel G. "Design and implementation of an FPGA-based image processor exploring a distributed data multi-core co-processor architecture /." 2009. http://etd.nd.edu/ETD-db/theses/available/etd-07212009-135252/.

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Thesis (M.S.C.S.E.)--University of Notre Dame, 2009.
Thesis directed by Jay Brockman for the Department of Computer Science and Engineering. "July 2009." Includes bibliographical references (leaves 108-110).

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Chien, Chih-Ta, and 簡志達. "Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/09878445894553887482.

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碩士
國立中正大學
資訊工程研究所
91
This Thesis proposes an efficient hardware design for the one-dimensional (1-D) discrete Fourier transform (DFT) and its inverse with variable lengths. By combining radix-2/4/8 algorithm, cyclic convolution formulation, sub-expression sharing and Cooly-Tuckey decomposition algorithm together, we have developed a parameterized hardware design for the DFT/IDFT of variable lengths ranging from 64 to 4096 points. Furthermore, we have also implemented a parameterized DSP Intellectual Property (IP) core with proposed design for meeting the system requirements of different system-on-chip (SOC) applications.

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Dissertations / Theses on the topic 'FPGA IP core implementation'

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