Journal articles: 'FPGA IP core implementation'

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Chhetri, Sujit Rokka, Bikash Poudel, Sandesh Ghimire, Shaswot Shresthamali, and Dinesh Kumar Sharma. "Implementation of Audio Effect Generator in FPGA." Nepal Journal of Science and Technology 15, no. 1 (February 3, 2015): 89–98. http://dx.doi.org/10.3126/njst.v15i1.12022.

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This paper describes the theory and implementation of audio effects such as echo, distortion and pitch-shift in Field Programmable Gate Array (FPGA). At first the mathematical formulation for generation of such effects is explained and then the algorithm is described for its implementation in FPGA using Very high speed integrated circuit hardware descriptive language (VHDL). The digital system being designed, which is synthesizable and reconfigurable, offers a great flexibility and scalability in designing and prototyping in FPGAs. The system is divided into three HDL blocks, each for echo, distortion, and pitch-shift effect generation, which are multiplexed in order to share the common ADC and DAC. The audio effect generator designed in this paper was successfully implemented in Spartan-3E FPGA utilizing the resources available effectively. There has been tremendous research being carried out in the field of IP core. Efficient IP cores designed to carry out digital signal processing are implemented in every modern device using configurable logics. This trend hasn’t yet been realized in Nepal. Through the design and implementation of audio effect generator, this paper also aims at bringing the field of IP core development to limelight among scholars of Nepal.DOI: http://dx.doi.org/10.3126/njst.v15i1.12022 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 89-98

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Ma, Cheng, and Ze Long He. "Implementation of FFT Algorithm Based on IP Core." Advanced Materials Research 981 (July 2014): 426–30. http://dx.doi.org/10.4028/www.scientific.net/amr.981.426.

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—In this paper, we propose a new way to implement the FFT Algorithm, which based on FPGA. At first we introduce the theory of FFT algorithm and its applications. Then the features of FFT IP core based on Altera FPGA is discussed. We elaborate the usage method of the customizable Altera FFT MegaCore function. A logic state machine is designed to create some command signals of this FFT IP core. Finally we use simulation tools Signal-Tap in quartus II inviroment to simulate and debug our FFT control module’s function. The result shows that this new control method of FFT IP core is feasible.

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Wang, Bin, Ju Long Lan, Yun Fei Guo, and Yuan Yang Zhang. "Design and Implementation of the Block Cipher-SMS4 IP Core." Advanced Materials Research 129-131 (August 2010): 881–85. http://dx.doi.org/10.4028/www.scientific.net/amr.129-131.881.

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Block ciphers play an essential role in securing the wireless communications. In this paper, an FPGA implementation of the new block cipher SMS4 is presented. The SMS4 Intellectual Property (IP) core includes a non-pipelined encryption/decryption data path with an on-the-fly key scheduler and supports both the Electronic Code Book (ECB) and Cipher Block Chaining (CBC) operation modes. Our result shows that the SMS4 IP core can achieve a high throughput using only a relatively small area. It is well suitable for the field of area restrained condition.

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Tămas, Tibor, and Sándor Tihamér Brassai. "Hardware Implementation of a Neuro-Fuzzy Controller Using High Level Synthesis Tool." MACRo 2015 1, no. 1 (March 1, 2015): 183–91. http://dx.doi.org/10.1515/macro-2015-0018.

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AbstractThe purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.

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Tolba, Mohammed F., Mohammed E. Fouda, Haneen G. Hezayyin, Ahmed H. Madian, and Ahmed G. Radwan. "Memristor FPGA IP Core Implementation for Analog and Digital Applications." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 8 (August 2019): 1381–85. http://dx.doi.org/10.1109/tcsii.2018.2882496.

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Zeng, Gui Gen, and Jiang Zhe Ren. "Design and Implementation of Configurable FFT/IFFT Soft-Core Based on FPGA." Applied Mechanics and Materials 241-244 (December 2012): 2901–9. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2901.

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As a Basic Transforming Operation between Time Field and Frequency Field, FFT Has Been Widely Used in Detection, Telecommunication, Signal Processing, Multimedia Communication Etc. the Implementation of the FFT Algorithms on FPGA Is Always the Hot Research Spots. in Order to Overcome the Shortcomings on the FPGA Resource Reusability Used in FFT Algorithm, this Article Discusses a New Configurable and High Efficient FFT/IFFT Soft-core Solution. the FFT/IFFT Soft-core Adopts Radix-22 Algorithm and Single-Path Delay Feedback (SDF) Pipeline Structure. its Configurable Factors Include: FFT/IFFT, FFT Points (2n, [3,12] ), Fixed-point Bit Width, Clock Delay of Complex Multiplier. the Design Takes FPGA Chip Stratix II EP2S130F780C4 as Hardware Platform, and the Complete Simulation and Synthesis Is Taken. the Maximum Operating Frequency Is up to 306.30MHz. if 300MHz Clock Frequency Used, 4096-point FFT Could Be Realized in 26.73us, and the Consumption of Memory Resources Is only 148Kbit. Compared with Altera FFT IP-core, Our FFT/IFFT Soft-core Has a Little Bit Longer Computing Time (0.6%). however, the LE Resource Consumption Is only 79% of Altera FFT IP-core. Platform, and the Complete Simulation and Synthesis Is Taken. the Maximum Operating Frequency Is up to 306.30MHz. if 300MHz Clock Frequency Used, 4096-point FFT Could Be Realized in 26.73us, and the Consumption of Memory Resources Is only 148Kbit. Compared with Altera FFT IP-core, Our FFT/IFFT Soft-core Has a Little Bit Longer Computing Time (0.6%). however, the LE Resource Consumption Is only 79% of Altera FFT IP-core.

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Xue, Zhao, Liu Quan, and Xiao Fei Wang. "IP Core Based on the Kalman Filter Algorithm in the FPGA Implementation." Advanced Materials Research 694-697 (May 2013): 1093–97. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.1093.

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This article discusses one-dimensional Kalman filter algorithm using FPGA hardware IP core implementation process. First of all, to program the FPGA matrix operations, implementation of double precision floating point. Then the Kalman filter algorithm programmed in MATLAB, to verify the correctness of the algorithm thinking. Finally the MATLAB language programming algorithm is converted into VHDL language. And call 64 a double precision floating point data algorithm realizes the design of 1-D Kalman filtration algorithm IP core, which make the Kalman filter meet the high precision as well as high speed to complete complex algorithm.

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Tang, Xia Qing, Xiang Liu, Jun Qiang Gao, and Bo Lin. "Design and Implementation of FPGA-Based High-Performance Floating Point Arithmetic Unit." Applied Mechanics and Materials 599-601 (August 2014): 1465–69. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.1465.

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Since FPGA processing data, the presence of fixed-point processing accuracy is not high, and IP Core floating point unit and there are some problems in the use of design risk. Based on the improved floating point unit and program optimization algorithm is designed to achieve single-precision floating-point add / subtract, multiply, and divide operations operator. IP Core for floating-point unit design and FPGA development software provides comparative results: both the maximum clock frequency and latency basically unchanged, while the former occupies less hardware resources, to complete a plus / minus, multiply, divide computation time required for the former than the latter were reduced by 46%, 37% and 57%. The program is downloaded to the FPGA chip to get the same results with the simulation results verify the correctness and feasibility of the design.

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Voronov, K. E., K. I. Sukhachev, and D. S. Vorobev. "Development of Control Module Based on a Computing IP-Core." Rocket-space device engineering and information systems 8, no. 1 (2021): 24–38. http://dx.doi.org/10.30894/issn2409-0239.2021.8.1.24.38.

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The article presents the result of the implementation of a synthesized microcontroller in integrated circuits of small FPGAs and a variant of building a control system for an onboard control module based on the developed solution. The possibility of creating a full-fledged microcontroller based on a type 5578TC034 FPGA and more capacious microcontrollers is shown. The description of the structure of the microcontroller, processor core and periphery is given. The processor instruction system is presented. Ip-modules of peripheral devices and some interfaces have been developed. A variant of creating a control system using the developed microcontroller is proposed. In the future, it is planned to increase the functionality of the synthesized microcontroller by optimizing ip-modules and adding new ones. When developing the control system, a domestic component base was used.

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Durai, Sharmila, and Rangarajan Parthasarathy. "Real Time Implementation of QFT-PUF Architecture for Data Secure System-on-Chip." Journal of Computational and Theoretical Nanoscience 14, no. 1 (January 1, 2017): 511–16. http://dx.doi.org/10.1166/jctn.2017.6355.

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System-on-chip (SoC) face major problem due to vulnerability of hack. The hacker target the cryptographic IP block in the architecture of SoC. However, PUF test wrapper provides the security for individual IP core. The individual IP core protection plays major problem in PUF test. We propose a novel method to protect the IP core with QFT-PUF authentication mechanism. QFT-PUF implement in PSOC-FPGA. The mechanism reduces the area and memory in architecture. The proposed method of key generation and their handling process drive from Quantum Fourier Transform. From the validation of QFT-PUF, Fault Acceptance Rate (FAR) increases then the Fault Rejection Rate (FRR).

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LI, Dong, Sheng AO, Jindong TIAN, and Yong TIAN. "Design and implementation of template filtering IP core based on FPGA." Journal of Shenzhen University Science and Engineering 35, no. 6 (2018): 622. http://dx.doi.org/10.3724/sp.j.1249.2018.06622.

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Ma, Xiao Cong, Guang Hui Cai, Hong Chao Sun, and Hong Ye Li. "Design and Implementation of an Encryption/Decryption System Based on FPGA." Advanced Materials Research 1022 (August 2014): 368–71. http://dx.doi.org/10.4028/www.scientific.net/amr.1022.368.

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This paper designs an encryption and decryption system based on the FPGA. The system uses AES algorithm to encrypt and decrypt data. A pipeline IP core is designed with the reconfigurable technology complying with the Avalon bus interface specification. The IP core is applied to be a custom component on Nios II architecture so that the encryption and decryption processes through hardware can be controlled by software. Finally, the program is downloaded to the Altera DE2 development board and completes the testing of encryption and decryption processes. The system can be widely implemented in the field of data security.

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Ren, Ai Feng, Ming Luo, and Fang Ming Hu. "Implementation of W-CDMA System Based on IP Functions." Advanced Materials Research 213 (February 2011): 315–19. http://dx.doi.org/10.4028/www.scientific.net/amr.213.315.

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This paper presents architecture design and field programmable gate array (FPGA) implementation for Wideband Code Division Multiple Access (W-CDMA) transceiver system. Systems that implement the W-CDMA standard must be flexible enough to accommodate changes with the standard, as well as improvements in capacity enhancement techniques such as adaptive antenna and multi-user detection schemes. FPGAs provide this flexibility. Altera high-density, high-performance programmable logic devices (PLDs) combined with intellectual property (IP) functions and the Quartus II development software provide a complete solution for the wireless communications application. The paper describes how to implement a W-CDMA system that conforms to the IMT-2000 standard using Altera FPGAs and IP functions.

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Batmaz, Burak, and Atakan Doğan. "1 Gbit/s UDP/IP Offload Engine IP Core with PCIe Interface." Journal of Circuits, Systems and Computers 27, no. 04 (December 6, 2017): 1850053. http://dx.doi.org/10.1142/s0218126618500536.

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A significant amount of processor power is required to handle packet processing in high speed data networks and taking it to the hardware helps processor to save its energy for other processes. In this study, an Offload Engine IP core that provides the hardware acceleration of UDP/IP protocol stack together with a few other network protocols is introduced. Furthermore, the IP core is equipped with PCI Express (PCIe) interface so as to communicate with applications running on a host PC. Consequently, a processor core deals with only the data processing, while the IP core takes care of the packet processing as per the protocol. The design and implementation of the IP core are verified and tested on an FPGA board; its area utilization and supported features are compared against several competitive designs from the literature. According to these results, the IP core is proved to be a useful one for those network applications that require a hardware-accelerated network protocol stack.

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Fernando, P. R., S. Katkoori, D. Keymeulen, R. Zebulum, and A. Stoica. "Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine." IEEE Transactions on Evolutionary Computation 14, no. 1 (February 2010): 133–49. http://dx.doi.org/10.1109/tevc.2009.2025032.

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Deliparaschos, K. M., G. C. Doyamis, and S. G. Tzafestas. "A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation." International Journal of Electronics 95, no. 11 (November 2008): 1149–66. http://dx.doi.org/10.1080/00207210802387494.

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Shang, Yalei. "Implementation of IP Core of Fast Sine and Cosine Operation through FPGA." Energy Procedia 16 (2012): 1253–58. http://dx.doi.org/10.1016/j.egypro.2012.01.200.

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Naik Dessai, Sanket Suresh. "Design and Implementation of an Ethernet MAC IP Core for Embedded Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 3 (November 1, 2014): 85. http://dx.doi.org/10.11591/ijres.v3.i3.pp85-97.

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An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price.

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Mendon, Ashwin A., Andrew G. Schmidt, and Ron Sass. "A Hardware Filesystem Implementation with Multidisk Support." International Journal of Reconfigurable Computing 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/572860.

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Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which offer the ability to introduce new, innovative functionalities that, previously, were not practical. This article describes one such innovation: a filesystem implemented in hardware. This has the potential of improving the performance of data-intensive applications by connecting secondary storage directly to FPGA compute accelerators. To test the feasibility of this idea, a Hardware Filesystem was designed with four basic operations (open, read, write, and delete). Furthermore, multi-disk and RAID-0 (striping) support has been implemented as an option in the filesystem. A RAM Disk core was created to emulate a SATA disk drive so results on running FPGA systems could be readily measured. By varying the block size from 64 to 4096 bytes, it was found that 1024 bytes gave the best performance while using a very modest 7% of a Xilinx XC4VFX60's slices and only four (of the 232) BRAM blocks available.

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Chen, Baoju, Simin Yu, Ping Chen, Liangshan Xiao, and Jinhu Lü. "Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications." International Journal of Bifurcation and Chaos 30, no. 05 (April 2020): 2050075. http://dx.doi.org/10.1142/s0218127420500753.

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In this paper, a Virtex-7-based video chaotic secure communication scheme is investigated. First, the network sending and receiving controller Intellectual Property (IP) cores are designed. Next, the chaotic encryption and decryption IP cores are implemented using fixed-point algorithm, pipeline operation, and state machine control. Thus, video capturing, video displaying, network sending, network receiving, chaotic encrypting, and chaotic decrypting can be achieved via IP core integration design. An improved 7D chaotic stream cipher algorithm for resisting divide-and-conquer attack is then designed and realized on a Virtex-7 high-end FPGA platform. Hardware experimental results are also given to verify the feasibility of the scheme.

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Yang, Pengfei, Quan Wang, and Jiyang Zhang. "Parallel design and implementation of Error Diffusion Algorithm and IP core for FPGA." Multimedia Tools and Applications 75, no. 8 (March 15, 2015): 4723–33. http://dx.doi.org/10.1007/s11042-015-2499-3.

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Ranjith, C., and S. P. Joy Vasantha Rani. "A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design." Journal of Circuits, Systems and Computers 29, no. 01 (April 4, 2019): 2050014. http://dx.doi.org/10.1142/s0218126620500140.

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Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

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Šušteršič, Tijana, and Aleksandar Peulić. "Implementation of Face Recognition Algorithm on Field Programmable Gate Array (FPGA)." Journal of Circuits, Systems and Computers 28, no. 08 (July 2019): 1950129. http://dx.doi.org/10.1142/s0218126619501299.

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The aim of this study is to implement an algorithm for face recognition, based on fast fourier transform (FFT), on the field programmable gate array (FPGA) chip. Implemented program included the initialization process of two single-IP-core ROM blocks, each with an image of a human face, which are sent to the real components of two-channel IP CoreFFT block. The result of classification could be displayed in the form of either a word “yes” or “no” on the seven-segment display or the information about the reference to the folder with the found match face. Due to the lack of memory on the chip, the results are discussed based on the results obtained by the simulation, whilst the implemented part of the system included displaying images on VGA monitor and result of the algorithm shown on seven-segment display or realized as a software solution in Matlab. The results show 79% accuracy and the advantage of presented system lies in the possibility of working with images in real time. The results obtained in this study can be a good starting point in the implementation of complex algorithms for face recognition using all the benefits that FPGAs offer.

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Zhang, K. B., J. M. Gao, and P. L. Jiang. "High Speed Federated Filter Design and Implementation." Advanced Materials Research 694-697 (May 2013): 2535–39. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2535.

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The theory of federal filter based on the Kalman filter is investigated in the design process, as well as the federal filter information distribution. Considering the advantage of parallel computing structure, the FPGA chip is selected and used to realize the IP core encapsulation and design of Federated Filter. The filtering speed is greatly improved to meet federal filter integrated navigation system. A group simulation experiments are conducted. The results shown that the filtering accuracy and filtering time of federal filter are both improved using the proposed method.

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Prasad Acharya, G., and M. Asha Rani. "FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 57. http://dx.doi.org/10.14419/ijet.v7i2.16.11416.

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The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

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Liu, Chang Hua, Xiao Le Xu, and Guo Dong Ding. "Design and Implementation of Galaxian Game Based on FPGA Architecture." Applied Mechanics and Materials 490-491 (January 2014): 1047–52. http://dx.doi.org/10.4028/www.scientific.net/amm.490-491.1047.

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With the development of computer and network technology, the pace of peoples life is more and more fast. At the same time, the need in the entertainment is also growing. The game based on handheld is becoming more and more popular. It has been booming along with the development of its educational, fun, casual, easy to carry, easy to operate, highly interactive and many other features to meet the people's entertainment needs.This paper introduces the embedded systems based on general-purpose software development model and development process, including the design of hardware platform and software. The design of the hardware platform is the QuartusII10.1, the software platform is Nios II EDS 10.1 and the programming language is C and VHDL. Based on the SPOC Builder tool, we designed the reconfigurable IP cores of the VGA display, LTM touch screen. With Galaxian game as an example, we design a embedded game based on GUI. The results show that the game system is friendly human-computer interaction and quick response and action. This configurable IP core is highly flexibility, variability, plasticity and it can achieve more functional expansion and development in the same resource.

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Kamar, Sara, Abdelmoniem Fouda, Abdelhalim Zekry, and Abdelmoniem Elmahdy. "FPGA implementation of RS codec with interleaver in DVB-T using VHDL." International Journal of Engineering & Technology 6, no. 4 (November 28, 2017): 171. http://dx.doi.org/10.14419/ijet.v6i4.8205.

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Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.This paper presents VHDL program for Reed-Solomoncodec (204, 188) and convolutional interleaver/deinterleaver, used in Digital Video Broadcasting-terrestrial system (DVB-T), according to ETSI EN 300 744 V1.5.1 standard. The VHDL programs are implemented on Xilinx 12.3 ISE and then simulated and tested via ISE simulator then the code is synthesized on FPGA device the results are compared with IP core for Xilinx 12.3 ISE, which gives the same results.

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Kołek, Krzysztof, Andrzej Firlit, Krzysztof Piątek, and Krzysztof Chmielowiec. "Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters." Energies 14, no. 6 (March 12, 2021): 1589. http://dx.doi.org/10.3390/en14061589.

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Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

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Kułaga, Rafał, and Marek Gorgoń. "FPGA Implementation of Decision Trees and Tree Ensembles for Character Recognition in Vivado Hls." Image Processing & Communications 19, no. 2-3 (September 1, 2014): 71–82. http://dx.doi.org/10.1515/ipc-2015-0012.

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Abstract Decision trees and decision tree ensembles are popular machine learning methods, used for classification and regression. In this paper, an FPGA implementation of decision trees and tree ensembles for letter and digit recognition in Vivado High-Level Synthesis is presented. Two publicly available datasets were used at both training and testing stages. Different optimizations for tree code and tree node layout in memory are considered. Classification accuracy, throughput and resource usage for different training algorithms, tree depths and ensemble sizes are discussed. The correctness of the module’s operation was verified using C/RTL cosimulation and on a Zynq-7000 SoC device, using Xillybus IP core for data transfer between the processing system and the programmable logic.

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Li, Qing Qian, and Yong Hui Zhang. "An Optimization Algorithm of Phase Angle Calculation Based on the FPGA Implementation." Applied Mechanics and Materials 513-517 (February 2014): 439–43. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.439.

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An optimization algorithm of phase angle calculation based on FPGA implementation is mainly described in this paper .From two arctangent function calculation algorithms analysis, we combine the strengths of them, and propose a optimized algorithm of phase angle calculation. The theoretical analysis and hardware validation shows that the algorithm has good performances such as high accuracy, good real-time performance, less resource consumption. At the same time, this algorithm can be comprehensive, and can be considered as an IP core to realize the high-speed, parallel calculation of transcendental function.

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Khalifa, Khaled Ben, and Mohamed Hédi Bedoui. "A Massively Parallel Implementation of a Modular Self-Organizing Map on FPGAs." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950054. http://dx.doi.org/10.1142/s0218126619500543.

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This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network’s size and the input data vectors’ dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A [Formula: see text] SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297[Formula: see text]MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one.

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Deng, Yao Hua, Gui Xiong Liu, Wei Han, Zi Wei Fang, Li Ming Wu, and Qing Fu Liao. "Research on Multi-Core Collaborative Computing for FWP Image Processing Algorithm by FPGA." Advanced Materials Research 230-232 (May 2011): 1340–44. http://dx.doi.org/10.4028/www.scientific.net/amr.230-232.1340.

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On the basis of analysis of research on embedded soft hardware collaborative design method, image processing SOPC collaborative design principle is elaborated, relation between complicated algorithm time and soft hardware implementation and the implementation method to accelerate algorithm by multi-processor and multi-core is studied, thus the logical relationship between equipment IP core on the chip with Fast Simplex Link(FSL) bus and bus bridge, connecting conditions and application flow is organized. Finally, design SOPC, for which, multi-core and multi-processor collaborative work with the core of PowerPC 405 processor by taking flexible workpiece path (FWP) image as an example. The test manifests that the computation speed of SOPC designed in this passage is higher 10 times than that of common single-core SOPC in terms of image processing computing, effectively solving the problem of slow speed for computing image preprocessing by software in the embedded system.

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Vidhyapathi, C. M., Alex Noel Joseph Raj, and S. Sundar. "The 3D-DTW Custom IP based FPGA Hardware Acceleration for Action Recognition." Journal of Imaging Science and Technology 65, no. 1 (January 1, 2021): 10401–1. http://dx.doi.org/10.2352/j.imagingsci.technol.2021.65.1.010401.

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Abstract This article proposes an implementation of an action recognition system, which allows the user to perform operations in real time. The Microsoft Kinect (RGB-D) sensor plays a central role in this system, which provides the skeletal joint information of humans directly. Computationally efficient skeletal joint position features are considered for describing each action. The dynamic time warping algorithm (DTW) is a widely used algorithm in many applications such as similarity sequence search, classification, and speech recognition. It provides the highest accuracy compared to all other algorithms. However, the computational time of the DTW algorithm is a major drawback in real world applications. To speed up the basic DTW algorithm, a novel three-dimensional dynamic time warping (3D-DTW) classification algorithm is proposed in this work. The proposed 3D-DTW algorithm is implemented in both software and field programmable gate array (FPGA) hardware modeling techniques. The performance of the 3D-DTW algorithm is evaluated for 12 actions in which each action is described with the feature vector size of 576 over 32 frames. From our software modeling results, it has been shown that the proposed algorithm performs the action classification accurately. However, the computation time of the 3D-DTW algorithm increases linearly when we increase either the number of actions or the feature vector size of each action. For further speedup, an efficient custom 3D-DTW intellectual property (IP) core is developed using the Xilinx Vivado high-level synthesis (HLS) tool to accelerate the 3D-DTW algorithm in FPGA hardware. The CPU centric software modeling of the 3D-DTW algorithm is compared with its hardware accelerated custom IP core. It has been shown that the developed 3D-DTW Custom IP core computation time is 40 times faster than its software counterpart. As the hardware results are promising, a parallel hardware software co-design architecture is proposed for the Xilinx Zynq-7020 System on Chip (SoC) FPGA for action recognition. The HLS simulation and synthesis results are provided to support the practical implementation of the proposed architecture. Our proposed approach outperforms many of the existing state-of-the-art DTW based action recognition techniques by providing the highest accuracy of 97.77%.

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Qiong, Yan Guo, and Zhou Mao Hua. "Implementation of QC-LDPC Decoder Based on FPGA for FSO System." Applied Mechanics and Materials 668-669 (October 2014): 1269–72. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.1269.

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QC-LDPC can bring a higher coding gain to the FSO system, but the complexity of the decoding algorithm restricted its application in high-speed FSO system.In this paper, it adopts an improved Modified Min-sum Algorithm (MMSA) to reduce the decoding complexity and save decoding time. In this paper, the author programs the decoder with VHDL Hardware Description Language and analyzes the static time of the design with Synplify Pro and QuartusII to verify the correctness. Moreover, each functional unit is downloaded to the EP3C16Q240C8 chip produced by ALTERA Company and encapsulated into the IP core. Finally, we used MATLAB software to build the FSO system for testing decoder performance. The results show that the QC-LDPC decoder based on FPGA has higher reliability in FSO system.

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Yu, Qun Xiu, Shou Ming Zhang, Chao Wang, and Li Zhi Xie. "Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking." Applied Mechanics and Materials 734 (February 2015): 621–24. http://dx.doi.org/10.4028/www.scientific.net/amm.734.621.

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In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.

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Hsieh, Chin Fa, and Tsung Han Tsai. "FPGA Implementation of a High-Speed Two Dimensional Discrete Wavelet Transform." Applied Mechanics and Materials 479-480 (December 2013): 508–12. http://dx.doi.org/10.4028/www.scientific.net/amm.479-480.508.

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This paper proposes high-speed VLSI architecture for implementing a forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme is used to increase the clock rate, which allows its critical path to take only one adder delay. The proposed design enables 100% hardware use and faster computing than other 2D DWT architecture. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array (FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.

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Ma, De, Kai Huang, Si Wen Xiu, Xiao Lang Yan, Jiong Feng, Jian Lin Zeng, and Hai Tong Ge. "An Automatic SoC Design Methodology for Integration and Verification." Advanced Materials Research 383-390 (November 2011): 2222–30. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.2222.

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The increasing complexity of current SoC design brings a great challenge to SoC designer for fast SoC RTL integration and effective verification. In this paper, an automatic SoC integration methodology based on IP-XACT standard is proposed as a complete and effective solution for low-level RTL simulation, FPGA emulation and ASIC implementation. A bottom-up approach is adopted for design integration and verification from component level, to SoC core level, and then to final chip level. The three-core MPSoC case study not only gives the detailed usage and analysis on the proposed methodology, but also shows its efficiency to integrate a complex SoC design and its feasibility for correct SoC implementation.

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Siva Kumar, M., B. Murali Krishna, N. Sai Tejeswi, Sanath Kumar Tulasi, N. Srinivasulu, and K. Hari Kishore. "FPGA implementation of tunable arbitrary sequencer for key generation mechanism." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 237. http://dx.doi.org/10.14419/ijet.v7i1.5.9154.

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In the present scenario information security has become a predominant issue. Cryptography is the process used for the purpose of information security. In cryptography message is encrypted with key produces cipher and decrypts the original message from cipher uses variety mechanisms and permutations. This paper presents a key generation mechanism suitable in cryptography applications which plays a vital role in data security. Random key generation techniques are multiplexed and configured in FPGA. In run time based on priority of section inputs randomly one method selectively produces a key which inputs to cryptosystem. Jitter process generates random numbers based on clock frequency triggered to oscillators, which produces pseudo random keys, but it consumes more resources when compared with other methods, but randomness in generated key is exponential. Pre stored random numbers in Block Memory are generated using IP core generator. The main advantage of the proposed model is to produce random keys which will be secure, predictable and attains high security. Due to its configurable nature, FPGA’s are suitable for wide variety of applications which can configure in runtime to implement custom designs and needs. Random number generation techniques are designed using Verilog HDL, simulated on Xilinx ISE simulator and implemented on Spartan FPGA.

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Meoni, Gabriele, Gianluca Giuffrida, and Luca Fanucci. "A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders." Information 10, no. 4 (April 24, 2019): 151. http://dx.doi.org/10.3390/info10040151.

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During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder.

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Valente, Giacomo, Vittoriano Muttillo, Mirco Muttillo, Gianluca Barile, Alfiero Leoni, Walter Tiberti, and Luigi Pomante. "SPOF—Slave Powerlink on FPGA for Smart Sensors and Actuators Interfacing for Industry 4.0 Applications." Energies 12, no. 9 (April 29, 2019): 1633. http://dx.doi.org/10.3390/en12091633.

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We here present a new PLC-POWERLINK industrial solution for Industry 4.0 applications. The proposed solution provides the capability to separate the sensing functionality from the PLC-side, in demand for the reconfigurable FPGA implementation. In particular, we here provide a framework that supports the interfacing between the POWERLINK protocol and commonly used standards, such as I2C, SPI, and UART. This has been obtained by using a framework built around a soft IP-core Application Processor, which manages the interfacing with several POWERLINK slaves, able to support the data exchange with the POWERLINK Communication Processor. A practical application example and related implementation details are presented in the paper.

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Shashidhara, K. S., and H. C. Srinivasaiah. "Hardware co-simulation of 1024-point FFT and it's Implementation, in Simulink, Xilinx Vivado IDE on Zynq-7000 FPGA." European Journal of Engineering Research and Science 4, no. 9 (September 15, 2019): 58–64. http://dx.doi.org/10.24018/ejers.2019.4.9.1501.

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In this paper a 1024-point FFT Algorithm is implemented on Zynq-7000 FPGA device. The design implementation uses Hardware co-simulation in Simulink and Xilinx Vivado environments with Zynq-7000 FPGA target evaluation board using JTAG setup. The power parameter for the configured FFT IP core for 1024 point and the signal source DDS block are estimated. The DDS with both sine and cosine signal outputs enabled, consume a power of 0.277 W, whereas, the 1024 point FFT core consume a power of 0.044 W. Further when 2 DDSs were instanced to generate orthogonal sine and cosine sources for OFDM signals of same frequency 1MHz each, a total of 0.277W power is consumed. When a single DDS core is configured for both sine or cosine signal only configuration by instancing a 1024-point FFT core the total power consumed is 0.268W and 0.267W, respectively, a 1mW higher to cosine case. Further, when 1024 point FFT core power alone is calculated it is found to be 0.044W (or 44mW). When a single DDS is instanced for OFDM signal generation by opting both the sine cosine signals, it consumed a total power of 0.233 W saving a power of 0.044W or 44mW by sine or cosine data re-use from the LUT ROM of DDS. Thus saving a power of 44mW by using data re-use through LUT’s of DDS. This is a significant power saving. In this, hardware co-simulation process, Xilinx system generator tool (Sysgen) is used. This implementation is coded using Verilog HDL, verified on Xilinx Vivado platform on the Zynq-7000 FPGA device. Note that Zynq-7000 is supporting hardware co-simulation, hence the 1024-point FFT has been implemented on this device. The simulation results are captured on Xilinx signal viewer for a proper conclusion.

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Fayçal, Radjah, Ziet Lahcene, and Benoudjit Nabil. "ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 2 (May 1, 2021): 818. http://dx.doi.org/10.11591/ijeecs.v22.i2.pp818-825.

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This paper presents an FPGA image segmentation-binarization system based on Iterative Self Organizing DATA (ISODATA) threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chip. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPC-builder or QSYS for the integration of NIOS-system, and NIOS-II-STB-ECLIPSE for the software program with eclipse c++ langage.

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TUNCER, Adem, and Mehmet YILDIRIM. "Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 24 (2016): 5055–67. http://dx.doi.org/10.3906/elk-1502-122.

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Cui, Linhai, Yusen Qin, Fanyang Kong, and Kaihong Yu. "Design of a Regular Expression Matching System Based on Network on Chip." Open Electrical & Electronic Engineering Journal 7, no. 1 (June 14, 2013): 46–50. http://dx.doi.org/10.2174/1874129001307010046.

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This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

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Li, Xiao Jun, and Lin Li. "IP Core Based Hardware Implementation of Multi-Layer Perceptrons on FPGAs: A Parallel Approach." Advanced Materials Research 433-440 (January 2012): 5647–53. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5647.

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There’re many models derived from the famous bio-inspired artificial neural network (ANN). Among them, multi-layer perceptron (MLP) is widely used as a universal function approximator. With the development of EDA and recent research work, we are able to use rapid and convenient method to generate hardware implementation of MLP on FPGAs through pre-designed IP cores. In the mean time, we focus on achieving the inherent parallelism of neural networks. In this paper, we firstly propose the hardware architecture of modular IP cores. Then, a parallel MLP is devised as an example. At last, some conclusions are made.

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Dourvas, Nikolaos, Michail-Antisthenis Tsompanas, Georgios Ch Sirakoulis, and Philippos Tsalides. "Hardware Acceleration of Cellular Automata Physarum polycephalum Model." Parallel Processing Letters 25, no. 01 (March 2015): 1540006. http://dx.doi.org/10.1142/s012962641540006x.

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During the past decades, computer science experts were inspired from the study of biological organisms. Moreover, bio-inspired algorithms were produced that many times can give excellent solutions with low computational cost in complex engineering problems. In our case, the plasmodium of Physarum polycephalum is capable of finding the shortest path solution between two points in a labyrinth. In this study, we implement a Cellular Automata (CA) model in hardware, which attempts to describe and, moreover, mimic the behavior of the plasmodium in a maze. Beyond the successful implementation of the CA-based Physarum model in software, in order to take full advantage of the inherent parallelism of CA, we focus on a Field Programmable Gate Array (FPGA) implementation of the proposed model. Namely, two different implementations were considered here. Their difference is on the desired precision produced by the numerical representation of CA model parameters. Based on the corresponding results of the shortest path in the labyrinth,the modeling efficiency of both approaches was compared depending on the resulting error propagation. The presented FPGA implementations succeed to take advantage of the CA's inherit parallelism and improve the performance of the CA algorithm when compared with software in terms of computational speed and power consumption. As a result, the implementations presented here, can also be considered as a preliminary CA-based Physarum polycephalum IP core which produces a biological inspired solution to the shortest-path problem.

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Huda Ja’afar, Noor, and Afandi Ahmad. "Pipeline architectures of Three-dimensional daubechies wavelet transform using hybrid method." Indonesian Journal of Electrical Engineering and Computer Science 15, no. 1 (July 1, 2019): 240. http://dx.doi.org/10.11591/ijeecs.v15.i1.pp240-246.

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The application of three-dimensional (3-D) medical image compression systems uses several building blocks for its computationally intensive algorithms to perform matrix transformation operations. Complexity in addressing large medical volumes data has resulted in vast challenges from a hardware implementation perspective. This paper presents an approach towards very-large-scale-integration (VLSI) implementation of 3-D Daubechies wavelet transform for medical image compression. Discrete wavelet transform (DWT) algorithm is used to design the proposed architectures with pipelined direct mapping technique. Hybrid method use a combination of hardware description language (HDL) and G-code, where this method provides an advantage compared to traditional method. The proposed pipelined architectures are deployed for adaptive transformation process of medical image compression applications. The soft IP core design was targeted on to Xilinx field programmable gate array (FPGA) single board RIO (sbRIO 9632). Results obtained for 3-D DWT architecture using Daubechies 4-tap (Daub4) implementation exhibits promising results in terms of area, power consumption and maximum frequency compared to Daubechies 6-tap (Daub6).

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OUERHANI, YOUSRI, MAHER JRIDI, and AYMAN ALFALOU. "AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE." Journal of Circuits, Systems and Computers 21, no. 06 (October 2012): 1240018. http://dx.doi.org/10.1142/s021812661240018x.

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In this paper we present a novel architecture for FFT implementation on FPGA. The proposed architecture based on radix-4 algorithm presents the advantage of a higher throughput and low area-delay product. In fact, the novelty consists on using a memory sharing and dividing technique along with parallel-in parallel-out Processing Elements (PE). The proposed architecture can perform N-point FFT using only 4/3N delay elements and involves a latency of N/4 cycles. Comparison in terms of hardware complexity and area-delay product with recent works presented in the literature and commercial IPs has been made to show the efficiency of the proposed design. Moreover, from the experimental results obtained from a FPGA prototype we find that the proposed design involves an execution time of 56% lower than that obtained with Xilinx IP core and an increase of 19% in the throughput by area ratio for 256-point FFT.

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Hu, Haibing, Wenxi Yao, and Zhengyu Lu. "Design and Implementation of Three-Level Space Vector PWM IP Core for FPGAs." IEEE Transactions on Power Electronics 22, no. 6 (November 2007): 2234–44. http://dx.doi.org/10.1109/tpel.2007.909296.

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He, Lifang, Gaimin Jin, and Sang-Bing Tsai. "Design and Implementation of Embedded Real-Time English Speech Recognition System Based on Big Data Analysis." Mathematical Problems in Engineering 2021 (September 1, 2021): 1–12. http://dx.doi.org/10.1155/2021/6561730.

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This article uses Field Programmable Gate Array (FPGA) as a carrier and uses IP core to form a System on Programmable Chip (SOPC) English speech recognition system. The SOPC system uses a modular hardware system design method. Except for the independent development of the hardware acceleration module and its control module, the other modules are implemented by software or IP provided by Xilinx development tools. Hardware acceleration IP adopts a top-down design method, provides parallel operation of multiple operation components, and uses pipeline technology, which speeds up data operation, so that only one operation cycle is required to obtain an operation result. In terms of recognition algorithm, a more effective training algorithm is proposed, Genetic Continuous Hidden Markov Model (GA_CHMM), which uses genetic algorithm to directly train CHMM model. It is to find the optimal model by encoding the parameter values of the CHMM and performing operations such as selection, crossover, and mutation according to the fitness function. The optimal parameter value after decoding corresponds to the CHMM model, and then the English speech recognition is performed through the CHMM algorithm. This algorithm can save a lot of training time, thereby improving the recognition rate and speed. This paper studies the optimization of embedded system software. By studying the fixed-point software algorithm and the optimization of system storage space, the real-time response speed of the system has been reduced from about 10 seconds to an average of 220 milliseconds. Through the optimization of the CHMM algorithm, the real-time performance of the system is improved again, and the average time to complete the recognition is significantly shortened. At the same time, the system can achieve a recognition rate of over 90% when the English speech vocabulary is less than 200.

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Journal articles on the topic 'FPGA IP core implementation'

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