Relevant bibliographies by topics / FPGA resources

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'FPGA resources'

Author: Grafiati
Published: 30 May 2022
Last updated: 31 July 2025

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Journal articles on the topic "FPGA resources"

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Xie, Weikun, Wenjing Qi, Xiaohui Lin, and Houjun Wang. "Research on an Intelligent Test Method for Interconnect Resources in an FPGA." Applied Sciences 13, no. 13 (2023): 7951. http://dx.doi.org/10.3390/app13137951.

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With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article u
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., Akriti. "The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 17–20. http://dx.doi.org/10.22214/ijraset.2024.58572.

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Abstract: This research investigates challenges in employing the Distributed Arithmetic (DA) algorithm for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). Focusing on coefficient representation, it explores precision trade-offs via fixed-point arithmetic and quantization. Memory optimization strategies, such as efficient storage within FPGA resources, are analysed to reduce memory requirements. Enhancing computational speed involves optimizing lookup table access and architectural modifications. Efficient management of FPGA resources and trade-offs between late
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Caffarena, Gabriel, Juan A. López, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz. "Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/703267.

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We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefits of a wise use of embedded FPGA resourc
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Dwivedi, Akshya. ""Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4483–88. http://dx.doi.org/10.22214/ijraset.2024.62485.

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Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resou
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Siddiqui, Abdullah Farhan, and Prof B. Rajendra Naik. "Implementation of FPGA-based Accelerator for Convolutional Neural Networks." April-May 2024, no. 43 (April 1, 2024): 10–16. http://dx.doi.org/10.55529/ijrise.43.10.16.

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This research paper presents a novel FPGA-based accelerator tailored for Convolutional Neural Networks (CNNs), specifically implemented on the Virtex-7 evaluation kit. By harnessing the inherent parallel processing capabilities of FPGAs, the architecture of the accelerator is meticulously crafted using Verilog. The FPGA implementation demonstrates a resource-efficient design, making use of 588 Look-Up Tables (LUTs) and 353 Flip Flops. Notably, the efficient utilization of these resources signifies a careful balance between computational efficiency and the available FPGA resources. This researc
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Guo, Shuaizhi, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, and Xi Jin. "RP-Ring: A Heterogeneous Multi-FPGA Accelerator." International Journal of Reconfigurable Computing 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6784319.

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To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical mode
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Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.

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The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). T
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Gazziro, Mario, Jecel Mattos de Assumpção Junior, Oswaldo Hideo Ando Junior, Marco Roberto Cavallari, and João Paulo Carmo. "Design and Evaluation of Open-Source Soft-Core Processors." Electronics 13, no. 4 (2024): 781. http://dx.doi.org/10.3390/electronics13040781.

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The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small “soft-core” processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is
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Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (2000): 219–35. http://dx.doi.org/10.1155/2000/12198.

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In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Increm
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Ullah, Anees, Ali Zahir, Noaman A. Khan, Waleed Ahmad, Alexis Ramos, and Pedro Reviriego. "BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs." Electronics 9, no. 2 (2020): 353. http://dx.doi.org/10.3390/electronics9020353.

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Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simul
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Dissertations / Theses on the topic "FPGA resources"

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Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191286.

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Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfig
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Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-231445.

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The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concep
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Iordache, Ancuta. "Performance-cost trade-offs in heterogeneous clouds." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S045/document.

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Les infrastructures de cloud fournissent une grande variété de ressources de calcul à la demande avec différents compromis coût-performance. Cela donne aux utilisateurs des nombreuses opportunités pour exécuter leurs applications ayant des besoins complexes en ressources, à partir d’un grand nombre de serveurs avec des interconnexions à faible latence jusqu’à des dispositifs spécialisés comme des GPUs et des FPGAs. Les besoins des utilisateurs concernant l’exécution de leurs applications peuvent varier entre une exécution la plus rapide possible, la plus chère ou un compromis entre les deux. C
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Hassan, Mohamed Nabil. "Low resource scalable elliptic curve cryptography on FPGA." Thesis, University of Sheffield, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.522417.

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Lam, Andrew H. "An analytical model of logic resource utilization for FPGA architecture development." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/19753.

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Designers constantly strive to improve Field-Programmable Gate Array (FPGA) performance through innovative architecture design. To evaluate performance, an understanding of the effects of modifying logic blocks structures and routing fabrics on performance is needed. Current architectures are evaluated via computer-aided design (CAD) simulations that are labourious and computationally-expensive experiments to perform. A more scientific method, based on understanding the relationships between architectural parameters and performance will enable the rapid evaluation of new architectures, even befo
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Hinnerson, Martin. "A Resource Efficient, HighSpeed FPGA Implementation of Lossless Image Compression for 3D Vision." Thesis, Linköpings universitet, Datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-165300.

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High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless comp
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Thangella, Praneeth Kumar, and Aravind Reddy Gundla. "Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16547.

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<p>AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.</p>
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Tolmie, Donald Francois. "Design of a low-resource 2D graphics engine for FPGAs." Master's thesis, Faculty of Engineering and the Built Environment, 2018. http://hdl.handle.net/11427/30042.

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This study focused on the design and implementation of a low-resource graphics engine, MicroGE, which can be implemented on an FPGA. MicroGE uses a minimal amount of FPGA resources when compared to other graphics engines. After researching existing graphics engines, it was discovered that most make use of a memory space to store frame buffer data. Because of the restrictions that were imposed on the design of MicroGE, it could not incorporate a large enough memory space to store a frame buffer. It was specified that MicroGE should be able to fit on low-resource FPGAs, without any external memo
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Yao, Jia Stroud Charles E. "Built-In self-test of global routing resources in Virtex-4 FPGAs." Auburn, Ala., 2009. http://hdl.handle.net/10415/1723.

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Simons, Taylor Scott. "High-Speed Image Classification for Resource-Limited Systems Using Binary Values." BYU ScholarsArchive, 2021. https://scholarsarchive.byu.edu/etd/9097.

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Image classification is a memory- and compute-intensive task. It is difficult to implement high-speed image classification algorithms on resource-limited systems like FPGAs and embedded computers. Most image classification algorithms require many fixed- and/or floating-point operations and values. In this work, we explore the use of binary values to reduce the memory and compute requirements of image classification algorithms. Our objective was to implement these algorithms on resource-limited systems while maintaining comparable accuracy and high speeds. By implementing high-speed image class
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Books on the topic "FPGA resources"

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Massey, Doreen E., and Gill Lenderyou. Sex Education Factpack (FPA Education & Training Resources). 2nd ed. Family Planning Association, 1993.

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(Illustrator), Geraldine Sponce, and Sean MacGarry (Illustrator), eds. Primary School Workbook (FPA Education & Training Resources). Family Planning Association, 1993.

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Masrani, Divyang K. Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low. 2006.

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Masrani, Divyang K. Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low. 2006.

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BUILT-IN SELF-TEST OF GLOBAL ROUTING RESOURCES IN FPGAS. LAP LAMBERT ACADEMIC PUBL, 2011.

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Hilgurt, S. Ya, and O. A. Chemerys. Reconfigurable signature-based information security tools of computer systems. PH “Akademperiodyka”, 2022. http://dx.doi.org/10.15407/akademperiodyka.458.297.

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The book is devoted to the research and development of methods for combining computational structures for reconfigurable signature-based information protection tools for computer systems and networks in order to increase their efficiency. Network security tools based, among others, on such AI-based approaches as deep neural networking, despite the great progress shown in recent years, still suffer from nonzero recognition error probability. Even a low probability of such an error in a critical infrastructure can be disastrous. Therefore, signature-based recognition methods with their theoretic
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Book chapters on the topic "FPGA resources"

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Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela Blott, and Christian Plessl. "Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-69766-1_9.

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AbstractMost FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization of their network capabilities is often challenging and error-prone because the whole network stack and communication patterns have to be implemented and managed on the FPGAs. Also, this approach conceptually involves a trade-off between the performance potential of improved communication and the impact of resource consumption for communication infrastructure, since the utilized resources on the FPGAs could oth
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León-Javier, Alejandro, Marco A. Moreno-Armendáriz, and Nareli Cruz-Cortés. "Designing a Compact Genetic Algorithm with Minimal FPGA Resources." In Advances in Intelligent and Soft Computing. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03156-4_35.

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Siozios, Kostas, Dimitrios Soudris, and Antonios Thanailakis. "Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_39.

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Galimberti, Andrea. "FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM." In Special Topics in Information Technology. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-51500-2_3.

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AbstractPost-quantum cryptography aims to design cryptosystems that can be deployed on traditional computers and resist attacks from quantum computers, which are widely expected to break the currently deployed public-key cryptography solutions in the upcoming decades. Providing effective hardware support is crucial to ensuring a wide adoption of post-quantum cryptography solutions, and it is one of the requirements set by the USA’s National Institute of Standards and Technology within its ongoing standardization process. This research delivers a configurable FPGA-based hardware architecture to
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Sugier, Jarosław. "Improving FPGA Implementations of BLAKE and BLAKE2 Algorithms with Memory Resources." In Advances in Dependability Engineering of Complex Systems. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59415-6_38.

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Simpson, Philip. "Resource Scoping." In FPGA Design. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_4.

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Simpson, Philip Andrew. "Resource Scoping." In FPGA Design. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_5.

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Sugier, Jarosław. "Dedicated FPGA Resources in Improving Power Efficiency of Implementations of BLAKE3 Hash Function." In System Dependability - Theory and Applications. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-61857-4_28.

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Wires, Kent E., Michael J. Schulte, and Don McCarley. "FPGA Resource Reduction Through Truncated Multiplication." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_59.

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Fröning, Holger, Federico Silla, and Hector Montaner. "MEMSCALE: Re-architecting Memory Resources for Clusters." In High-Performance Computing Using FPGAs. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-1791-0_19.

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Conference papers on the topic "FPGA resources"

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Chen, Wenwei, Xinyu He, Tongshu Ding, Jian Wang, and Jinmei Lai. "Exhaustive Application-Dependent Testing for FPGA Interconnect Resources." In 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2024. https://doi.org/10.1109/icsict62049.2024.10831626.

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Pizarro, Kevin, Miguel Andrade, and Ioannis Vourkas. "Trading Parallelism for Resources in the FPGA Implementation of Cellular Automata-Based Models." In 2023 18th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA). IEEE, 2023. http://dx.doi.org/10.1109/cnna60945.2023.10652706.

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Jang, S., J. Jung, J. H. Jung, Y. Choi, I. Lee, and Y. Choi. "Development of Multi-Chain Tapped-delay Line Based TDC Using Down Sampling Method for Minimizing FPGA Resources." In 2024 IEEE Nuclear Science Symposium (NSS), Medical Imaging Conference (MIC) and Room Temperature Semiconductor Detector Conference (RTSD). IEEE, 2024. http://dx.doi.org/10.1109/nss/mic/rtsd57108.2024.10656012.

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Cieszewski, Radoslaw, Ryszard Romaniuk, Krzysztof Poźniak, and Maciej Linczuk. "FPGA matrix multiplication with resource optimization and constraints." In Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2024, edited by Ryszard S. Romaniuk, Andrzej Smolarz, and Waldemar Wójcik. SPIE, 2024. https://doi.org/10.1117/12.3052256.

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Bragança, Lucas, Jeronimo Penha, Michael Canesche, Dener Ribeiro, José Augusto M. Nacif, and Ricardo Ferreira. "An Open-Source Cloud-FPGA Gene Regulatory Accelerator." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2021. http://dx.doi.org/10.5753/wscad.2021.18527.

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FPGAs are suitable to speed up gene regulatory network (GRN) algorithms with high throughput and energy efficiency. In addition, virtualizing FPGA using hardware generators and cloud resources increases the computing ability to achieve on-demand accelerations across multiple users. Recently, Amazon AWS provides high-performance Cloud's FPGAs. This work proposes an open source accelerator generator for Boolean gene regulatory networks. The generator automatically creates all hardware and software pieces from a high-level GRN description. We evaluate the accelerator performance and cost for CPU,
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Gardel, Alfredo, Ignacio Bravo, Jose L. Lazaro, Beatriz Perez, Javier Balinas, and Alvaro Hernandez. "Verification of FPGA internal resources." In 2009 IEEE International Symposium on Intelligent Signal Processing - (WISP 2009). IEEE, 2009. http://dx.doi.org/10.1109/wisp.2009.5286572.

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Guerra, Victor S., and Gabriel L. Nazar. "A Partition-Aware VNF Placement Methodology for FPGA-Equipped NFVIs." In Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos. Sociedade Brasileira de Computação, 2024. http://dx.doi.org/10.5753/sbrc.2024.1545.

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In the context of Network Function Virtualization (NFV), Field Programmable Gate Arrays (FPGAs) can be used to reduce bottlenecks introduced by the substitution of dedicated hardware middleboxes by virtualized implementations. The problem of placing Virtualized Network Functions (VNFs) on FPGA-equipped NFV infrastructures, however, imposes additional challenges that require an accurate modeling of the FPGA fabric. More specifically, simultaneous sharing of the FPGA requires careful partitioning of its resources into fixed regions that can be dynamically reconfigure and to which functions can b
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Veedu, B. M., A. Azam, and M. A. Soderstrand. "FPGA resources for simple heterodyne filter." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.987710.

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Mayer-Lindenberg, Fritz. "High-Level FPGA Programming through Mapping Process Networks to FPGA Resources." In 2009 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE, 2009. http://dx.doi.org/10.1109/reconfig.2009.73.

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Alves, Gabriel Sá B., Anfranserai M. Dias, and Victor T. Sarinho. "Development of A Sprite-Based Architecture for Creating 2D Games in Reconfigurable Environments Using Fpga Devices." In Anais Estendidos do Simpósio Brasileiro de Jogos e Entretenimento Digital. Sociedade Brasileira de Computação, 2022. http://dx.doi.org/10.5753/sbgames_estendido.2022.225306.

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The understanding of concepts worked on FPGAs combined with the creation of games in hardware platforms has helped in the understanding and assimilation of the necessary techniques and approaches to build digital game systems. This work presents the development and validation of a Sprite-Based Architecture that aims to develop 2D games in reconfigurable environments based on FPGA devices. To this end, a set of functions and other resources implemented in C language were develop, that aims to help the creation of games through the developed architecture.
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Reports on the topic "FPGA resources"

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Selvakkumaran, Navaratnasothie, Abhishek Ranjan, Salil Raje, and George Karypis. Scalable Partitioning Algorithms for FPGAs With Heterogeneous Resources. Defense Technical Information Center, 2004. http://dx.doi.org/10.21236/ada439474.

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You might also be interested in the extended bibliographies on the topic 'FPGA resources' for particular source types:
Journal articles Dissertations / Theses
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