Relevant bibliographies by topics / FPGA resources

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'FPGA resources'

Author: Grafiati
Published: 30 May 2022
Last updated: 19 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'FPGA resources.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "FPGA resources"

1

Xie, Weikun, Wenjing Qi, Xiaohui Lin, and Houjun Wang. "Research on an Intelligent Test Method for Interconnect Resources in an FPGA." Applied Sciences 13, no. 13 (2023): 7951. http://dx.doi.org/10.3390/app13137951.

Full text
Abstract:
With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.
APA, Harvard, Vancouver, ISO, and other styles
2

., Akriti. "The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 17–20. http://dx.doi.org/10.22214/ijraset.2024.58572.

Full text
Abstract:
Abstract: This research investigates challenges in employing the Distributed Arithmetic (DA) algorithm for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). Focusing on coefficient representation, it explores precision trade-offs via fixed-point arithmetic and quantization. Memory optimization strategies, such as efficient storage within FPGA resources, are analysed to reduce memory requirements. Enhancing computational speed involves optimizing lookup table access and architectural modifications. Efficient management of FPGA resources and trade-offs between latency, throughput, and resource usage are also explored. Algorithmic refinements specific to DA-based FIR filters are studied to enhance resource utilization and computational efficiency. Overall, this work offers insights and solutions spanning algorithm design, memory utilization, lookup table speed, and FPGA architecture for more efficient DA-based FIR filter implementations on FPGAs.
APA, Harvard, Vancouver, ISO, and other styles
3

Caffarena, Gabriel, Juan A. López, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz. "Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/703267.

Full text
Abstract:
We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%.
APA, Harvard, Vancouver, ISO, and other styles
4

Dwivedi, Akshya. ""Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4483–88. http://dx.doi.org/10.22214/ijraset.2024.62485.

Full text
Abstract:
Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resources effectively, balancing latency, throughput, and resource use. It looks at specific improvements to the DA method for FIR filters to make better use of resources and enhance performance. Overall, this work provides insights and solutions for algorithm design, memory use, lookup table speed, and FPGA architecture to make DA-based FIR filter implementations on FPGAs more efficient.
APA, Harvard, Vancouver, ISO, and other styles
5

Siddiqui, Abdullah Farhan, and Prof B. Rajendra Naik. "Implementation of FPGA-based Accelerator for Convolutional Neural Networks." April-May 2024, no. 43 (April 1, 2024): 10–16. http://dx.doi.org/10.55529/ijrise.43.10.16.

Full text
Abstract:
This research paper presents a novel FPGA-based accelerator tailored for Convolutional Neural Networks (CNNs), specifically implemented on the Virtex-7 evaluation kit. By harnessing the inherent parallel processing capabilities of FPGAs, the architecture of the accelerator is meticulously crafted using Verilog. The FPGA implementation demonstrates a resource-efficient design, making use of 588 Look-Up Tables (LUTs) and 353 Flip Flops. Notably, the efficient utilization of these resources signifies a careful balance between computational efficiency and the available FPGA resources. This research significantly contributes to the field of hardware acceleration for CNNs by offering an optimized solution for high-performance deep learning applications. The presented architecture serves as a promising foundation for future advancements in FPGA-based accelerators, providing valuable insights for researchers and engineers working in the domain of hardware optimization for Convolutional Neural Networks.
APA, Harvard, Vancouver, ISO, and other styles
6

Guo, Shuaizhi, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, and Xi Jin. "RP-Ring: A Heterogeneous Multi-FPGA Accelerator." International Journal of Reconfigurable Computing 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6784319.

Full text
Abstract:
To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.
APA, Harvard, Vancouver, ISO, and other styles
7

Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.

Full text
Abstract:
The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.
APA, Harvard, Vancouver, ISO, and other styles
8

Gazziro, Mario, Jecel Mattos de Assumpção Junior, Oswaldo Hideo Ando Junior, Marco Roberto Cavallari, and João Paulo Carmo. "Design and Evaluation of Open-Source Soft-Core Processors." Electronics 13, no. 4 (2024): 781. http://dx.doi.org/10.3390/electronics13040781.

Full text
Abstract:
The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small “soft-core” processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources, including program size for 8-bit applications. The number of instructions is not large, but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2 mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.
APA, Harvard, Vancouver, ISO, and other styles
9

Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (2000): 219–35. http://dx.doi.org/10.1155/2000/12198.

Full text
Abstract:
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g., Actel's ES6500 FPGA family).
APA, Harvard, Vancouver, ISO, and other styles
10

Ullah, Anees, Ali Zahir, Noaman A. Khan, Waleed Ahmad, Alexis Ramos, and Pedro Reviriego. "BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs." Electronics 9, no. 2 (2020): 353. http://dx.doi.org/10.3390/electronics9020353.

Full text
Abstract:
Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "FPGA resources"

1

Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191286.

Full text
Abstract:
Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.
APA, Harvard, Vancouver, ISO, and other styles
2

Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-231445.

Full text
Abstract:
The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is required<br>Das Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt
APA, Harvard, Vancouver, ISO, and other styles
3

Iordache, Ancuta. "Performance-cost trade-offs in heterogeneous clouds." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S045/document.

Full text
Abstract:
Les infrastructures de cloud fournissent une grande variété de ressources de calcul à la demande avec différents compromis coût-performance. Cela donne aux utilisateurs des nombreuses opportunités pour exécuter leurs applications ayant des besoins complexes en ressources, à partir d’un grand nombre de serveurs avec des interconnexions à faible latence jusqu’à des dispositifs spécialisés comme des GPUs et des FPGAs. Les besoins des utilisateurs concernant l’exécution de leurs applications peuvent varier entre une exécution la plus rapide possible, la plus chère ou un compromis entre les deux. Cependant, le choix du nombre et du type des ressources à utiliser pour obtenir le compromis coût-performance que les utilisateurs exigent constitue un défi majeur. Cette thèse propose trois contributions avec l’objectif de fournir des bons compromis coût-performance pour l’exécution des applications sur des plates-formes hétérogènes. Elles suivent deux directions : un bon usage des ressources et un bon choix des ressources. Nous proposons comme première contribution une méthode de partage pour des accélérateurs de type FPGA dans l’objectif de maximiser leur utilisation. Dans une seconde contribution, nous proposons des méthodes de profilage pour la modélisation de la demande en ressources des applications. Enfin, nous démontrons comment ces technologies peuvent être intégrées dans une plate-forme de cloud hétérogène<br>Cloud infrastructures provide on-demand access to a large variety of computing devices with different performance and cost. This creates many opportunities for cloud users to run applications having complex resource requirements, starting from large numbers of servers with low-latency interconnects, to specialized devices such as GPUs and FPGAs. User expectations regarding the execution of applications may vary between the fastest possible execution, the cheapest execution or any trade-off between the two extremes. However, enabling cloud users to easily make performance-cost trade-offs is not a trivial exercise and choosing the right amount and type of resources to run applications accordingto user expectations is very difficult. This thesis proposes three contributions to enable performance-cost trade-offs for application execution in heterogeneous clouds by following two directions: make good use of resources and make good choice of resources. We propose as a first contribution a method to share FPGA-based accelerators in cloud infrastructures having the objective to improve their utilization. As a second contribution we propose profiling methods to automate the selection of heterogeneous resources for executing applications under user objectives. Finally, we demonstrate how these technologies can be implemented and exploited in heterogeneous cloud platforms
APA, Harvard, Vancouver, ISO, and other styles
4

Hassan, Mohamed Nabil. "Low resource scalable elliptic curve cryptography on FPGA." Thesis, University of Sheffield, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.522417.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Lam, Andrew H. "An analytical model of logic resource utilization for FPGA architecture development." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/19753.

Full text
Abstract:
Designers constantly strive to improve Field-Programmable Gate Array (FPGA) performance through innovative architecture design. To evaluate performance, an understanding of the effects of modifying logic blocks structures and routing fabrics on performance is needed. Current architectures are evaluated via computer-aided design (CAD) simulations that are labourious and computationally-expensive experiments to perform. A more scientific method, based on understanding the relationships between architectural parameters and performance will enable the rapid evaluation of new architectures, even before the development of a CAD tool. This thesis presents an analytical model that describes such relationships and is based principally on Rent’s Rule. Specifically, it relates logic architectural parameters to the area efficiency of an FPGA. Comparison to experimental results show that our model is accurate. This accuracy combined with the simple form of the model’s equations make it a powerful tool for FPGA architects to better understand and guide the development of future FPGA architectures.
APA, Harvard, Vancouver, ISO, and other styles
6

Hinnerson, Martin. "A Resource Efficient, HighSpeed FPGA Implementation of Lossless Image Compression for 3D Vision." Thesis, Linköpings universitet, Datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-165300.

Full text
Abstract:
High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless compression algorithms and the implementation operate at 214.3 MHz with a max throughput of 3.43 Gbit/s. The compression ratio is compared to that of competing implementations from Teledyne DALSA Inc. and Pleora Technologies on a set of typical 3D range data images. The proposed algorithm achieve a higher compression ratio while maintaining a small hardware footprint.
APA, Harvard, Vancouver, ISO, and other styles
7

Thangella, Praneeth Kumar, and Aravind Reddy Gundla. "Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16547.

Full text
Abstract:
<p>AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.</p>
APA, Harvard, Vancouver, ISO, and other styles
8

Tolmie, Donald Francois. "Design of a low-resource 2D graphics engine for FPGAs." Master's thesis, Faculty of Engineering and the Built Environment, 2018. http://hdl.handle.net/11427/30042.

Full text
Abstract:
This study focused on the design and implementation of a low-resource graphics engine, MicroGE, which can be implemented on an FPGA. MicroGE uses a minimal amount of FPGA resources when compared to other graphics engines. After researching existing graphics engines, it was discovered that most make use of a memory space to store frame buffer data. Because of the restrictions that were imposed on the design of MicroGE, it could not incorporate a large enough memory space to store a frame buffer. It was specified that MicroGE should be able to fit on low-resource FPGAs, without any external memory components. Also, MicroGE should be able to fit on modern, high-resource, FPGAs without using a significant amount of those FPGAs’ resources. These goals were achieved by designing MicroGE according to an architecture which differs from the ones of existing graphics engines. MicroGE only renders parts of the video frame, which can be stored in a small memory space, before those parts are transmitted to an HDMI or DVI monitor. After the design was completed, MicroGE, along with other components, was implemented in a VHDL design. Hardware was developed, which contained a Spartan-6 LX25 FPGA, to verify this VHDL. Other verification methods, including the use of VHDL test benches, were also used to verify the VHDL design. A software library, MGAPI, was developed on an Arduino Due microcontroller board. This software library allowed the Arduino Due to display graphics on an HDMI monitor via MicroGE. The Arduino Due was able to update the display of 1000 graphics primitives within 111 ms. The internal FPGA RAM resource usage of MicroGE, 792 kb, was found to be significantly lower than the amount of memory required for a frame buffer. Even though these results were satisfactory, there are still many improvements that can be made to MicroGE. These improvements include increasing the number of rendering capabilities, optimisation of power usage, and increasing the control and video output interfaces.
APA, Harvard, Vancouver, ISO, and other styles
9

Yao, Jia Stroud Charles E. "Built-In self-test of global routing resources in Virtex-4 FPGAs." Auburn, Ala., 2009. http://hdl.handle.net/10415/1723.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Simons, Taylor Scott. "High-Speed Image Classification for Resource-Limited Systems Using Binary Values." BYU ScholarsArchive, 2021. https://scholarsarchive.byu.edu/etd/9097.

Full text
Abstract:
Image classification is a memory- and compute-intensive task. It is difficult to implement high-speed image classification algorithms on resource-limited systems like FPGAs and embedded computers. Most image classification algorithms require many fixed- and/or floating-point operations and values. In this work, we explore the use of binary values to reduce the memory and compute requirements of image classification algorithms. Our objective was to implement these algorithms on resource-limited systems while maintaining comparable accuracy and high speeds. By implementing high-speed image classification algorithms on resource-limited systems like embedded computers, FPGAs, and ASICs, automated visual inspection can be performed on small low-powered systems. Industries like manufacturing, medicine, and agriculture can benefit from compact, high-speed, low-power visual inspection systems. Tasks like defect detection in manufactured products and quality sorting of harvested produce can be performed cheaper and more quickly. In this work, we present ECO Jet Features, an algorithm adapted to use binary values for visual inspection. The ECO Jet Features algorithm ran 3.7x faster than the original ECO Features algorithm on embedded computers. It also allowed the algorithm to be implemented on an FPGA, achieving 78x speedup over full-sized desktop systems, using a fraction of the power and space. We reviewed Binarized Neural Nets (BNNs), neural networks that use binary values for weights and activations. These networks are particularly well suited for FPGA implementation and we compared and contrasted various FPGA implementations found throughout the literature. Finally, we combined the deep learning methods used in BNNs with the efficiency of Jet Features to make Neural Jet Features. Neural Jet Features are binarized convolutional layers that are learned through deep learning and learn classic computer vision kernels like the Gaussian and Sobel kernels. These kernels are efficiently computed as a group and their outputs can be reused when forming output channels. They performed just as well as BNN convolutions on visual inspection tasks and are more stable when trained on small models.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "FPGA resources"

1

Massey, Doreen E., and Gill Lenderyou. Sex Education Factpack (FPA Education & Training Resources). 2nd ed. Family Planning Association, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

(Illustrator), Geraldine Sponce, and Sean MacGarry (Illustrator), eds. Primary School Workbook (FPA Education & Training Resources). Family Planning Association, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Masrani, Divyang K. Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low. 2006.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Masrani, Divyang K. Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low. 2006.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

BUILT-IN SELF-TEST OF GLOBAL ROUTING RESOURCES IN FPGAS. LAP LAMBERT ACADEMIC PUBL, 2011.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Hilgurt, S. Ya, and O. A. Chemerys. Reconfigurable signature-based information security tools of computer systems. PH “Akademperiodyka”, 2022. http://dx.doi.org/10.15407/akademperiodyka.458.297.

Full text
Abstract:
The book is devoted to the research and development of methods for combining computational structures for reconfigurable signature-based information protection tools for computer systems and networks in order to increase their efficiency. Network security tools based, among others, on such AI-based approaches as deep neural networking, despite the great progress shown in recent years, still suffer from nonzero recognition error probability. Even a low probability of such an error in a critical infrastructure can be disastrous. Therefore, signature-based recognition methods with their theoretically exact matching feature are still relevant when creating information security systems such as network intrusion detection systems, antivirus, anti-spam, and wormcontainment systems. The real time multi-pattern string matching task has been a major performance bottleneck in such systems. To speed up the recognition process, developers use a reconfigurable hardware platform based on FPGA devices. Such platform provides almost software flexibility and near-ASIC performance. The most important component of a signature-based information security system in terms of efficiency is the recognition module, in which the multipattern matching task is directly solved. It must not only check each byte of input data at speeds of tens and hundreds of gigabits/sec against hundreds of thousand or even millions patterns of signature database, but also change its structure every time a new signature appears or the operating conditions of the protected system change. As a result of the analysis of numerous examples of the development of reconfigurable information security systems, three most promising approaches to the construction of hardware circuits of recognition modules were identified, namely, content-addressable memory based on digital comparators, Bloom filter and Aho–Corasick finite automata. A method for fast quantification of components of recognition module and the entire system was proposed. The method makes it possible to exclude resource-intensive procedures for synthesizing digital circuits on FPGAs when building complex reconfigurable information security systems and their components. To improve the efficiency of the systems under study, structural-level combinational methods are proposed, which allow combining into single recognition device several matching schemes built on different approaches and their modifications, in such a way that their advantages are enhanced and disadvantages are eliminated. In order to achieve the maximum efficiency of combining methods, optimization methods are used. The methods of: parallel combining, sequential cascading and vertical junction have been formulated and investigated. The principle of multi-level combining of combining methods is also considered and researched. Algorithms for the implementation of the proposed combining methods have been developed. Software has been created that allows to conduct experiments with the developed methods and tools. Quantitative estimates are obtained for increasing the efficiency of constructing recognition modules as a result of using combination methods. The issue of optimization of reconfigurable devices presented in hardware description languages is considered. A modification of the method of affine transformations, which allows parallelizing such cycles that cannot be optimized by other methods, was presented. In order to facilitate the practical application of the developed methods and tools, a web service using high-performance computer technologies of grid and cloud computing was considered. The proposed methods to increase efficiency of matching procedure can also be used to solve important problems in other fields of science as data mining, analysis of DNA molecules, etc. Keywords: information security, signature, multi-pattern matching, FPGA, structural combining, efficiency, optimization, hardware description language.
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "FPGA resources"

1

Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela Blott, and Christian Plessl. "Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-69766-1_9.

Full text
Abstract:
AbstractMost FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization of their network capabilities is often challenging and error-prone because the whole network stack and communication patterns have to be implemented and managed on the FPGAs. Also, this approach conceptually involves a trade-off between the performance potential of improved communication and the impact of resource consumption for communication infrastructure, since the utilized resources on the FPGAs could otherwise be used for computations. In this work, we investigate this trade-off, firstly, by using synthetic benchmarks to evaluate the different configuration options of the communication framework ACCL and their impact on communication latency and throughput. Finally, we use our findings to implement a shallow water simulation whose scalability heavily depends on low-latency communication. With a suitable configuration of ACCL, good scaling behavior can be shown to all 48 FPGAs installed in the system. Overall, the results show that the availability of inter-FPGA communication frameworks as well as the configurability of framework and network stack are crucial to achieve the best application performance with low latency communication.
APA, Harvard, Vancouver, ISO, and other styles
2

León-Javier, Alejandro, Marco A. Moreno-Armendáriz, and Nareli Cruz-Cortés. "Designing a Compact Genetic Algorithm with Minimal FPGA Resources." In Advances in Intelligent and Soft Computing. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03156-4_35.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Siozios, Kostas, Dimitrios Soudris, and Antonios Thanailakis. "Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_39.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Galimberti, Andrea. "FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM." In Special Topics in Information Technology. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-51500-2_3.

Full text
Abstract:
AbstractPost-quantum cryptography aims to design cryptosystems that can be deployed on traditional computers and resist attacks from quantum computers, which are widely expected to break the currently deployed public-key cryptography solutions in the upcoming decades. Providing effective hardware support is crucial to ensuring a wide adoption of post-quantum cryptography solutions, and it is one of the requirements set by the USA’s National Institute of Standards and Technology within its ongoing standardization process. This research delivers a configurable FPGA-based hardware architecture to support BIKE, a post-quantum QC-MDPC code-based key encapsulation mechanism. The proposed architecture is configurable through a set of architectural and code parameters, which make it efficient, providing good performance while using the resources available on FPGAs effectively, flexible, allowing to support different large QC-MDPC codes defined by the designers of the cryptosystem, and scalable, targeting the whole Xilinx Artix-7 FPGA family. Two separate modules target the cryptographic functionality of the client and server nodes of the quantum-resistant key exchange, respectively, and a complexity-based heuristic that leverages the knowledge of the time and space complexity of the configurable hardware components steers the design space exploration to identify their best parameterization. The proposed architecture outperforms the state-of-the-art reference software that exploits the Intel AVX2 extension and runs on a desktop-class CPU by 1.77 and 1.98 times, respectively, for AES-128- and AES-192-equivalent security instances of BIKE, and it provides a speedup of more than six times compared to the fastest reference state-of-the-art hardware architecture, which targets the same FPGA family.
APA, Harvard, Vancouver, ISO, and other styles
5

Sugier, Jarosław. "Improving FPGA Implementations of BLAKE and BLAKE2 Algorithms with Memory Resources." In Advances in Dependability Engineering of Complex Systems. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59415-6_38.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Simpson, Philip. "Resource Scoping." In FPGA Design. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Simpson, Philip Andrew. "Resource Scoping." In FPGA Design. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Sugier, Jarosław. "Dedicated FPGA Resources in Improving Power Efficiency of Implementations of BLAKE3 Hash Function." In System Dependability - Theory and Applications. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-61857-4_28.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Wires, Kent E., Michael J. Schulte, and Don McCarley. "FPGA Resource Reduction Through Truncated Multiplication." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_59.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Fröning, Holger, Federico Silla, and Hector Montaner. "MEMSCALE: Re-architecting Memory Resources for Clusters." In High-Performance Computing Using FPGAs. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-1791-0_19.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "FPGA resources"

1

Chen, Wenwei, Xinyu He, Tongshu Ding, Jian Wang, and Jinmei Lai. "Exhaustive Application-Dependent Testing for FPGA Interconnect Resources." In 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2024. https://doi.org/10.1109/icsict62049.2024.10831626.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Pizarro, Kevin, Miguel Andrade, and Ioannis Vourkas. "Trading Parallelism for Resources in the FPGA Implementation of Cellular Automata-Based Models." In 2023 18th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA). IEEE, 2023. http://dx.doi.org/10.1109/cnna60945.2023.10652706.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Jang, S., J. Jung, J. H. Jung, Y. Choi, I. Lee, and Y. Choi. "Development of Multi-Chain Tapped-delay Line Based TDC Using Down Sampling Method for Minimizing FPGA Resources." In 2024 IEEE Nuclear Science Symposium (NSS), Medical Imaging Conference (MIC) and Room Temperature Semiconductor Detector Conference (RTSD). IEEE, 2024. http://dx.doi.org/10.1109/nss/mic/rtsd57108.2024.10656012.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Cieszewski, Radoslaw, Ryszard Romaniuk, Krzysztof Poźniak, and Maciej Linczuk. "FPGA matrix multiplication with resource optimization and constraints." In Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2024, edited by Ryszard S. Romaniuk, Andrzej Smolarz, and Waldemar Wójcik. SPIE, 2024. https://doi.org/10.1117/12.3052256.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Bragança, Lucas, Jeronimo Penha, Michael Canesche, Dener Ribeiro, José Augusto M. Nacif, and Ricardo Ferreira. "An Open-Source Cloud-FPGA Gene Regulatory Accelerator." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2021. http://dx.doi.org/10.5753/wscad.2021.18527.

Full text
Abstract:
FPGAs are suitable to speed up gene regulatory network (GRN) algorithms with high throughput and energy efficiency. In addition, virtualizing FPGA using hardware generators and cloud resources increases the computing ability to achieve on-demand accelerations across multiple users. Recently, Amazon AWS provides high-performance Cloud's FPGAs. This work proposes an open source accelerator generator for Boolean gene regulatory networks. The generator automatically creates all hardware and software pieces from a high-level GRN description. We evaluate the accelerator performance and cost for CPU, GPU, and Cloud FPGA implementations by considering six GRN models proposed in the literature. As a result, the FPGA accelerator is at least 12x faster than the best GPU accelerator. Furthermore, the FPGA reaches the best performance per dollar in cloud services, at least 5x better than the best GPU accelerator.
APA, Harvard, Vancouver, ISO, and other styles
6

Gardel, Alfredo, Ignacio Bravo, Jose L. Lazaro, Beatriz Perez, Javier Balinas, and Alvaro Hernandez. "Verification of FPGA internal resources." In 2009 IEEE International Symposium on Intelligent Signal Processing - (WISP 2009). IEEE, 2009. http://dx.doi.org/10.1109/wisp.2009.5286572.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Guerra, Victor S., and Gabriel L. Nazar. "A Partition-Aware VNF Placement Methodology for FPGA-Equipped NFVIs." In Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos. Sociedade Brasileira de Computação, 2024. http://dx.doi.org/10.5753/sbrc.2024.1545.

Full text
Abstract:
In the context of Network Function Virtualization (NFV), Field Programmable Gate Arrays (FPGAs) can be used to reduce bottlenecks introduced by the substitution of dedicated hardware middleboxes by virtualized implementations. The problem of placing Virtualized Network Functions (VNFs) on FPGA-equipped NFV infrastructures, however, imposes additional challenges that require an accurate modeling of the FPGA fabric. More specifically, simultaneous sharing of the FPGA requires careful partitioning of its resources into fixed regions that can be dynamically reconfigure and to which functions can be mapped. In this work, we will demonstrate that accurate modeling of the FPGA partitions into the placement solution is crucial to achieve solutions that are guaranteed to be viable. Experimental results obtained through two Integer Liner Programming models will be used to demonstrate that partition awareness can avoid invalid solutions caused by overestimation of the device capabilities, with a small impact on the number of allocated user requisitions.
APA, Harvard, Vancouver, ISO, and other styles
8

Veedu, B. M., A. Azam, and M. A. Soderstrand. "FPGA resources for simple heterodyne filter." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.987710.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Mayer-Lindenberg, Fritz. "High-Level FPGA Programming through Mapping Process Networks to FPGA Resources." In 2009 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE, 2009. http://dx.doi.org/10.1109/reconfig.2009.73.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Alves, Gabriel Sá B., Anfranserai M. Dias, and Victor T. Sarinho. "Development of A Sprite-Based Architecture for Creating 2D Games in Reconfigurable Environments Using Fpga Devices." In Anais Estendidos do Simpósio Brasileiro de Jogos e Entretenimento Digital. Sociedade Brasileira de Computação, 2022. http://dx.doi.org/10.5753/sbgames_estendido.2022.225306.

Full text
Abstract:
The understanding of concepts worked on FPGAs combined with the creation of games in hardware platforms has helped in the understanding and assimilation of the necessary techniques and approaches to build digital game systems. This work presents the development and validation of a Sprite-Based Architecture that aims to develop 2D games in reconfigurable environments based on FPGA devices. To this end, a set of functions and other resources implemented in C language were develop, that aims to help the creation of games through the developed architecture.
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "FPGA resources"

1

Selvakkumaran, Navaratnasothie, Abhishek Ranjan, Salil Raje, and George Karypis. Scalable Partitioning Algorithms for FPGAs With Heterogeneous Resources. Defense Technical Information Center, 2004. http://dx.doi.org/10.21236/ada439474.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'FPGA resources' for particular source types:
Journal articles Dissertations / Theses
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography