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Journal articles on the topic 'FPGA resources'

Author: Grafiati

Published: 30 May 2022

Last updated: 31 July 2025

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1

Xie, Weikun, Wenjing Qi, Xiaohui Lin, and Houjun Wang. "Research on an Intelligent Test Method for Interconnect Resources in an FPGA." Applied Sciences 13, no. 13 (2023): 7951. http://dx.doi.org/10.3390/app13137951.

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With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article u

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., Akriti. "The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 17–20. http://dx.doi.org/10.22214/ijraset.2024.58572.

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Abstract: This research investigates challenges in employing the Distributed Arithmetic (DA) algorithm for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). Focusing on coefficient representation, it explores precision trade-offs via fixed-point arithmetic and quantization. Memory optimization strategies, such as efficient storage within FPGA resources, are analysed to reduce memory requirements. Enhancing computational speed involves optimizing lookup table access and architectural modifications. Efficient management of FPGA resources and trade-offs between late

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Caffarena, Gabriel, Juan A. López, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz. "Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/703267.

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We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefits of a wise use of embedded FPGA resourc

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Dwivedi, Akshya. ""Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4483–88. http://dx.doi.org/10.22214/ijraset.2024.62485.

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Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resou

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Siddiqui, Abdullah Farhan, and Prof B. Rajendra Naik. "Implementation of FPGA-based Accelerator for Convolutional Neural Networks." April-May 2024, no. 43 (April 1, 2024): 10–16. http://dx.doi.org/10.55529/ijrise.43.10.16.

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This research paper presents a novel FPGA-based accelerator tailored for Convolutional Neural Networks (CNNs), specifically implemented on the Virtex-7 evaluation kit. By harnessing the inherent parallel processing capabilities of FPGAs, the architecture of the accelerator is meticulously crafted using Verilog. The FPGA implementation demonstrates a resource-efficient design, making use of 588 Look-Up Tables (LUTs) and 353 Flip Flops. Notably, the efficient utilization of these resources signifies a careful balance between computational efficiency and the available FPGA resources. This researc

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Guo, Shuaizhi, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, and Xi Jin. "RP-Ring: A Heterogeneous Multi-FPGA Accelerator." International Journal of Reconfigurable Computing 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6784319.

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To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical mode

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Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.

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The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). T

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Gazziro, Mario, Jecel Mattos de Assumpção Junior, Oswaldo Hideo Ando Junior, Marco Roberto Cavallari, and João Paulo Carmo. "Design and Evaluation of Open-Source Soft-Core Processors." Electronics 13, no. 4 (2024): 781. http://dx.doi.org/10.3390/electronics13040781.

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The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small “soft-core” processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is

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Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (2000): 219–35. http://dx.doi.org/10.1155/2000/12198.

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In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Increm

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Ullah, Anees, Ali Zahir, Noaman A. Khan, Waleed Ahmad, Alexis Ramos, and Pedro Reviriego. "BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs." Electronics 9, no. 2 (2020): 353. http://dx.doi.org/10.3390/electronics9020353.

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Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simul

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Cho, Mannhee, and Youngmin Kim. "FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit." Electronics 10, no. 22 (2021): 2859. http://dx.doi.org/10.3390/electronics10222859.

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Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing high-performance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accel

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Pathan, Aneela, Khalil M. Zohaib, Rizwan Aziz, Adil Hussain Chandio, and Syed Haseeb Shah. "An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier." Mehran University Research Journal of Engineering and Technology 44, no. 2 (2025): 136–43. https://doi.org/10.22581/muet1982.3220.

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Information is deteriorated by communication channels in several ways. The most notable is the addition of noise to the signal during transmission. Noise is reduced by the use of adaptive filters. Wiener, Steepest, and LMS are the most often utilized. While in hardware translation on ASICS and FPGAs, adaptive filters require more resources than straightforward FIR or IIR designs. Reducing resources is necessary to optimize the implementation. The literature on resource-optimized filter implementation with multiplier optimization has been seen with a number of approaches. In this study, a new p

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Alonso, Tobias, Lucian Petrica, Mario Ruiz, et al. "Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (2022): 1–34. http://dx.doi.org/10.1145/3470567.

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Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN

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Kiefer, Martin, Ilias Poulakis, Eleni Tzirita Zacharatou, and Volker Markl. "Optimistic Data Parallelism for FPGA-Accelerated Sketching." Proceedings of the VLDB Endowment 16, no. 5 (2023): 1113–25. http://dx.doi.org/10.14778/3579075.3579085.

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Sketches are a popular approximation technique for large datasets and high-velocity data streams. While custom FPGA-based hardware has shown admirable throughput at sketching, the state-of-the-art exploits data parallelism by fully replicating resources and constructing independent summaries for every parallel input value. We consider this approach pessimistic, as it guarantees constant processing rates by provisioning resources for the worst case. We propose a novel optimistic sketching architecture for FPGAs that partitions a single sketch into multiple independent banks shared among all inp

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Choi, Seonghyun, and Woojoo Lee. "Developing a Grover's quantum algorithm emulator on standalone FPGAs: optimization and implementation." AIMS Mathematics 9, no. 11 (2024): 30939–71. http://dx.doi.org/10.3934/math.20241493.

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<p>Quantum computing (QC) leverages superposition, entanglement, and parallelism to solve complex problems that are challenging for classical computing methods. The immense potential of QC has spurred explosive interest and research in both academia and industry. However, the practicality of QC based on large-scale quantum computers remains limited by issues of scalability and error correction. To bridge this gap, QC emulators utilizing classical computing resources have emerged, with modern implementations employing FPGAs for efficiency. Nevertheless, FPGA-based QC emulators face signif

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Wang, Gui Tang, Rui Huang Wang, Feng Wang, and Wen Juan Liu. "An Implementation and Improvement of Fast Two-Dimensional Median Filtering." Applied Mechanics and Materials 55-57 (May 2011): 95–100. http://dx.doi.org/10.4028/www.scientific.net/amm.55-57.95.

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This paper discussed a conventional fast median filtering algorithm for FPGA implementation. An improved way -- Quasi-median filtering algorithm -- have been proposed to reduce the occupancy rate of FPGA resources on the premise of ensuring the result of median filtering. Through the detailed analysis and comparison of results of simulation and experiments, conclusions can be drawn that such improvements can achieve better filtering results, and can reduce FPGA resource utilization. It offers some value for the application of design which requires more FPGA resources.

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Pérez, Ignacio, and Miguel Figueroa. "A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems." Sensors 21, no. 8 (2021): 2637. http://dx.doi.org/10.3390/s21082637.

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Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application

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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA reso

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Sauvage, Laurent, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, and Yves Mathieu. "Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/375245.

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FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential

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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 89–96. https://doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have b

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Tufa, Guta Tesema, Fitsum Assamnew Andargie, and Anchit Bijalwan. "Acceleration of Deep Neural Network Training Using Field Programmable Gate Arrays." Computational Intelligence and Neuroscience 2022 (October 17, 2022): 1–11. http://dx.doi.org/10.1155/2022/8387364.

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Convolutional neural network (CNN) training often necessitates a considerable amount of computational resources. In recent years, several studies have proposed for CNN inference and training accelerators in which the FPGAs have previously demonstrated good performance and energy efficiency. To speed up the processing, CNN requires additional computational resources such as memory bandwidth, a FPGA platform resource usage, time, power consumption, and large datasets for training. They are constrained by the requirement for improved hardware acceleration to support scalability beyond existing da

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Sobas, Justin, and François Marc. "Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA." Micromachines 15, no. 1 (2023): 19. http://dx.doi.org/10.3390/mi15010019.

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Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding

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Brunella, Marco Spaziani, Giacomo Belocchi, Marco Bonola, et al. "hXDP." Communications of the ACM 65, no. 8 (2022): 92–100. http://dx.doi.org/10.1145/3543668.

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The network interface cards (NICs) of modern computers are changing to adapt to faster data rates and to help with the scaling issues of general-purpose CPU technologies. Among the ongoing innovations, the inclusion of programmable accelerators on the NIC's data path is particularly interesting, since it provides the opportunity to offload some of the CPU's network packet processing tasks to the accelerator. Given the strict latency constraints of packet processing tasks, accelerators are often implemented leveraging platforms such as Field-Programmable Gate Arrays (FPGAs). FPGAs can be re-pro

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Gao, Hongxu, Zeyu Li, Lirong Zhou, Xiang Li, and Quan Wang. "GLRM: Geometric Layout-Based Resource Management Method on Multiple Field Programmable Gate Array Systems." Electronics 13, no. 10 (2024): 1821. http://dx.doi.org/10.3390/electronics13101821.

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Multiple field programmable gate array (Multi-FPGA) systems are capable of forming larger and more powerful computing units through high-speed interconnections between chips and are beginning to be widely used by various computing service providers. However, the new computing architecture brings new challenges to the system’s task resource management. Existing resource management methods do not fully exploit resources in Multi-FPGA systems, and it is difficult to support fast resource request and release. In this regard, we propose a geometric layout-based resource management (GLRM) method for

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Schelten, Niklas, Fritjof Steinert, Justin Knapheide, Anton Schulte, and Benno Stabernack. "A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application." ACM Transactions on Reconfigurable Technology and Systems 16, no. 1 (2022): 1–23. http://dx.doi.org/10.1145/3543176.

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The use of application-specific accelerators in data centers has been the state of the art for at least a decade, starting with the availability of General Purpose GPUs achieving higher performance either overall or per watt. In most cases, these accelerators are coupled via PCIe interfaces to the corresponding hosts, which leads to disadvantages in interoperability, scalability and power consumption. As a viable alternative to PCIe-attached FPGA accelerators this paper proposes standalone FPGAs as Network-attached Accelerators (NAAs) . To enable reliable communication for decoupled FPGAs we p

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Gehrer, Stefan, and Georg Sigl. "Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs." Journal of Circuits, Systems and Computers 25, no. 01 (2015): 1640002. http://dx.doi.org/10.1142/s0218126616400028.

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Physically unclonable functions (PUFs) are an innovative way to generate device unique keys using uncontrollable production tolerances. In this work, we present a method to use PUFs on modern FPGA-based system-on-chips (SoCs). The processor system part of the SoC is used to configure the FPGA part. We propose a reconfigurable PUF design that can be changed by using the partial reconfiguration (PR) feature of modern FPGAs. Multiple ring oscillator PUF (RO PUF) designs are loaded on the same logic blocks of the FPGA in order to make use of different resources, i.e., sources of entropy, on the FP

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Qasim, Aseel. "Efficient Multi-Carrier Communication Systems: A Performance Evaluation of Parallel and Sequential Data Processing Models." Journal of Internet Services and Information Security 15, no. 1 (2025): 67–78. https://doi.org/10.58346/jisis.2025.i1.005.

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Orthogonal frequency division multiplexing (OFDM) is a popular method for multi-carrier transmission today. Nonetheless, one disadvantage of OFDM is its large peak-to-average power ratio (PAPR) which decreases the efficiency of power amplifiers. Orthogonal Wavelet Division Multiplexing (OWDM) offers an alternative to Orthogonal Frequency Division Multiplexing (OFDM). While OFDM utilizes the Inverse Fast Fourier Transform (IFFT), OWDM employs the Inverse Discrete Wavelet Transform (IDWT). Previous studies have shown that the Bit Error Rate (BER) for both OWDM and OFDM is nearly identical; howev

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Kyriakos, Angelos, Elissaios-Alexios Papatheofanous, Charalampos Bezaitis, and Dionysios Reisis. "Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification." Journal of Imaging 8, no. 4 (2022): 114. http://dx.doi.org/10.3390/jimaging8040114.

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A plethora of image and video-related applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable applications include the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) that detect objects in image frames. Aiming at contributing to the CNN accelerator solutions, the current paper focuses on the design of Field-Programmable Gate Arrays (FPGAs) for CNNs of limited feature space to improve performance, power consumption and resource utilization. The proposed design approach targets the design

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Rawski, Mariusz. "Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs." International Journal of Electronics and Telecommunications 56, no. 4 (2010): 345–50. http://dx.doi.org/10.2478/v10177-010-0045-9.

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Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAsDistributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture explor

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Tounsi, Mohamed, Ali Jafer Mahdi, Mahmood Anees Ahmed, et al. "Hardware Implementation of a Deep Learning-based Autonomous System for Smart Homes using Field Programmable Gate Array Technology." Engineering, Technology & Applied Science Research 14, no. 5 (2024): 17203–8. http://dx.doi.org/10.48084/etasr.8372.

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The current study uses Field-Programmable Gate Array (FPGA) hardware to advance smart home technology through a self-learning system. The proposed intelligent three-hidden layer system outperformed prior systems with 99.21% accuracy using real-world data from the MavPad dataset. The research shows that FPGA solutions can do difficult computations in seconds. The study also examines the difficulties of maximizing performance with limited resources when incorporating deep learning technologies into FPGAs. Despite these challenges, the research shows that FPGA-based solutions improve home technol

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Skhiri, Rym, Virginie Fresse, Jean Paul Jamont, Benoit Suffran, and Jihene Malek. "From FPGA to Support Cloud to Cloud of FPGA: State of the Art." International Journal of Reconfigurable Computing 2019 (December 5, 2019): 1–17. http://dx.doi.org/10.1155/2019/8085461.

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Field Programmable Gate Array (FPGA) draws a significant attention from both industry and academia by accelerating computationally expensive applications and achieving low power consumption. FPGAs are interesting due to the flexibility and reconfigurabiltiy of their device. Cloud computing becomes a major trend towards infrastructure and computing resources dematerialization. It provides “unlimited” storage capacities and a large number of data and applications that make collaboration easier between multiple (not domain specific) designers. Many papers in the literature have surveyed Cloud and

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Перепелицын, Артём Евгеньевич. "МЕТОД РАЗРАБОТКИ МУЛЬТИПАРАМЕТРИЗИРУЕМЫХ ПРОЕКТОВ ПРОГРАММИРУЕМОЙ ЛОГИКИ". Aerospace technic and technology, № 2 (26 квітня 2018): 64–70. http://dx.doi.org/10.32620/aktt.2018.2.09.

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A classification of project flexibility ways provided in VHDL language is proposed. The results of the analysis of the dependence of the FPGA resources required for the implementation of arithmetic blocks are presented. The peculiarities of implementation of FPGA arithmetic operations with a fixed point are analyzed. The analytical ratios of the of logical elements number for the Altera FPGA from the input data width of the arithmetic blocks are given. The results of an experimental study of the dependence of required FPGA resources amount for parametrizable arithmetic blocks implementation ar

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Dandekar, Omkar, William Plishker, Shuvra S. Bhattacharyya, and Raj Shekhar. "Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration." International Journal of Reconfigurable Computing 2008 (2008): 1–17. http://dx.doi.org/10.1155/2008/738174.

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In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such as field-programmable gate arrays (FPGAs). For adaptive utilization of resources at run time, FPGAs with capabilities for dynamic reconfiguration are emerging. In this context, it is useful for designers to derive sets of efficient configurations that trade off application performance with fabric resources. Such sets can be maintained at run time so that the best available design tradeoff is used. Fi

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Irfan, Muhammad, Zahid Ullah, and Ray C. C. Cheung. "Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs." Electronics 8, no. 5 (2019): 584. http://dx.doi.org/10.3390/electronics8050584.

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Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in findin

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Jang, Seojin, Wei Liu, Sangun Park, and Yongbeom Cho. "Automatic RTL Generation Tool of FPGAs for DNNs." Electronics 11, no. 3 (2022): 402. http://dx.doi.org/10.3390/electronics11030402.

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With the increasing use of multi-purpose artificial intelligence of things (AIOT) devices, embedded field-programmable gate arrays (FPGA) represent excellent platforms for deep neural network (DNN) acceleration on edge devices. FPGAs possess the advantages of low latency and high energy efficiency, but the scarcity of FPGA development resources challenges the deployment of DNN-based edge devices. Register-transfer level programming, hardware verification, and precise resource allocation are needed to build a high-performance FPGA accelerator for DNNs. These tasks present a challenge and are ti

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Siecha, Roza Teklehaimanot, Getachew Alemu, Jeffrey Prinzie, and Paul Leroux. "5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays." Electronics 12, no. 16 (2023): 3478. http://dx.doi.org/10.3390/electronics12163478.

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A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exp

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Singh, Sanjay, Anil Kumar Saini, Ravi Saini, A. S. Mandal, Chandra Shekhar, and Anil Vohra. "Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector." ISRN Machine Vision 2013 (March 7, 2013): 1–6. http://dx.doi.org/10.1155/2013/820216.

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This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compass operator. The architecture uses a single processing element to compute the gradient for all directions. This greatly economizes on the FPGA resources' usages (more than 40% reduction) while maintaining real-time video frame rates. The measured performance of the architecture is 50 fps for standard PAL size video and 200 fps for CIF size video. The use of pipelining further improved the performance (185 fps for PAL size video and 740 fps for CIF size video) without signif

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Zhou, Zhimei, Yong Wan, Yin Liu, Xiaoyan Guo, Qilin Yin, and Chen Feng. "The advancement of cluster based FPGA place & route technic." MATEC Web of Conferences 309 (2020): 01014. http://dx.doi.org/10.1051/matecconf/202030901014.

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As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in

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Minhas, Umar Ibrahim, Roger Woods, and Georgios Karakonstantis. "Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs." Journal of Signal Processing Systems 93, no. 5 (2021): 587–602. http://dx.doi.org/10.1007/s11265-020-01633-z.

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AbstractWhilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime. This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more efficient mapping of heterogeneous tasks onto the FPGA. In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both

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Shashidhara, K. S., and H. C. Srinivasaiah. "Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs." European Journal of Engineering Research and Science 4, no. 9 (2019): 81–88. http://dx.doi.org/10.24018/ejers.2019.4.9.1515.

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This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource

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Shashidhara, K. S., and H. C. Srinivasaiah. "Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs." European Journal of Engineering and Technology Research 4, no. 9 (2019): 81–88. http://dx.doi.org/10.24018/ejeng.2019.4.9.1515.

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This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource

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K. Suganthi. "Enhancing Sustainable Farming Practices through FPGA Technology." Journal of Information Systems Engineering and Management 10, no. 15s (2025): 176–85. https://doi.org/10.52783/jisem.v10i15s.2442.

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Sustainable farming is essential to address the increasing demand for food while minimizing environmental impact. Field-Programmable Gate Arrays (FPGAs) provide a powerful and energy-efficient platform for real-time processing, which can be leveraged to optimize various aspects of agricultural management. This paper focuses on the use of FPGA technology to enhance real-time monitoring and control systems for irrigation, ensuring that crops receive optimal water levels based on current soil moisture conditions. By interfacing with soil moisture sensors, FPGA systems can collect data and immedia

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Khurshid, Burhan, and Roohie Naaz. "Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations." Electronics ETF 19, no. 1 (2015): 14. http://dx.doi.org/10.7251/els1519014k.

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Modern day field programmable gate arrays(FPGAs) have very huge and versatile logic resources resulting inthe migration of their application domain from prototypedesigning to low and medium volume production designing.Unfortunately most of the work pertaining to FPGAimplementations does not focus on the technology dependentoptimizations that can implement a desired functionality withreduced cost. In this paper we consider the mapping of simpleripple carry fixed-point adders (RCA) on look-up table (LUT)based FPGAs. The objective is to transform the given RCABoolean network into an optimized cir

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Biookaghazadeh, Saman, Pravin Kumar Ravi, and Ming Zhao. "Toward Multi-FPGA Acceleration of the Neural Networks." ACM Journal on Emerging Technologies in Computing Systems 17, no. 2 (2021): 1–23. http://dx.doi.org/10.1145/3432816.

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High-throughput and low-latency Convolutional Neural Network (CNN) inference is increasingly important for many cloud- and edge-computing applications. FPGA-based acceleration of CNN inference has demonstrated various benefits compared to other high-performance devices such as GPGPUs. Current FPGA CNN-acceleration solutions are based on a single FPGA design, which are limited by the available resources on an FPGA. In addition, they can only accelerate conventional 2D neural networks. To address these limitations, we present a generic multi-FPGA solution, written in OpenCL, which can accelerate

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Roy, Kalapi, Bingzhong (David) Guan, and Carl Sechen. "A Sea-of-Gates Style FPGA Placement Algorithm." VLSI Design 4, no. 4 (1996): 293–307. http://dx.doi.org/10.1155/1996/92380.

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Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach con

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Morales-Sandoval, Miguel, Luis Armando Rodriguez Flores, Rene Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, and Ignacio Algredo. "A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks." Journal of Sensors 2021 (January 6, 2021): 1–13. http://dx.doi.org/10.1155/2021/8860413.

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The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyp

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Gnad, Dennis R. E., Cong Dang Khoa Nguyen, Syed Hashim Gillani, and Mehdi B. Tahoori. "Voltage-Based Covert Channels Using FPGAs." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (2021): 1–25. http://dx.doi.org/10.1145/3460229.

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Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logi

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Kalistru, I. I., M. A. Borodin, A. S. Rybkin, and R. A. Gladko. "Methods for implementing the Kuznyechik algorithm on FPGAs." Radio industry 28, no. 3 (2018): 64–70. http://dx.doi.org/10.21778/2413-9599-2018-28-3-64-70.

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Increased volumes and speed of data transmission over computer networks, and also the need to protect the transmitted data, require accordingly to increase the speed of cryptographic data processing. One of the ways to achieve high performance is implementation of FPGAs-based cryptographic equipment. Therewith, to cut the cost of equipment, it is important that encryption modules shall consume a minimum possible hardware resources. The work aims to find the most compact high-speed solution for FPGA-based Kuznyechik block cipher. Several methods for hardware implementation of linear transformat

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Gothandaraman, Akila, Gregory D. Peterson, G. Lee Warren, Robert J. Hinde, and Robert J. Harrison. "A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs." VLSI Design 2010 (February 28, 2010): 1–8. http://dx.doi.org/10.1155/2010/946486.

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Recent advances in Field-Programmable Gate Array (FPGA) technology make reconfigurable computing using FPGAs an attractive platform for accelerating scientific applications. We develop a deeply pipelined and parallel architecture for Quantum Monte Carlo simulations using FPGAs. Quantum Monte Carlo simulations enable us to obtain the structural and energetic properties of atomic clusters. We experiment with different pipeline structures for each component of the design and develop a deeply pipelined architecture that provides the best performance in terms of achievable clock rate, while at the

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Chochaev, R. Zh, D. A. Zheleznikov, G. A. Ivanova, S. V. Gavrilov, and V. I. Enns. "FPGA Routing Architecture Estimation Models and Methods." Proceedings of Universities. Electronics 25, no. 5 (2020): 410–22. http://dx.doi.org/10.24151/1561-5405-2020-25-5-410-422.

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The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement, routing) on a set of the test circuits with subsequent estimation of various parameters for each FPGA architecture being analyzed, had been dominant. Despite the high accuracy, this approach has a long runtime and requires lots of computing resources, as well as CAD tuned to the analyzed FPGA architecture. Modern FPGA contain more than a million

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