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1
Kulesza, Zbigniew, and Zdzisław Gosiewski. "An FPGA Implementation of the Robust Controller for the Active Magnetic Bearing System." Solid State Phenomena 147-149 (January 2009): 399–409. http://dx.doi.org/10.4028/www.scientific.net/ssp.147-149.399.
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The article presents the project design flow that leads to the implementation of the robust controller law in the FPGA chip. The designed robust FPGA controller is going to be used in the heteropolar active magnetic bearing system. The hardware and software architectures of the designed controller are presented. The hardware consists of the market available Spartan-3 Development Board and two specially designed A/D and D/A converters boards. The software architecture is made of several VHDL entities that are translated into the target FPGA chip. The results of the experimental preliminary tests show that the dynamic properties of the designed controller are very good and the authors hope that the dynamic performance, especially the stability of the whole active magnetic bearing system, will improve.
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Barlian, Henryranu Prasetio, and Syauqy Dahnial. "Design of Digital to Analog Voice Data Packet Conversion from Ethernet Protocol using FPGA." TELKOMNIKA Telecommunication, Computing, Electronics and Control 15, no. 2 (2017): 646–53. https://doi.org/10.12928/TELKOMNIKA.v15i2.3612.
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This paper describes a system that is designed to be able to receive packet voice signal using the Ethernet protocol in local networks using FPGA which was programmed decode the data packets. The digital data packets are then converted back into analog data that will be used to control another system. The design was implemented as four components consisting of frame starter unit, address matching unit, buffer unit and DAC processing unit. The system was designed on Xilinx development board using ISE design suite and simulated on ISIM. The test results showed that the system response was less than 40 ms. The result also showed that our proposed design only occupies 11% of number of slices and it also requires 5% of total IOBs on Xilinx Spartan 3-E.
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Piyush, .A. Nitnaware, and A.P.Khandait Dr. "Fpga Based Soil Irrigation Robot." International Journal of Innovative Science and Research Technology 7, no. 6 (2022): 35–37. https://doi.org/10.5281/zenodo.6865146.
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The design of FPGA based soil irrigation robot is proposed. The soil moisture sensor senses the moisture level and gives output to the FPGA board. gives This board gives signal to motor drives which turn on the motor pump. The obstacle detection is done by using IR sensor. This simulation is done on Xilinx software with Spartan 3.
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Lei, Dong Ming, Ping Li, and Nian Yu Zou. "4PSK Signal Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2870–73. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2870.
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Based on the traditional demodulation method of four phase shift keying (QPSK), a QPSK demodulation model was proposed. The FPGA-based QPSK modulation and demodulation system and circuit had been achieved. In Xilinx ISE12.3 development environment, using the SPARTAN-3E development board, the simulation results demonstrate the feasibility of this design.
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Bespalov, Nikolay, and Yury Goryachkin. "Device for Current Test Pulse Development Through a Diode in a Direct Direction." International Journal of Engineering & Technology 7, no. 3.19 (2018): 81. http://dx.doi.org/10.14419/ijet.v7i3.19.16991.
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The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.
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Petrovic, Miljan, and Milica Jovanovic. "Realization of universal periodic sequence generator on FPGA." Serbian Journal of Electrical Engineering 13, no. 1 (2016): 59–70. http://dx.doi.org/10.2298/sjee1601059p.
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This paper presents mathematical modeling and performance evaluation of different realizations of universal periodic digital signal generator based on infinite impulse response filter. The development kit used was Spartan 3E-Starter Board. Using Xilinx software environment and VHDL, the generator has been described and then synthesized and implemented on FPGA chip on the board. Included realizations are direct form II (canonical form) of the filter, as well as hardware optimized single register structure with different control mechanism. Comparative analysis of these two digital systems points to their differences, advantages and weaknesses.
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Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.
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Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.
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Amar, Hebibi, Bartil Arres, and Ziet Lahcene. "Comparison of two new methods for implementa BPSK modulator using FPGA." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 19, no. 2 (2020): 819–27. https://doi.org/10.11591/ijeecs.v19.i2.pp819-827.
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The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.
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Zulfikar, Zulfikar, Shuja A. Abbasi, and Abdul Rahman M. Alamoud. "FPGA Hardware Realization: Addition of Two Digital Signals Based on Walsh Transforms." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (2016): 2688. http://dx.doi.org/10.11591/ijece.v6i6.12040.
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<p>This paper presents hardware realization of addition of two digital signals based on Walsh transforms and inverse Walsh transforms targeted to the Xilinx FPGA Spartan 3 board. The realization utilizes Walsh Transform to convert the input data to frequency domain and the inverse Walsh transform to reconvert the data from frequency domain. The designed system is capable of performing addition, subtraction, multiplication and Arbitrary Waveform Generation (AWG). However, in the present work, the hardware realization of addition only has been demonstrated. The Clock frequency for realization into the board is supplied by an external function generator. Output results are captured using a logic analyzer. Input data to the board (system) is passed manually through the available slide switches on-board.</p>
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Amar, Hebibi, Arres Bartil, and Lahcene Ziet. "Comparison of two new methods for implementa BPSK modulator using FPGA." Indonesian Journal of Electrical Engineering and Computer Science 19, no. 2 (2020): 819. http://dx.doi.org/10.11591/ijeecs.v19.i2.pp819-827.
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<span>The design of electronic systems has become mainly dependent on FPGAs applications. This is due to the softness effectiveness progress by reconfigurable computing and reduced time to develop solutions for digital signal processing. In this article, we present the theoretical backgrounds of a BPSK modulation and hardware designs of the BPSK system, a firstly with the help of Matlab/Simulink reliant on the System Generator and a second with Xilinx ISE VERILOG Hardware Description Language. In order to show the differences between them, in terms of efficiency, duration of development and how many resources are used in FPGA. For the projected system, we have a tendency to aimed toward employing a moderately sized, low-value FPGA to implement the system. The Atlys development board by Digilent to configure develops, and run the system, based on a Xilinx Spartan-6 LX45 FPGA.</span>
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Yaliagr, Sumant S., and Sanket Dessai. "Design and Development of IP for Modified Haar Wavelet Transform (MHWT) Image Fusion using FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (2018): 57. http://dx.doi.org/10.11591/ijres.v7.i1.pp57-66.
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<p>The fast growth in the field of digital imaging applications in remote sensing, bio medical and other satellite applications had created an architecture studies for image fusion in capable to store large amount of data and process. An algorithm considered for the process of image fusion for implementation of FPGA is Modified Haar Wavelet Transform (MHWT) based image fusion where at the time four pixels are consider in calculation of different bands as compared to conventional Haar wavelet based image fusion. The process of modification uses far less memory and computation power. The FPGA implementation of MHWT based image fusion is done on Digilent development board with Spartan 6 series FPGA. The architecture is developed in VHDL. The timing analysis is done and report is obtained for I/O interactions, memory units etc. The architecture is made to run in cosimulation with Simulink. The design is tested with different kinds of images and run successfully. The visual analysis of the resultant fused image is achived and observed.</p>
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Sumant, S. Yaliagr, and Dessai Sanket. "Design and Development of IP for Modified Haar Wavelet Transform (MHWT) Image Fusion using FPGA." International Journal of Reconfigurable and Embedded Systems 7, no. 1 (2018): 57–66. https://doi.org/10.11591/ijres.v7.i1.pp57-66.
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The fast growth in the field of digital imaging applications in remote sensing, bio medical and other satellite applications had created an architecture studies for image fusion in capable to store large amount of data and process. An algorithm considered for the process of image fusion for implementation of FPGA is Modified Haar Wavelet Transform (MHWT) based image fusion where at the time four pixels are consider in calculation of different bands as compared to conventional Haar wavelet based image fusion. The process of modification uses far less memory and computation power. The FPGA implementation of MHWT based image fusion is done on Digilent development board with Spartan 6 series FPGA. The architecture is developed in VHDL. The timing analysis is done and report is obtained for I/O interactions, memory units etc. The architecture is made to run in co-simulation with Simulink. The design is tested with different kinds of images and run successfully. The visual analysis of the resultant fused image is achived and observed.
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Śmigielski, Grzegorz. "Numerical control system based on a programmable logic device." MATEC Web of Conferences 357 (2022): 01005. http://dx.doi.org/10.1051/matecconf/202235701005.
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The article presents a numerical control system of a multi-axis machine built using a programmable logic device.The system consists of PC, motor controller (based on FPGA), power stages and motors. The complete code of controller was written in the VHDL language and implementing in Xilinx Spartan 3 board. The PC program was created using LabVIEW.The logical and functional tests of the system have been carried out. The application of a programmable device enables its quick configuration according to the requirements set by the user.The main advantage of FPGA is the option to expand to following modules, such as the incremental encoder support module, PWM, FOC etc. In these applications, the advantage of the programmable system becomes visible, which due to its specifics, is built for parallel processing or generating signals.
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Ieno, Egidio, Luis Manuel Garcés, Alejandro José Cabrera, and Tales Cleber Pimenta. "Simple generation of threshold for images binarization on FPGA." Ingeniería e Investigación 35, no. 3 (2015): 69–75. http://dx.doi.org/10.15446/ing.investig.v35n3.51750.
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<p class="Abstractandkeywordscontent">This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB<sup>®</sup>/Simulink<sup>®</sup> and Xilinx System Generator<sup>®</sup> tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.</p>
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Suartini, Tuti, Sri Lestari Harja, and Aan Sukandar. "Improvement of a cashing trainer assembly methodology for FPGA development in vocational education students." Journal of Social Studies (JSS) 18, no. 2 (2022): 217–28. http://dx.doi.org/10.21831/jss.v18i2.53195.
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Learning media is defined as a tool used in conveying learning messages to students. Teachers or lectures can use the media to stimulate thoughts, feelings, attention and abilities or skills, and one of them is the use of trainers. The development board FPGA of trainer tools for skill learning in digital technology-based vocational education today has been a problem that obstructs the growth of experts in high-tech-based vocational field.The Spartan development board and its software can be used to elaborate the improvement of skill learning. This research analyse how the development board can be used to enhance students’ thinking skill. The trainer tools in the market lately are still in the form of a mother board that can be interfaced with various devices commonly used to perform various digital automation technology. This study elaborates the use of the cashing trainer assembly among electrical engineering students and mechanical engineering students in a joint project to assembly a development mother board.The learning media is also used in group training among the peers.Based on trials and observations made by researchers, the students as the object of research results, have not performed optimally to combine planning of cashing trainer assembly methodology and practice in the assembly.
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Rashidi, Bahram. "Low-Cost and Optimized Two Layers Embedded Board Based on ATmega32L Microcontroller and Spartan-3 FPGA." International Journal of Modern Education and Computer Science 5, no. 3 (2013): 56–68. http://dx.doi.org/10.5815/ijmecs.2013.03.08.
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Aamir, Muhammad, Nishat Ahmad Khan, and B. S. Chowdhry. "Benchmarking of Data Communication Protocol for Integration of Telecontrol Interface with RTU." Sir Syed University Research Journal of Engineering & Technology 5, no. 1 (2015): 4. http://dx.doi.org/10.33317/ssurj.51.
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The outcome of this research work is focused on optimized the design of wireless link for an FPGA based RemoteTerminal Unit (RTU). A situation representing multiple RTUs communicating with one Telecontrol Interface (TCI) developed to address optimized implementation of wireless SCADA. It was then further verified by means of benchmarking. The hardware implementation and verification of this particular RTU design has been done using a starter kit based on XILINX Spartan-3 Series FPGA with 500K logic gates and MHX-2400 frequency hopping2.4 GHz spread-spectrum communications module which is used as Telecontrol Interface. The FPGA based RTU isflexible in terms of I/Os, CPU and radio related configurations and any expansion in design can be accommodated quickly if needed as FPGA based designs are reconfigurable. However, the integration of MHX-2400 had been examined and found suitable as Telecontrol Interface for this development.
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Huang, Wan Fu. "Designing a Four-by-Four Keypad Arbitrary-Key-Entry Detector." Applied Mechanics and Materials 433-435 (October 2013): 887–94. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.887.
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This paper presents a field programmable gate array (FPGA) prototype of a four-by-four keypad arbitrary-key-entry detector design for entering any arbitrary set of the 4x4 keypad keys. The number of the valid keys was defined by a multiple-bit mask input. The character code of the prohibited key would not be generated after a key stroke. A valid-key stroke caused the detector circuit to generate a 4-bit hexadecimal character code and a sampling tick for the next-stage device to capture the pressed key information. The detector design and the testing circuitry were implemented on an Atlys Spartan-6 FPGA Development Board. The design itself can be incorporated into a wide variety of key-entry tools on electronic instruments, mechanical devices, medical apparatus, and more, to improve the key-stroke filtering and ease the interface connection.
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Priramadhi, Rizki Ardianto, and Denny Darlis. "Prototyping Feed-Forward Artificial Neural Network on Spartan 3S1000 FPGA for Blood Type Classification." IJAIT (International Journal of Applied Information Technology) 5, no. 01 (2022): 34. http://dx.doi.org/10.25124/ijait.v5i01.3220.
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In this research, a Feed-Forward Artificial Neural Network design was implemented on Xilinx Spartan 3S1000 Field Programable Gate Array using XSA-3S Board and prototyped blood type classification device. This research uses blood sample images as a system input. The system was built using VHSIC Hardware Description Language to describe the feed-forward propagation with a backpropagation neural network algorithm. We use three layers for the feed-forward ANN design with two hidden layers. The hidden layer designed has two neurons. In this study, the accuracy of detection obtained for four-type blood image resolutions results from 86%-92%, respectively.
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Triqadafi, Adin O., Tyas N. Zafirah, Hari A. Dharmawan, and Setyawan P. Sakti. "Four-Channels High-Resolution Frequency Counter for QCM Sensor Array Using Generic FPGA XC6SLX9 Board." Journal of Electrical and Computer Engineering 2023 (May 9, 2023): 1–10. http://dx.doi.org/10.1155/2023/5182455.
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A frequency counter is essential for resonance-based sensors like quartz crystal microbalance. An electronic nose or tongue using a QCM sensor array requires a multichannel frequency counter to detect the frequency shift of the sensors simultaneously. The frequency counter’s resolution, precision, and sampling speed are important factors. Board size, energy consumption, and rapid deployment are also considered in the design. This work shows the development of an independent multichannel frequency counter using a commercial Xilinx Spartan 6 series XC6SLX9 board module and a microcontroller board. Both modules are general-purpose modules; therefore, there is no need for a printed circuit board design, resulting in a quick implementation: the use of FPGA results in a compact size and low energy consumption. The developed counter is designed based on a reciprocal counter utilizing the internal logic block of the FPGA. The FPGA module has a built-in 50 MHz TCXO clock and is the reference clock. The high-resolution timing of the counter is realized by multiplying the 50 MHz clock by 6 to reach 300 MHz. The multiplication utilizes the PLL modules in the FPGA. The high precision and accuracy of the counter are achieved by calibrating the timing clock to a 10 MHz rubidium oscillator. The data communication to the microcontroller is done via the SPI by implementing the SPI protocol in the FPGA. The resource is optimized by utilizing PLL and DSP blocks for the counter. Only 5% registers and 5% LUTs of the FPGA resource are used to build a four-channel frequency counter. The result shows that the counter can measure the frequency of incoming signals with a resolution of 0.033 Hz at 10 MHz with a sampling time of 1 second. The system has been tested to monitor the frequency changes of a QCM sensor array.
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N. Krishna Kumari. "FPGA Implementation of Direct Torque Control for Surface Mounted Permanent Magnet Synchronous Motor using PID Controller." Journal of Electrical Systems 20, no. 6s (2024): 2911–21. http://dx.doi.org/10.52783/jes.3296.
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This paper presents a real time FPGA implementation of a Direct Torque Controller for Surface Mounted Permanent magnet Synchronous Motor (SPM) using PID controller. The Direct Torque algorithm with PID controller is designed and implemented using VHDL.The complete digital controller is divided into three modules. From first module position of flux vector is found based on the flux error and torque error and the sector. The torque error is obtained from PID controller. From second module the switching state of the inverter is found based on the position of the flux vector, whereas third module indicates the complete digital controller. The digital controller algorithm presented in this paper has been implemented on a Xilinx Spartan-3 FPGA board. The inverter keeps the same state till the outputs of the hysteresis controllers change states. This inverter is fed to the SPM to maintain a desired constant speed when the load varies. Experimental results on FPGA implementation of a Direct Torque Controller for SPM using PID controller are provided in this paper for two reference speeds and two load torques.
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Liu, Hai Ke, Shun Wang, Xin Gna Kang, and Jin Liang Wang. "Realization of NAND FLASH Control Glueless Interface Circuit." Advanced Materials Research 1008-1009 (August 2014): 659–62. http://dx.doi.org/10.4028/www.scientific.net/amr.1008-1009.659.
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The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.
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Rodríguez-Orozco, Eduardo, Enrique García-Guerrero, Everardo Inzunza-Gonzalez, et al. "FPGA-based Chaotic Cryptosystem by Using Voice Recognition as Access Key." Electronics 7, no. 12 (2018): 414. http://dx.doi.org/10.3390/electronics7120414.
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A new embedded chaotic cryptosystem is introduced herein with the aim to encrypt digital images and performing speech recognition as an external access key. The proposed cryptosystem consists of three technologies: (i) a Spartan 3E-1600 FPGA from Xilinx; (ii) a 64-bit Raspberry Pi 3 single board computer; and (iii) a voice recognition chip manufactured by Sunplus. The cryptosystem operates with four embedded algorithms: (1) a graphical user interface developed in Python language for the Raspberry Pi platform, which allows friendly management of the system; (2) an internal control entity that entails the start-up of the embedded system based on the identification of the key access, the pixels-entry of the image to the FPGA to be encrypted or unraveled from the Raspberry Pi, and the self-execution of the encryption/decryption of the information; (3) a chaotic pseudo-random binary generator whose decimal numerical values are converted to an 8-bit binary scale under the VHDL description of m o d ( 255 ) ; and (4) two UART communication algorithms by using the RS-232 protocol, all of them described in VHDL for the FPGA implementation. We provide a security analysis to demonstrate that the proposed cryptosystem is highly secure and robust against known attacks.
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Bhuyan, Kanhu Charan, Sumit Kumar Sao, and Kamalakanta Mahapatra. "An FPGA Based Controller for a SOFC DC-DC Power System." Advances in Power Electronics 2013 (December 28, 2013): 1–12. http://dx.doi.org/10.1155/2013/345646.
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Fuel cells are an attractive option for alternative power and of use in a variety of applications. This paper proposes a state space model for the solid oxide fuel cell (SOFC) based power system that comprises fuel cell, DC-DC buck converter, and load. In this investigation we have taken up a case study for SOFC feeding a DC load where a DC-DC buck converter acts as the interface between the load and the source. A proportional-integral (PI) controller is used in conjunction with pulse width modulation (PWM) that computes the pulse width and switches the MOSFET at the right instant so that the desired voltage is obtained. The proposed model is validated through extensive simulation using MATLAB/SIMULINK. Controller for the fuel cell power system (FCPS) is prototyped using XC3S500E development board containing a SPARTAN 3E Xilinx FPGA that simplifies the entire control circuit besides providing additional flexibility for further improvement. The results clearly indicate improved performance and validate our proposed model.
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Rashidi, Bahram, and Ghader Karimian. "A Two Layers Novel Low-Cost and Optimized Embedded Board Based on TMS320C6713 DSP and Spartan-3 FPGA." International Journal of Modern Education and Computer Science 5, no. 4 (2013): 64–75. http://dx.doi.org/10.5815/ijmecs.2013.04.08.
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ASHWINI, DESHMUKH, and WAJE MRS.MANISHA. "FPGA IMPLEMENTATION OF DWT FOR ECG SIGNAL PRE-PROCESSING." JournalNX - A Multidisciplinary Peer Reviewed Journal 3, no. 6 (2017): 83–87. https://doi.org/10.5281/zenodo.1438143.
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This paper falls inside the extent of execution of Advanced Signal Processing (DSP) calculations in the best in class Field Programmable Gate Array (FPGA); along these lines, it shows an FPGA-based inserted framework outline and its assessment for a pre-handling phase of ECG flag investigation; such an outline employments the Discrete Wavelet Transform (DWT) approach. In this way, the framework bargains primarily with the pattern meander ( BLW) evacuation also, the QRS location. As the DWT-based usage requires critical equipment assets, our framework is composed, in a soul of streamlining, to fit in ease and low-control FPGA gadget for convenient restorative hardware. It is created with the Xilinx configuration device, System Generator for DSP which is a module to Simulink. This equipment configuration is tried with ECG information records from the MIT-BIH Arrhythmia database. By a cautious visual examination of the reenactment comes about, we report that the entire outline gives a decent reaction particularly to the piece of BLW concealment; in addition, just this part concerning the BLW is tried with a JTAG Hardware co-reenactment in the accessible load up at the season of experimentation, that is the Nexys 3 board of Digilent including Xilinx SPARTAN 6 XC6SLX16. https://journalnx.com/journal-article/20150359
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Espinal, A., H. Rostro-Gonzalez, M. Carpio, et al. "Quadrupedal Robot Locomotion: A Biologically Inspired Approach and Its Hardware Implementation." Computational Intelligence and Neuroscience 2016 (2016): 1–13. http://dx.doi.org/10.1155/2016/5615618.
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A bioinspired locomotion system for a quadruped robot is presented. Locomotion is achieved by a spiking neural network (SNN) that acts as a Central Pattern Generator (CPG) producing different locomotion patterns represented by their raster plots. To generate these patterns, the SNN is configured with specific parameters (synaptic weights and topologies), which were estimated by a metaheuristic method based on Christiansen Grammar Evolution (CGE). The system has been implemented and validated on two robot platforms; firstly, we tested our system on a quadruped robot and, secondly, on a hexapod one. In this last one, we simulated the case where two legs of the hexapod were amputated and its locomotion mechanism has been changed. For the quadruped robot, the control is performed by the spiking neural network implemented on an Arduino board with 35% of resource usage. In the hexapod robot, we used Spartan 6 FPGA board with only 3% of resource usage. Numerical results show the effectiveness of the proposed system in both cases.
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Saber, Mohamed, and Marwa M. Eid. "Low power pseudo-random number generator based on lemniscate chaotic map." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 863. http://dx.doi.org/10.11591/ijece.v11i1.pp863-871.
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Lemniscate chaotic map (LCM) provides a wide range of control parameters, canceling the need for several rounds of substitutions, and excellent performance in the confusion process. Unfortunately, the hardware model of LCM is complex and consumes high power. This paper presents a proposed low power hardware model of LCM called practical lemniscate chaotic map (P-LCM) depending on trigonometric identities to reduce the complexity of the conventional model. The hardware model designed and implement into the field programmable gate array (FPGA) board, Spartan-6 SLX45FGG484-3. The proposed model achieves a 48.3 % reduction in used resources and a 34.6 % reduction in power consumption compared to the conventional LCM. We also introduce a new pseudo-random number generator based on a proposed low power P-LCM model and perform the randomization tests for the proposed encryption system.
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Thilagavathy, J., and L. Surya. "Implementation of HOG based feature extraction method." i-manager's Journal on Digital Signal Processing 11, no. 2 (2023): 9. http://dx.doi.org/10.26634/jdp.11.2.20314.
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Human detection on emerging intelligent transportation systems is a challenging task in hardware implementation. The Histogram of Oriented Gradients (HOG)-based human detection is the most successful algorithm due to its superior performance. Unfortunately, more intensive computations and poor performance at a multi-scale and low-contrast make human detection more difficult and unreliable. To address the aforementioned problems, an efficient histogram of edge-oriented gradients-based human detection is proposed to preserve the edge gradients at low-contrast and support multi-scale detection. The proposed algorithm uses approximation methods and adopts a pipelined structure that utilizes low-cost and high-speed, respectively. Experiments conducted on various challenging human datasets show that the proposed method provides efficient detection. This algorithm has been synthesized on Xilinx Spartan 3 FPGA software and board, achieving better hardware utilization compared to other state-of-the-art approaches.
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Al-Rubaye, Wajdi T. Joudah, Ahmed S. Al-Araji, and Hayder A. Dhahad. "An Adaptive Digital Neural Network-Like-PID Control Law Design for Fuel Cell System Based on FPGA Technique." Journal of Engineering 26, no. 9 (2020): 24–44. http://dx.doi.org/10.31026/j.eng.2020.09.03.
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This paper proposes an on-line adaptive digital Proportional Integral Derivative (PID) control algorithm based on Field Programmable Gate Array (FPGA) for Proton Exchange Membrane Fuel Cell (PEMFC) Model. This research aims to design and implement Neural Network like a digital PID using FPGA in order to generate the best value of the hydrogen partial pressure action (PH2) to control the stack terminal output voltage of the (PEMFC) model during a variable load current applied. The on-line Particle Swarm Optimization (PSO) algorithm is used for finding and tuning the optimal value of the digital PID-NN controller (kp, ki, and kd) parameters that improve the dynamic behavior of the closed-loop digital control fuel cell system and to achieve the stability of the desired output voltage of fuel cell. The numerical simulation results (MATLAB) package along with the schematic design experimental work using Spartan-3E xc3s500e-4fg320 board with the Xilinx development tool Integrated Software Environment (ISE) version 14.7 and using Verilog hardware description language for design testing are illustrated the performance enhancement of the proposed an adaptive intelligent FPGA-PID-NN controller in terms of error voltage reduction and generating optimal value of the hydrogen partial pressure action (PH2) without oscillation in the output and no saturation state when these results are compared with other controllers.
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Meddah, Karim, Malika Kedir Talha, Hadjer Zairi, et al. "FPGA IMPLEMENTATION SYSTEM FOR QRS COMPLEX DETECTION." Biomedical Engineering: Applications, Basis and Communications 32, no. 01 (2020): 2050005. http://dx.doi.org/10.4015/s1016237220500052.
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Due to the rising number of cardiovascular diseases death, the monitoring of cardiac patients has become a primary objective in the world. In this context, a fully FPGA-based system, for ECG signal monitoring and cardiac arrhythmia detection, has been proposed. The proposed QRS detection method is inspired by the Pan and Tompkins algorithm. It is optimized to be implemented in FPGA board Spartan 3 E (Nexys 2) using the VHDL language on the Xilinx ISE 14.2. In order to evaluate the effectiveness and reliability of our system, three comparative studies have been performed. The first comparison targeted the different results obtained with a floating-point representation under Matlab on one hand, and a fixed point representation under Xilinx ISE on the other hand, both using the MIT-BIH arrhythmia database records. The second comparison concerns the results obtained from the records of eight preselected subjects, with a commercialized electronic armband device ROMED BP-WR20 in a real-time test. The third is a comparison between the performance of our proposed method with the recent works in terms of reducing the FPGA resources list. The full embedded system has been realized completely from the signal acquisition to the display using the analog discovery device. The designed architecture has been validated using records obtained from the Massachusetts Institute of Technology — Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real-time via the analog discovery device. The overall accuracy and sensitivity are obtained as 97.6% and 97.3%, respectively.
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Khushboo, Bais* Zoonubiya Ali. "DESIGN OF A HIGH-SPEED WALLACE TREE MULTIPLIER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 6 (2016): 476–80. https://doi.org/10.5281/zenodo.55546.
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Multiplication is one of the most common arithmetic operations employed in digital systems, but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improving the efficiency of the circuit. The ever increasing need for development of efficient and high speed multipliers has motivated several researchers to go a step ahead and present some novel approach. This paper presents an approach towards the reduction of delay in the Wallace tree multipliers by using 4:2 compressors along with full-adders and half-adders, in the partial product reduction stage; and employing Kogge-Stone adder for the final addition. The proposed multiplier has been designed using Xilinx ISE Design Suite 14.7 and implemented for Spartan 3 FPGA.
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Mohamed, Elghayyaty, Wahbi Azeddine, El Idrissi Anas El Habti, Mouhib Omar, and Abdelkader Hadjoudja. "Development and Validation of an optimized syndromes block for reed solomon decoder." ITM Web of Conferences 52 (2023): 03008. http://dx.doi.org/10.1051/itmconf/20235203008.
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Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.
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S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.
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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster speed. Concurrently, Look Ahead Adders are strategically deployed in the initial stages of the enhanced adder to capitalize on their computational prowess, particularly beneficial for smaller bit numbers. A 64-bit hybrid CSLA is realized on the Xilinx Spartan 6 FPGA development board. The resultant modified hybrid carry select adder demonstrates notable improvements in speed and energy efficiency, surpassing conventional carry select adder implementations.</em>
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Sotnik, О., S. Marchenko, V. Litvinenko, and О. Syanov. "RADIO COMMUNICATION CHANNEL WITH FREQUENCY MODULATED SIGNAL BASED ON PROGRAMMABLE LOGICAL INTEGRATED CIRCUIT." Collection of scholarly papers of Dniprovsk State Technical University (Technical Sciences) 1, no. 38 (2021): 75–83. http://dx.doi.org/10.31319/2519-2884.38.2021.9.
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This paper presents the results of an experimental study of a radio communication channel (RF) with a frequency-modulated signal based on a programmable logic integrated circuit (FPGA). The work highlights the features of hardware and software implementation of algorithms for the synthesis of frequency-modulated signal and demodulation of this signal using FPGA in real time. The software part is made in the development environment of ISE WebPack 14.7 in Verilog language with the ability to visualize the results of GTKWave. Hardware implementation is performed on the basis of FPGA (Spartan-6) using a debug board from Alinx AX309.
 The experimental study consists of two stages of the study of the FM oscillator modulator and the synchronous FM oscillator demodulator. In the course of research, the amplitude spectral characteristics of the signals (amplitude spectra) were obtained: at the output of the modulator and demodulator of the frequency-modulated signal, which have good agreement with the simulation results. The quality of the hardware synchronous demodulation of the FM signal based on the phase tuning system was confirmed by the result of the obtained spectrum of the restored information signal, in which the ratio between the first harmonic and the second is 51.87 dBm. When obtaining the results of experimental studies of the RH system, it was found necessary to take into account the peculiarities of the arithmetic of integers, which make errors in the hardware implementation of DSP algorithms.
 Thus, the use of programmable logic integrated circuits at the present stage of development of telecommunications and radio engineering opens wide opportunities for the construction of high-speed digital RH systems with parallel signal processing in real time.
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Siswoyo, Bambang, M. Agus Choiron, Yudy Surya Irawan, and I. N. G. Wardana. "System Architecture and FPGA Embedding of Compact Fuzzy Logic Controller for Arm Robot Joints." Applied Mechanics and Materials 493 (January 2014): 480–85. http://dx.doi.org/10.4028/www.scientific.net/amm.493.480.
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This research is about the system architecture for embedding of the Compact Fuzzy Logic Controller (Compact-FLC) into the FPGA with a minimal need in device resource. This exciting research is to minimize the FPGA resources needed to build Compact-FLC based on FPGA for controlling each joint of arm robots manipulator. Compact-FLC results of this research have been used in the XILINX Spartan 3 XC3S1000 FPGA.The Compact-FLC has been applied with satisfactory results as Servo Controller for one joint of arm robot manipulator which the results showed that the controller achieved a process speed of 65,4uS, which is equivalent to a maximum sampling frequency of 15.290 KHz. Output membership function in this Compact-FLC used singleton membership function with Center Of Area algorithm. Two input membership functions, i.e E (Error) and CE (Change Error) have been used, both formed from several combination of triangular membership functions. The maximum number of fuzzysets that can be processed is sixteen. The overlapping function is not limited because there have been 256 if-then rule available as look up table in FPGA's ROM.The device utilization summary from ISE of XILINX development software gave the following data: Slice FlipFlops needed are 3869 or 25% of 15360 availability, 4 input LUT needed are 2319 or 15% of 15360 availability, Blocks of RAM needed are 4 or 16% of 24 availability, MULT18x18s needed are 2 or 8% of 24 availability, GCLKs needed are 2 or 25% of 8 availability, Bonded IOBs needed are 32 or 18% of 173 availability.
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Marakumbi, Prakash, and Satish Bhairannawar. "Efficient reconfigurable architecture to enhance medical image security." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 3 (2023): 1516. http://dx.doi.org/10.11591/ijeecs.v30.i3.pp1516-1524.
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Medical images are one of the most critical and sensitive types of data in information systems. For the secure storage and transfer of medical images, confidentiality is the most important aspect. This paper presents efficient embedding technique to enhance medical image security. The Gaussian filters are used as preprocessing to remove high frequency components and then applied to cumulative distribution function (CDF) 5/3 wavelet to obtain LL band features. Similarly, the LL band features of cover image are obtained. The alpha bending technique combines both the LL band features of cover and secret image to form first level of encryption and now with other high frequency bands of LH, HL and HH applied to Inverse CDF 5/3 obtains an encrypted image which is then transferred along with key obtained through other bands of LH, HL and HH. The key generated acts as additional level of security and similarly, at the receiver the opposite operations are performed to obtain the original secrete image. The performance is measured in terms of Peak signal-to-noise ratio (PSNR) and is compared with existing techniques to validate the results. Further, the entire architecture is synthesized on spartan 6 field-programmable gate array (FPGA) board to compare the hardware utilizations.
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Prakash, Marakumbi, and Bhairannawar Satish. "Efficient reconfigurable architecture to enhance medical image security." Efficient reconfigurable architecture to enhance medical image security 30, no. 3 (2023): 1516–24. https://doi.org/10.11591/ijeecs.v30.i3.pp1516-1524.
Full textAbstract:
Medical images are one of the most critical and sensitive types of data in information systems. For the secure storage and transfer of medical images, confidentiality is the most important aspect. This paper presents efficient embedding technique to enhance medical image security. The Gaussian filters are used as preprocessing to remove high frequency components and then applied to cumulative distribution function (CDF) 5/3 wavelet to obtain LL band features. Similarly, the LL band features of cover image are obtained. The alpha bending technique combines both the LL band features of cover and secret image to form first level of encryption and now with other high frequency bands of LH, HL, and HH applied to Inverse CDF 5/3 obtains an encrypted image which is then transferred along with key obtained through other bands of LH, HL, and HH. The key generated acts as additional level of security and similarly, at the receiver the opposite operations are performed to obtain the original secrete image. The performance is measured in terms of Peak signal-to-noise ratio (PSNR) and is compared with existing techniques to validate the results. Further, the entire architecture is synthesized on spartan 6 field-programmable gate array (FPGA) board to compare the hardware utilizations.
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Bazhenova, D. D., M. Aiman Al Akkad, and A. A. Ivakin. "Development of a Technological Module for Control and Verification of on-Board Equipment for Storing Temporary Data." Intellekt. Sist. Proizv. 19, no. 3 (2021): 47–54. http://dx.doi.org/10.22213/2410-9304-2021-3-47-54.
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High-speed radio link HSRL is designed to transmit target information from spacecraft equipment to the ground. A block of onboard equipment for storing temporary data OESTD is a part of the onboard equipment of a high-speed radio link OEHSRL. Before the spacecraft is launched into space, acceptance tests of the input control are carried out. To do this, it was necessary to develop testing equipment TE and software for it. TE of OESTD is designed to check the OESTD in general and each block in particular during autonomous tests. This paper considers the subsystem of technological software - a component of the TE software system, which allows checking the operation of the FPGA as part of the OESTD. The subsystem main algorithms and functions performed by the subsystem are given. The interaction of the operator of control and testing equipment with programmable logic integrated circuits FPGA, which are part of the on-board equipment block for storing temporary data of the OESTD, is considered. Debugging software is required to enable this interaction. An FPGA with the RISC-V architecture was chosen, debugging via GRMON turned out to be impossible and OpenOCD was chosen. As a result, a technological software module was developed for testing and ensuring the operability of the FPGA as part of the onboard equipment for storing temporary data. The following components were developed: a subsystem for interaction with the device to ensure the ability to send commands and receive response messages, service functions to convert response messages into a readable form for the operator, a subsystem for interaction of the module with the main frame of the TE software, and widgets to provide the ability to manually enter commands from the user conveniently.
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Fadhil, Muthna Jasim. "Optimization of Power Consumption for the Design of 802.11n MIMO_OFDM System." Journal of University of Babylon for Engineering Sciences 26, no. 4 (2018): 172–84. http://dx.doi.org/10.29196/jub.v26i4.795.
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In modern systems communication, different methods have been improved to change the prior imitative techniques that process communication data with high speed. It is necessary to improve (OFDM) Orthogonal Frequency Division Multiplexing technique because the development in the guideline communication of wireless system which include security data and transmission data reliability. The applications communications of wireless is important to develop in order to optimize the process of communication leads to reduce the level consumption energy of the output level signal. The architecture of VLSI is used to optimize the performance transceiver in 802.11 n OFDM-MIMO systems, this idea concentrate on the design of 6x6 MIMO_OFDM system in software simulink of MATLAB then using generator system for transfer to code of VHDL and applying in FPGA Xilinx Spartan 3 XC3S200 . The modelsim used to get the simulation while Xilinx power estimator is used to calculate power. The results registered total power consumption about 94mW while compared with previous work was 136mW which means a high reduction of about 30.8% .
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Komal, Gophane, and P. C. Bhaskar Dr. "An Adaptive IoT Framework using FPGA Based SOC for varying Applications." International Journal of Trend in Scientific Research and Development 2, no. 3 (2018): 728–33. https://doi.org/10.31142/ijtsrd10976.
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With the evolution of IoT, it is expected to create large impact on human lives. IoT is a region where world convergences with physical world. The IoT is an intelligent network which connects all things to the Internet for the purpose of exchanging information and communicating through the information sensing devices. It achieves the goal of intelligent identifying, locating, tracking, monitoring, and managing things. IoT Internet of Things is a system where objects are embedded with sensor technology to interact with each other over wireless communication medium to generate exchange and transfer data without human interaction. In this paper we presented, FPGA based Adaptive IoT framework for Distinct Applications, based on Cloud server. In this, the controllers can read, collect, and transmit huge volume of data over the internet. This paper is focusing, the development of an adaptive IoT system that can be used in any field for wireless communication. Komal Gophane | Dr. P. C. Bhaskar "An Adaptive IoT Framework: using FPGA Based SOC for varying Applications" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018, URL: https://www.ijtsrd.com/papers/ijtsrd10976.pdf
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Golitsyn, Aleksandr, and Natalya Seyfi. "The Architecture of the Digital Device for Round-The-Clock Surveillance." Siberian Journal of Physics 7, no. 3 (2012): 129–36. http://dx.doi.org/10.54362/1818-7919-2012-7-3-129-136.
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The article describes the hardware development of the image processing system which is used as a viewer in digital day-and-night surveillance device. During the work the most suitable image sensor for the surveillance in low luminance conditions is selected, image processing module based on FPGA is developed and the printed circuit board of the device is designed
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Stęplewski, Wojciech, Mateusz Mroczkowski, Radoslav Darakchiev, Konrad Futera, and Grażyna Kozioł. "New technologies of multi-layered printed circuit boards, intended of rapid-design electronic modules." Circuit World 41, no. 3 (2015): 121–24. http://dx.doi.org/10.1108/cw-03-2015-0008.
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Purpose – The purpose of this study was the use of embedded components technology and innovative concepts of the printed circuit board (PCB) for electronic modules containing field-programmable gate array (FPGA) devices with a large number of pins (e.g. Virtex 6, FF1156/RF1156 package, 1,156 pins). Design/methodology/approach – In the multi-layered boards, embedded passive components that support FPGA device input/output (I/O), such as blocking capacitors and pull-up resistors, were used. These modules can be used in rapid design of electronic devices. In the study, the MC16T FaradFlex material was used for the inner capacitive layer. The Ohmega-Ply RCM 25 Ω/sq material was used to manufacture pull-up resistors for high-frequency pins. The embedded components have been connected to pins of the FPGA component by using plated-through holes for capacitors and blind vias for resistors. Also, a technique for a board-to-board joining, by using castellated terminations, is described. Findings – The fully functional modules for assembly of the FPGA were manufactured. Achieved resistance of embedded micro resistors, as small as the smallest currently used surface-mount device components (01005), was below required tolerance of 10 per cent. Obtained tolerance of capacitors was less than 3 per cent. Use of embedded components allowed to replace the pull-up resistors and blocking capacitors and shortens the signal path from the I/O of the FPGA. Correct connection to the castellated terminations with a very small pitch was also obtained. This allows in further planned studies to create a full signal distribution system from the FPGA without the use of unreliable plug connectors in aviation and space technology. Originality/value – This study developed and manufactured several innovative concepts of signal distribution from printed circuit boards. The signal distribution solutions were integrated with embedded components, which allowed for significant reduction in the signal path. This study allows us to build the target object that is the module for rapid design of the FPGA device. Usage of a pre-designed module would lessen the time needed to develop a FPGA-based device, as a significant part of the necessary work (mainly designing the signal and power fan-out) will already be done during the module development.
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Allani, Mohamed Yassine, Jamel Riahi, Silvano Vergura, and Abdelkader Mami. "FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load." Energies 14, no. 8 (2021): 2108. http://dx.doi.org/10.3390/en14082108.
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The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.
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Umapathi, N. "Design of Mixed Radix FFT Algorithm Using FPGA." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 06 (2025): 1–9. https://doi.org/10.55041/ijsrem49458.
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ABSTRACT: FFT algorithms like radix-2 are efficient for signal lengths that are powers of two, many practical applications require FFT computation for arbitrary input sizes. To address this limitation, this project presents the design and FPGA-based implementation of a Mixed Radix FFT algorithm, which accommodates composite input sizes by combining multiple radix strategies (e.g., radix-2, radix-3, radix-5). The proposed architecture leverages the parallel processing capabilities of Field Programmable Gate Arrays (FPGAs) to optimize performance, reduce latency, and improve resource utilization. The design is implemented using hardware description languages (HDLs) such as VHDL or Verilog, synthesized and verified on a suitable FPGA development board. Key aspects of the design include modular decomposition, pipelining, and memory-efficient data management. he results demonstrate that the Mixed Radix FFT design on FPGA offers high flexibility and computational efficiency, making it well-suited for real-time signal processing applications in embedded systems.
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Vaidyanathan, Sundarapandian, Ahmad Taher Azar, Ibrahim A. Hameed, et al. "Bifurcation Analysis, Synchronization and FPGA Implementation of a New 3-D Jerk System with a Stable Equilibrium." Mathematics 11, no. 12 (2023): 2623. http://dx.doi.org/10.3390/math11122623.
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This research paper addresses the modelling of a new 3-D chaotic jerk system with a stable equilibrium. Such chaotic systems are known to exhibit hidden attractors. After the modelling of the new jerk system, a detailed bifurcation analysis has been performed for the new chaotic jerk system with a stable equilibrium. It is shown that the new jerk system has multistability with coexisting attractors. Next, we apply backstepping control for the synchronization design of a pair of new jerk systems with a stable equilibrium taken as the master-slave chaotic systems. Lyapunov stability theory is used to establish the synchronization results for the new jerk system with a stable equilibrium. Finally, we show that the FPGA design of the new jerk system with a stable equilibrium can be implemented using the FPGA Zybo Z7-20 development board. The design of the new jerk system consists of multipliers, adders and subtractors. It is observed that the experimental attractors are in good agreement with simulation results.
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Firdaus, Firdaus, Rivanol Chadri, and Nasrullah Nasrullah. "Rancang Bangun Generator PWM Berbasis Mikrokontroler AVR ATmega." Elektron : Jurnal Ilmiah 12, no. 2 (2020): 61–66. http://dx.doi.org/10.30630/eji.12.2.171.
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PWM is widely used in the fields of automatic control, power electronics and cellular communications. Previous research designed a PWM generator using the OMAP-L138 chip to produce a simple, high-precision, flexible and portable circuit. Another generator uses a single board computer FEZ Panda III and an Arduino board for power inverters. While the FPGA Spartan 3 is also used to generate PWM signals that can vary the duty cycle. In this paper, the PWM signal generator is made using the AVR ATmega8535 microcontroller where the frequency parameters and the output signal duty cycle can be adjusted via the keypad. The signal is tested using a measuring instrument for its accuracy. The ATmega AVR microcontroller family has a timer / counter with one of its operating modes, namely fast PWM. In order to change the frequency and duty cycle as desired, the ICR register is used to store the TOP value and the OCR register for the MAX value. The OCR value determine the duty cycle and the ICR value specify the frequency. The results are the higher the PWM frequency, the greater the value of the measured and desired frequency difference, this is because the large frequency makes ICR register value becomes small even though the frequency divider at minimum value. The difference between measurements and calculations on the Duty Cycle gives the result under 1%. This difference also occurs due to the rounding of the ICR and OCR values, but at a frequency of 20 kHz and a 25% Duty Cycle where the ICR value is 599 and OCR is 116 resulting in the minimum difference in frequency and Duty Cycle. From the experiments that have been carried out, the design of the PWM generator based on the AVR ATmega microcontroller has been successfully realized
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Firdaus, Firdaus, Rivanol Chadri, and Nasrullah Nasrullah. "Rancang Bangun Generator PWM Berbasis Mikrokontroler AVR ATmega." Elektron : Jurnal Ilmiah 12, no. 2 (2020): 61–66. http://dx.doi.org/10.30630/eji.12.2.171.
Full textAbstract:
PWM is widely used in the fields of automatic control, power electronics and cellular communications. Previous research designed a PWM generator using the OMAP-L138 chip to produce a simple, high-precision, flexible and portable circuit. Another generator uses a single board computer FEZ Panda III and an Arduino board for power inverters. While the FPGA Spartan 3 is also used to generate PWM signals that can vary the duty cycle. In this paper, the PWM signal generator is made using the AVR ATmega8535 microcontroller where the frequency parameters and the output signal duty cycle can be adjusted via the keypad. The signal is tested using a measuring instrument for its accuracy. The ATmega AVR microcontroller family has a timer / counter with one of its operating modes, namely fast PWM. In order to change the frequency and duty cycle as desired, the ICR register is used to store the TOP value and the OCR register for the MAX value. The OCR value determine the duty cycle and the ICR value specify the frequency. The results are the higher the PWM frequency, the greater the value of the measured and desired frequency difference, this is because the large frequency makes ICR register value becomes small even though the frequency divider at minimum value. The difference between measurements and calculations on the Duty Cycle gives the result under 1%. This difference also occurs due to the rounding of the ICR and OCR values, but at a frequency of 20 kHz and a 25% Duty Cycle where the ICR value is 599 and OCR is 116 resulting in the minimum difference in frequency and Duty Cycle. From the experiments that have been carried out, the design of the PWM generator based on the AVR ATmega microcontroller has been successfully realized
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Balubaid, Mohammed, Osman Taylan, Mustafa Tahsin Yilmaz, Ehsan Eftekhari-Zadeh, Ehsan Nazemi, and Mohammed Alamoudi. "Central Nervous System: Overall Considerations Based on Hardware Realization of Digital Spiking Silicon Neurons (DSSNs) and Synaptic Coupling." Mathematics 10, no. 6 (2022): 882. http://dx.doi.org/10.3390/math10060882.
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The Central Nervous System (CNS) is the part of the nervous system including the brain and spinal cord. The CNS is so named because the brain integrates the received information and influences the activity of different sections of the bodies. The basic elements of this important organ are: neurons, synapses, and glias. Neuronal modeling approach and hardware realization design for the nervous system of the brain is an important issue in the case of reproducing the same biological neuronal behaviors. This work applies a quadratic-based modeling called Digital Spiking Silicon Neuron (DSSN) to propose a modified version of the neuronal model which is capable of imitating the basic behaviors of the original model. The proposed neuron is modeled based on the primary hyperbolic functions, which can be realized in high correlation state with the main model (original one). Really, if the high-cost terms of the original model, and its functions were removed, a low-error and high-performance (in case of frequency and speed-up) new model will be extracted compared to the original model. For testing and validating the new model in hardware state, Xilinx Spartan-3 FPGA board has been considered and used. Hardware results show the high-degree of similarity between the original and proposed models (in terms of neuronal behaviors) and also higher frequency and low-cost condition have been achieved. The implementation results show that the overall saving is more than other papers and also the original model. Moreover, frequency of the proposed neuronal model is about 168 MHz, which is significantly higher than the original model frequency, 63 MHz.
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Deeg, Florian, Xiangyuan Wu, and Sebastian M. Sattler. "Self-locking Domino Logic Pipelined Controller for RISC-V in FPGA." Athens Journal of Τechnology & Engineering 11, no. 3 (2024): 201–18. http://dx.doi.org/10.30958/ajte.11-3-2.
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This paper proposes an asynchronous RISC-V CPU design based on self-locking domino logic. The asynchronous approach offers advantages over traditional synchronous designs, including improved performance, lower power consumption, and greater modularity. The paper details the design and implementation of the asynchronous control unit using domino logic on an FPGA development board. The control unit is designed for a Turing-complete 32-bit RISC-V architecture. A significant aspect of the design is the self-locking mechanism, which ensures that the circuit only unlocks after all processing stages have been completed. This eliminates the need for a global clock and simplifies hazard-free operation. Furthermore, the paper discusses the potential for parallelizing the ALU using domino logic to improve performance further. The implementation of the asynchronous CPU has been analyzed in terms of power, performance, and area using the Vivado Design Suite. The power analysis indicates that the asynchronous processor consumes considerably less power in the clock network compared to its synchronous counterpart, thereby underscoring its energy efficiency. A performance analysis using the SPECint2000 benchmark suite demonstrates a 10% increase in performance, while only using slightly more area. These findings illustrate the asynchronous processor’s potential for performance-critical applications while maintaining energy and area efficiency.