Relevant bibliographies by topics / FPGA - System-on-Chip

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'FPGA - System-on-Chip'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "FPGA - System-on-Chip"

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SUNITHA A, SUNITHA A., and RAGHU MC RAGHU MC. "Implementation of Can Bus Based System -on-Chip on Altera FPGA." International Journal of Scientific Research 3, no. 5 (June 1, 2012): 268–70. http://dx.doi.org/10.15373/22778179/may2014/82.

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Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 485. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp485-491.

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<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>
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Samsonov, Alexander N., and Khristina V. Samoilova. "High speed video recording system on a chip for detonation jet engine testing." MATEC Web of Conferences 158 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201815801028.

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This article describes system on a chip development for high speed video recording purposes. Current research was started due to difficulties in selection of FPGAs and CPUs which include wide bandwidth, high speed and high number of multipliers for real time signal analysis implementation. Current trend of high density silicon device integration will result soon in a hybrid sensor-controller-memory circuit packed in a single chip. This research was the first step in a series of experiments in manufacturing of hybrid devices. The current task is high level syntheses of high speed logic and CPU core in an FPGA. The work resulted in FPGA-based prototype implementation and examination.
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Baklouti, M., Ph Marquet, J. L. Dekeyser, and M. Abid. "FPGA-based many-core System-on-Chip design." Microprocessors and Microsystems 39, no. 4-5 (June 2015): 302–12. http://dx.doi.org/10.1016/j.micpro.2015.03.007.

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Yu, Bing, Tian Hong Zhang, and Dong Dong Liu. "Low Cost AFDX End System Based on System on a Programmable Chip." Applied Mechanics and Materials 29-32 (August 2010): 2308–11. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.2308.

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AFDX (Avionics Full DupleX Switched Ethernet, ARINC 664) utilized in Airbus A380 and Boeing 787 represents a major upgrade in both bandwidth and capability; however some legacy systems are difficult to connect into the AFDX bus smoothly. A low cost AFDX end system based on SOPC (System On a Programmable Chip) is presented. A Xilinx Spartan 3AN FPGA is employed to build the whole system; and then a dedicated reduced Ethernet MAC controller for AFDX end system is designed; a MC8051 open core microcontroller is employed as the system controller and protocol processing unit. The whole design costs small FPGA resources and the experiments show that the designed AFDX end system works robustly and correctly.
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Zhu, Jun Chao, Yong Chen Li, Ying Kui Jiao, and Zhi Jun Ma. "Image Acquisition System Design of Camera Based on FPGA." Applied Mechanics and Materials 668-669 (October 2014): 836–39. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.836.

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It designs an image acquisition system of the camera based on FPGA. It uses a CMOS image sensor as the sensitive chip and controls the timing of image collection by designing the FPGA. FPGA transfers captured image into a PC to display. It uses the I2C bus to initiate CMOS sensor. A problem of cross-clock is solved by asynchronous FIFO. By the ping-pong operation based on two SDRAM chips to solve the problem of high speed data cache. The FPGA chip communicates signal data with PC by Ethernet port. The experiment proved that the system is able to collect 2048×1536 resolution images in a speed of 12fps.
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Liu, Wen Qiang. "Design of Fiber Data Transmission System Based on FPGA." Applied Mechanics and Materials 687-691 (November 2014): 3207–11. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3207.

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Optical fiber data transmission system has advantages of long-distance transmission, low error rate, high speed data transmission, using FPGA chip NIOSII embedded processor and on chip peripheral constitute the core components, without changing the basic framework of the system, can be upgraded and functional changes to the FPGA internal hardware and software, improved design flexibility, reduced the development cost.
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Xu, Yubao. "FPGA Alarm System Based on Multi Temperature Sensor." International Journal of Online Engineering (iJOE) 13, no. 05 (May 14, 2017): 109. http://dx.doi.org/10.3991/ijoe.v13i05.7053.

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The purpose of this study is to achieve real-time acquisition and monitoring of temperature in large-scale industrial or agricultural production scene, and timely detect abnormal temperature. FPGA chip, multi temperature sensor and alarm control module three parts consist of FPGA alarm system obtained based on multi temperature sensor. Multi temperature sensor is used for the acquisition of relevant temperature signal in the production site, and the transmission of the collected data through the way of digital signal chip to the FPGA chip for further processing. The FPGA chip is responsible for the parameter setting, the temperature signal acquisition and the threshold comparison and so on, and according to the data processing result, it can send out the normal response control signal to the alarm module. The alarm module contains the pre-warning lights and the alarm device that it can receive the control signal and realize alarm response. The results showed that the test in planting flowers in greenhouse showed that the system is sensitive in response and small in error of temperature acquisition, in accordance with the requirements for use. As a result, the system can be widely used in the temperature monitoring in the production scene, suitable for being promoted in a variety of occasions needing for monitoring the temperature.
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Shimizu, Kenta. "FPGA AND SYSTEM ON CHIP EDUCATION FOR EMBEDDED ENGINEER." International Journal of E-Learning and Educational Technologies in the Digital Media 1, no. 2 (2015): 68–80. http://dx.doi.org/10.17781/p001557.

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Nascimento, Jose M. P., Mario P. Vestias, and Gabriel Martin. "Hyperspectral Compressive Sensing With a System-On-Chip FPGA." IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing 13 (2020): 3701–10. http://dx.doi.org/10.1109/jstars.2020.2996679.

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Dissertations / Theses on the topic "FPGA - System-on-Chip"

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Namork, Magnus Krokum. "Network on Chip for FPGA : Development of a test system for Network on Chip." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13654.

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Testing and verification of digital systems is an essential part of product develop-ment. The Network on Chip(NoC), as a new paradigm within interconnections;has a specific need for testing. This is to determine how performance and prop-erties of the NoC are compared to the requirements of different systems such asprocessors or media applications.A NoC has been developed within the AHEAD project to form a basis for areconfigurable platform used in the AHEAD system. This report gives an outlineof the project to develop testing and benchmarking systems for a NoC. The specificwork has been regarding the development of a generic module connected to theNoC and capability of testing the NoCs’ properties. The test system was initiatedby Ivar Ersland in 2009 and developed further by Andreas Hepsø, and MagnusNamork in the fall of 2010. The functionality and systems that are implementedare the following:• Fully functional Hardware/Software interface which de&#64257;nes communicationbetween NoC the user• Reactive system which responds to interaction based on package information• MPEG example system that mimics an MPEG data stream• Software reconfiguration of the traffic tables by sending specific packages tothe system• Cell processor example application to test simple computation and commu-nicating modules on the networkThe systems have been tested successfully, verified and implemented on a XilinxSpartan FPGA. It has also been developed a software system written in C to read and interpret data from the Network in on-chip tests. In total these imple-mentations have been the foundation of building a benchmarking platform for theNoC.
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Ljungberg, Jan. "SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor." Thesis, Tekniska Högskolan, Högskolan i Jönköping, JTH, Data- och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263.

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In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results.
I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.
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Bretz, Daniel. "Digitales Diktiergerät als System-on-a-Chip mit FPGA-Evaluierungsboard." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9033538.

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Yabarrena, Jean Mimar Santa Cruz. "Tecnologias system on chip e CAN em sistemas de controle distribuído." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/18/18149/tde-31072006-203757/.

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Sistemas de controle precisam trabalhar com restrições temporais rigorosas para garantir seu correto funcionamento, sendo por isso considerados sistemas de tempo-real. Quando tais sistemas são distribuídos, as redes de sensores, atuadores e controladores estão interligados em geral, por redes de campo. Nesse contexto, as redes de campo desempenham um papel extremamente importante no comportamento global do sistema. O presente trabalho de pesquisa apresenta a descrição do processo de desenvolvimento de um system on-chip (SoC) para um sistema de controle. Diferentemente das abordagens clássicas, o trabalho está focado em implementar o sistema baseado em um paradigma diferenciado, baseado em lógica reprogramável. Apresenta-se o projeto e construção dos IP cores necessários para controlar um motor DC, utilizando o barramento control area network (CAN) para obter uma plataforma distribuída. A arquitetura on chip utilizada está baseada na especificação CoreConnect da IBM. São expostos, ainda, trabalhos de simulação tanto dos componentes isolados, como do sistema integrado, de forma a realizar uma comparação qualitativa do processo de desenvolvimento
Control systems require strict time constraints to work properly, being therefore considered real-time systems. When such systems are distributed, controllers, sensors, and actuators are generally interconnected by fieldbuses. In this context the fieldbuses play an important role in the system global behavior. This research presents the description of the development process of a system-on-chip SoC. Differentiated from the classical approaches, this work focus the implementation of a reprogrammable logic based system. This work explain the necessary IP cores implementation, allowing a DC motor control, using a control area network (CAN) bus to reach a distributed platform. The on-chip architecture used is based on the IBM CoreConnect specification. Moreover it shows isolated components and integral system simulations, in such a way to obtain a qualitative comparison of development processes
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Zhou, Yuteng. "Computer Vision System-On-Chip Designs for Intelligent Vehicles." Digital WPI, 2018. https://digitalcommons.wpi.edu/etd-dissertations/162.

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Intelligent vehicle technologies are growing rapidly that can enhance road safety, improve transport efficiency, and aid driver operations through sensors and intelligence. Advanced driver assistance system (ADAS) is a common platform of intelligent vehicle technologies. Many sensors like LiDAR, radar, cameras have been deployed on intelligent vehicles. Among these sensors, optical cameras are most widely used due to their low costs and easy installation. However, most computer vision algorithms are complicated and computationally slow, making them difficult to be deployed on power constraint systems. This dissertation investigates several mainstream ADAS applications, and proposes corresponding efficient digital circuits implementations for these applications. This dissertation presents three ways of software / hardware algorithm division for three ADAS applications: lane detection, traffic sign classification, and traffic light detection. Using FPGA to offload critical parts of the algorithm, the entire computer vision system is able to run in real time while maintaining a low power consumption and a high detection rate. Catching up with the advent of deep learning in the field of computer vision, we also present two deep learning based hardware implementations on application specific integrated circuits (ASIC) to achieve even lower power consumption and higher accuracy. The real time lane detection system is implemented on Xilinx Zynq platform, which has a dual core ARM processor and FPGA fabric. The Xilinx Zynq platform integrates the software programmability of an ARM processor with the hardware programmability of an FPGA. For the lane detection task, the FPGA handles the majority of the task: region-of-interest extraction, edge detection, image binarization, and hough transform. After then, the ARM processor takes in hough transform results and highlights lanes using the hough peaks algorithm. The entire system is able to process 1080P video stream at a constant speed of 69.4 frames per second, realizing real time capability. An efficient system-on-chip (SOC) design which classifies up to 48 traffic signs in real time is presented in this dissertation. The traditional histogram of oriented gradients (HoG) and support vector machine (SVM) are proven to be very effective on traffic sign classification with an average accuracy rate of 93.77%. For traffic sign classification, the biggest challenge comes from the low execution efficiency of the HoG on embedded processors. By dividing the HoG algorithm into three fully pipelined stages, as well as leveraging extra on-chip memory to store intermediate results, we successfully achieved a throughput of 115.7 frames per second at 1080P resolution. The proposed generic HoG hardware implementation could also be used as an individual IP core by other computer vision systems. A real time traffic signal detection system is implemented to present an efficient hardware implementation of the traditional grass-fire blob detection. The traditional grass-fire blob detection method iterates the input image multiple times to calculate connected blobs. In digital circuits, five extra on-chip block memories are utilized to save intermediate results. By using additional memories, all connected blob information could be obtained through one-pass image traverse. The proposed hardware friendly blob detection can run at 72.4 frames per second with 1080P video input. Applying HoG + SVM as feature extractor and classifier, 92.11% recall rate and 99.29% precision rate are obtained on red lights, and 94.44% recall rate and 98.27% precision rate on green lights. Nowadays, convolutional neural network (CNN) is revolutionizing computer vision due to learnable layer by layer feature extraction. However, when coming into inference, CNNs are usually slow to train and slow to execute. In this dissertation, we studied the implementation of principal component analysis based network (PCANet), which strikes a balance between algorithm robustness and computational complexity. Compared to a regular CNN, the PCANet only needs one iteration training, and typically at most has a few tens convolutions on a single layer. Compared to hand-crafted features extraction methods, the PCANet algorithm well reflects the variance in the training dataset and can better adapt to difficult conditions. The PCANet algorithm achieves accuracy rates of 96.8% and 93.1% on road marking detection and traffic light detection, respectively. Implementing in Synopsys 32nm process technology, the proposed chip can classify 724,743 32-by-32 image candidates in one second, with only 0.5 watt power consumption. In this dissertation, binary neural network (BNN) is adopted as a potential detector for intelligent vehicles. The BNN constrains all activations and weights to be +1 or -1. Compared to a CNN with the same network configuration, the BNN achieves 50 times better resource usage with only 1% - 2% accuracy loss. Taking car detection and pedestrian detection as examples, the BNN achieves an average accuracy rate of over 95%. Furthermore, a BNN accelerator implemented in Synopsys 32nm process technology is presented in our work. The elastic architecture of the BNN accelerator makes it able to process any number of convolutional layers with high throughput. The BNN accelerator only consumes 0.6 watt and doesn't rely on external memory for storage.
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Reiche, Myrgård Martin. "Acceleration of deep convolutional neural networks on multiprocessor system-on-chip." Thesis, Uppsala universitet, Avdelningen för datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-385904.

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In this master thesis some of the most promising existing frameworks and implementations of deep convolutional neural networks on multiprocessor system-on-chips (MPSoCs) are researched and evaluated. The thesis’ starting point was a previousthesis which evaluated possible deep learning models and frameworks for object detection on infra-red images conducted in the spring of 2018. In order to fit an existing deep convolutional neural network (DCNN) on a Multiple-Processor-System on Chip it needs modifications. Most DCNNs are trained on Graphic processing units (GPUs) with a bit width of 32 bit. This is not optimal for a platform with hard memory constraints such as the MPSoC which means it needs to be shortened. The optimal bit width depends on the network structure and requirements in terms of throughput and accuracy although most of the currently available object detection networks drop significantly when reduced below 6 bits width. After reducing the bit width, the network needs to be quantized and pruned for better memory usage. After quantization it can be implemented using one of many existing frameworks. This thesis focuses on Xilinx CHaiDNN and DNNWeaver V2 though it touches a little on revision, HLS4ML and DNNWeaver V1 as well. In conclusion the implementation of two network models on Xilinx Zynq UltraScale+ ZCU102 using CHaiDNN were evaluated. Conversion of existing network were done and quantization tested though not fully working. The results were a two to six times more power efficient implementation in comparison to GPU inference.
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Bayona, Adam Robert. "System on a chip – Soft IP from the FPGA-vendor or an OpenCore-processor?" Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9507.

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Two different processors from two FPGA vendors and an OpenCore-processor have been investigated. For this work two different boards were used, the first was the Cyclone II FPGA Altera Board, in which the Nios II Altera microprocessor and the free processor Leon2 were tested. The second board was a SUZAKU-S board, in which the Microblaze Xilinx microprocessor and the free processor Leon2 were tested. We performed two different benchmarks in these boards, the Dhrystone and the Whetstone, to compare the different velocities between the free and not free processors. Also the documentation and ease of use of the processors is considered.

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Druyer, Rémy. "Réseau sur puce sécurisé pour applications cryptographiques sur FPGA." Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS023/document.

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Que ce soit au travers des smartphones, des consoles de jeux portables ou bientôt des supercalculateurs, les systèmes sur puce (System-on-chip (SoC)) ont vu leur utilisation largement se répandre durant ces deux dernières décennies. Ce phénomène s’explique notamment par leur faible consommation de puissance au regard des performances qu’ils sont capables de délivrer, et du large panel de fonctions qu’ils peuvent intégrer. Les SoC s’améliorant de jour en jour, ils requièrent de la part des systèmes d’interconnexions qui supportent leurs communications, des performances de plus en plus élevées. Pour répondre à cette problématique les réseaux sur puce (Network-on-Chip (NoC)) ont fait leur apparition.En plus des ASIC, les circuit reconfigurables FPGA sont un des choix possibles lors de la réalisation d’un SoC. Notre première contribution a donc été de réaliser et d’étudier les performances du portage du réseau sur puce générique Hermes initialement conçu pour ASIC, sur circuit reconfigurable. Cela nous a permis de confirmer que l’architecture du système d’interconnexions doit être adaptée à celle du circuit pour pouvoir atteindre les meilleures performances possibles. Par conséquent, notre deuxième contribution a été la conception de l’architecture de TrustNoC, un réseau sur puce optimisé pour FPGA à hautes performances en latence, en fréquence de fonctionnement, et en quantité de ressources logiques occupées.Un autre aspect primordial qui concerne les systèmes sur puce, et plus généralement de tous les systèmes numériques est la sécurité. Notre dernière principale contribution a été d’étudier les menaces qui s’exercent sur les SoC durant toutes les phases de leur vie, puis de développer à partir d’un modèle de menaces, des mécanismes matériels de sécurité permettant de lutter contre des détournements d’IP, et des attaques logicielles. Nous avons également veillé à limiter au maximum le surcoût qu’engendre les mécanismes de sécurité sur les performances sur réseau sur puce
Whether through smartphones, portable game consoles, or high performances computing, Systems-on-Chip (SoC) have seen their use widely spread over the last two decades. This can be explained by the low power consumption of these circuits with the regard of the performances they are able to deliver, and the numerous function they can integrate. Since SoC are improving every day, they require better performances from interconnects that support their communications. In order to address this issue Network-on-Chip have emerged.In addition to ASICs, FPGA circuits are one of the possible choices when conceiving a SoC. Our first contribution was therefore to perform and study the performance of Hermes NoC initially designed for ASIC, on reconfigurable circuit. This allowed us to confirm that the architecture of the interconnection system must be adapted to that of the circuit in order to achieve the best possible performances. Thus, our second contribution was to design TrustNoC, an optimized NoC for FPGA platform, with low latency, high operating frequency, and a moderate quantity of logical resources required for implementation.Security is also a primordial aspect of systems-on-chip, and more generally, of all digital systems. Our latest contribution was to study the threats that target SoCs during all their life cycle, then to develop and integrate hardware security mechanisms to TrustNoC in order to counter IP hijacking, and software attacks. During the design of security mechanisms, we tried to limit as much as possible the overhead on NoC performances
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Powell, Andrew Andre. "Performance of the Xilinx Zynq System-on-Chip Interconnect with Asymmetric Multiprocessing." Master's thesis, Temple University Libraries, 2014. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/306468.

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Electrical and Computer Engineering
M.S.E.E.
For many applications, embedded designers need to construct systems that facilitate real-time constraints and thus require complete information on a processor's performance under specified parameters. An important and limiting factor in any processor's performance is how quickly components are able to intercommunicate over the system's bus. However, another important constraint, specific to real-time systems, is knowing precisely how long the data communication will require. A highly integrated system composed of multiple processing cores, referred to as a System-on-Chip (SoC) device, contains a bus known as an on-chip interconnect. Specifically, this thesis research presents how rapidly the AMBA AXI on-chip interconnect of Xilinx Zynq-7000 Extensible Processing Platform (EPP) SoC device functions by measuring the time required to communicate between memory and the two major device components of the SoC device. The memory is either internal or external. The two major device components include the processing system (PS) and programmable logic (PL). The PS contains a dual-core ARM Cortex-A9 processor that executes FreeRTOS in Asymmetric Multiprocessing. Communication between the PL and memory is through the PS-PL interfaces; the Accelerator Coherency Port AXI interface, High Performance AXI interface, and the General Purpose AXI interface. The benchmarking is performed under several, changing parameters; such as the payload size and the number of devices executing in the PL. The embedded design is implemented with Xilinx Vivado Design Suite, which includes the Vivado IDE and the SDK, and is executed on the Avnet ZedBoard and Xilinx ZC702 Evaluation Kit.
Temple University--Theses
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Vyas, Dhaval N. "FPGA-based hardware accelerator design for performance improvement of a system-on-a-chip application." Diss., Online access via UMI:, 2005.

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Books on the topic "FPGA - System-on-Chip"

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Kamat, Rajanish K. Unleash the System On Chip using FPGAs and Handel C. Dordrecht: Springer Netherlands, 2009.

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Kamat, Rajanish K., Santosh A. Shinde, and Vinod G. Shelake. Unleash the System On Chip using FPGAs and Handel C. Kamat Rajanish K Shinde Santosh A Shelake Vinod G, 2010.

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Processor Design: System-On-Chip Computing for ASICs and FPGAs. Springer, 2007.

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Unleash the System On Chip using FPGAs and Handel C. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-1-4020-9362-3.

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Book chapters on the topic "FPGA - System-on-Chip"

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Snyder, Brian L. "Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and DesignBook." In System on Chip Design Languages, 129–37. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6674-5_11.

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Schwarz, Bernd. "Ein FPGA-basiertes System-on-Chip in der Echtzeitbildverarbeitung." In Eingebettete Systeme, 131–40. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-16189-6_14.

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Muehlberghuber, Michael, Christoph Keller, Frank K. Gürkaynak, and Norbert Felber. "FPGA-Based High-Speed Authenticated Encryption System." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 1–20. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_1.

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Majumder, Atanu, Sangeet Saha, and Amlan Chakrabarti. "Task Allocation Strategies for FPGA Based Heterogeneous System on Chip." In Computer Information Systems and Industrial Management, 341–53. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59105-6_29.

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Tahghighi, Mohammad, Sharad Sinha, and Wei Zhang. "Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA." In Lecture Notes in Computer Science, 159–70. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30481-6_13.

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Anandaraj, S. P., R. Naveen Kumar, S. Ravi, and S. S. V. N. Sharma. "Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems through On-Chip System Evolution." In Communication and Networking, 459–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-17604-3_53.

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Airoldi, Roberto, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, and Jari Nurmi. "Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management." In Lecture Notes in Computer Science, 88–97. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03138-0_10.

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Castano-Londono, Luis, Cristian Alzate Anzola, David Marquez-Viloria, Guillermo Gallo, and Gustavo Osorio. "Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool." In Communications in Computer and Information Science, 52–63. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-31019-6_5.

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Pellauer, Michael, Michael Adler, Angshuman Parashar, and Joel Emer. "Accelerating Simulation with FPGAs." In Processor and System-on-Chip Simulation, 107–26. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6175-4_7.

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Kamat, Rajanish K., Santosh A. Shinde, Pawan K. Gaikwad, and Hansraj Guhilot. "Development of FPGA Based Network on Chip for Circumventing Spam." In Harnessing VLSI System Design with EDA Tools, 15–50. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1864-7_2.

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Conference papers on the topic "FPGA - System-on-Chip"

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Santti, Tero, Joonas Tyystjarvi, and Juha Plosila. "FPGA Prototype of the REALJava Co-Processor." In 2007 International Symposium on System-on-Chip. IEEE, 2007. http://dx.doi.org/10.1109/issoc.2007.4427434.

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Kariniemi, Heikki, and Jari Nurmi. "Micronmesh for fault-tolerant GALS Multiprocessors on FPGA." In 2008 International Symposium on System-on-Chip (SOC). IEEE, 2008. http://dx.doi.org/10.1109/issoc.2008.4694870.

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Fridman, Alexander, and Serguey Semenov. "System-on-Chip FPGA-based GNSS receiver." In 2013 11th East-West Design and Test Symposium (EWDTS). IEEE, 2013. http://dx.doi.org/10.1109/ewdts.2013.6673192.

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Muralikrishna, B., G. L. Madhumati, Habibulla Khan, and K. Gnana Deepika. "Reconfigurable System-on-Chip design using FPGA." In 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2014. http://dx.doi.org/10.1109/icdcsyst.2014.6926215.

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Bhattacharjee, Debjyoti, Anupam Chattopadhyay, and Ricardo Jack Liwongan. "Accelerating Binary-Matrix Multiplication on FPGA." In 2019 32nd IEEE International System-on-Chip Conference (SOCC). IEEE, 2019. http://dx.doi.org/10.1109/socc46988.2019.1570544215.

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Brunelli, C., F. Garzia, J. Nurmi, C. Mucci, F. Campi, and D. Rossi. "A FPGA Implementation of An Open-Source Floating-Point Computation System." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595636.

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Caffarena, Gabriel, Juan Lopez, Carlos Carreras, and Octavio Nieto-Taladriz. "Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources." In 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.321978.

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Gu, Chongyan, Yijun Cui, Neil Hanley, and Maire O'Neill. "Novel lightweight FF-APUF design for FPGA." In 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905439.

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Jastrzebski, R., R. Pollanen, and O. Pyrhonen. "Analysis of System Architecture of FPGA-based Embedded Controller for Magnetically Suspended Rotor." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595661.

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Innamaa, A. "FPGA Prototyping: Untapping Potential within the Multimillion-Gate System-on-Chip Design Space." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595662.

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