Relevant bibliographies by topics / Fractional Spur

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Fractional Spur'

Author: Grafiati
Published: 4 June 2021
Last updated: 14 February 2022

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Journal articles on the topic "Fractional Spur"

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Boon, C. C., M. A. Do, K. S. Yeo, and J. G. Ma. "New spur reduction fractional-N frequency divider." Microwave and Optical Technology Letters 33, no. 5 (2002): 355–58. http://dx.doi.org/10.1002/mop.10320.

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Biswas, Debdut, and Tarun Kanti Bhattacharyya. "Spur reduction architecture for multiphase fractional PLLs." IET Circuits, Devices & Systems 13, no. 8 (2019): 1169–80. http://dx.doi.org/10.1049/iet-cds.2019.0041.

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Huang, Shui-long, and Hai-ying Zhang. "A fractional spur suppression technique in the fractional-N frequency synthesizer." Analog Integrated Circuits and Signal Processing 66, no. 3 (2010): 455–58. http://dx.doi.org/10.1007/s10470-010-9565-6.

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Liu, Ming Qin, and Yu Ling Liu. "Physical Fractional Step Method for Solution of 2D Water Flow around a Spur Dike." Advanced Materials Research 374-377 (October 2011): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/amr.374-377.1085.

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A numerical model for simulating of 2D flow around a spur dike was presented by using the physical fractional-step method. The water governing equations were separated into three parts. The first is a convective problem; the second is a diffusive problem; and the third is a source term. The advantage of this method is that in the convective-diffusion equation a more reasonable scheme for the convective and diffusive operator is adopted respectively. Numerical simulation for 2D flow around a spur dike was implemented. The comparisons with other numerical solutions show that the proposed method can be capable of dealing with 2D spur-dike flows.
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Gonzalez-Diaz, Victor R., Miguel A. Garcia-Andrade, Guillermo Espinosa F. V., and Franco Maloberti. "Optimized reduction of spur tones in fractional frequency synthesizers." Analog Integrated Circuits and Signal Processing 65, no. 2 (2010): 245–51. http://dx.doi.org/10.1007/s10470-010-9473-9.

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Hou, Jingyu, Shaopu Yang, Qiang Li, and Yongqiang Liu. "Nonlinear dynamic analysis of spur gear system based on fractional-order calculus." Modern Physics Letters B 34, no. 36 (2020): 2050420. http://dx.doi.org/10.1142/s0217984920504205.

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In this paper, nonlinear dynamic model of spur gear pairs with fractional-order damping under the condition of time-varying stiffness, backlash and static transmission error is established. The general formula of fractional-order damping term is derived by using the incremental harmonic balance method (IHBM), and the approximate analytical solution of the system is obtained by use of the iterative formula. The correctness of the results is verified by comparing with the numerical solutions in the existing literature. The effects of mesh stiffness, internal excitation amplitude and fractional order on the dynamic behavior of the system are analyzed. The results show that changing the fractional order can effectively control the resonance position and amplitude in the meshing process. Both the mesh stiffness and internal excitation can control the collision state and the stability.
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Pamarti, S., and S. Delshadpour. "A Spur Elimination Technique for Phase Interpolation-Based Fractional-$N$ PLLs." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 6 (2008): 1639–47. http://dx.doi.org/10.1109/tcsi.2008.916571.

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Jordan, D. A., M. R. Inggs, and M. Y. Abdul Gaffar. "Integer boundary spur considerations for fractional‐N PLL based FMCW radar." Electronics Letters 56, no. 14 (2020): 729–32. http://dx.doi.org/10.1049/el.2020.0764.

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Ho, Cheng-Ru, and Mike Shuo-Wei Chen. "A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <–73 dBc Fractional Spur and <–110 dBc Reference Spur in 65 nm CMOS." IEEE Journal of Solid-State Circuits 51, no. 12 (2016): 3216–30. http://dx.doi.org/10.1109/jssc.2016.2596770.

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He, Dan, Fujian Lu, and Dezhi Wang. "Current pulse shaping technique for low spur fractional‐N phase‐locked loop." Electronics Letters 56, no. 5 (2020): 231–32. http://dx.doi.org/10.1049/el.2019.3492.

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Dissertations / Theses on the topic "Fractional Spur"

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Imran, Saeed Sohail. "Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80886.

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With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.
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Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.

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Dailey, Shane Robert. "Geochemistry of the Fluorine- and Beryllium-Rich Spor Mountain Rhyolite, Western Utah." BYU ScholarsArchive, 2016. https://scholarsarchive.byu.edu/etd/6258.

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The Miocene rhyolites of the Spor Mountain Formation hosts the world's largest beryllium deposit which produced 85% of the world's beryllium in 2010. The fresh lava is extremely enriched in Be (up to 75 ppm in matrix glass). We have examined the rhyolite to understand the Be enrichment. The Spor Mountain rhyolite contains ~40% quartz, ~40% sanidine, ~10% biotite, and ~10% plagioclase, along with accessory fluorite, columbite, euxenite, fergusonite, monazite, thorite, and zircon. Two types of rhyolite erupted within the Spor Mountain Formation, a less evolved magma (1150 ppm Rb, 42 ppm Be, 0.68 wt% F in matrix glass) and an evolved magma (1710 ppm Rb, 75 ppm Be, 1.56 wt% F in matrix glass). Eruption temperatures estimated using zircon saturation, feldspar-liquid, two feldspar, and Ti-in-quartz geothermometers converge on 718 °C for the less evolved magma and 682 °C for the evolved magma. Using the Ti-in-Qz equation of Huang and Audetat (2012), the pressure of the Spor Mountain rhyolite system is estimated to be around 2 kbar at 700°C. Water content of the rhyolite melt was less than <5 wt%, based on the presence of all four major mineral phases at 700°C and the magma was water undersaturated (Webster et al., 1987). Viscosity of the rhyolite was about 6.2 log Pa·s for the less evolved rhyolite and 5.8 log Pa·s for the evolved rhyolite. Magma viscosities calculated using the Einstein-Roscoe question suggest the evolved magma has a slightly higher viscosity than the less evolved magma (7.0 log Pa·s in the evolved magma vs 6.7 log Pa·s in the less evolved magma) because of higher phenocryst content. Fluorine lowered the melt viscosity, though not by a significant amount (less than 0.5 log units at 1.7 wt% F). Partition coefficients for 32 elements have been calculated for biotite, for 21 elements for sanidine and plagioclase, and for 6 elements for quartz, using data acquired by laser ablation inductively coupled plasma mass spectrometry. Partition coefficients for feldspars in the Spor Mountain rhyolite are generally higher than other silicic magmas, and lower for biotite. Beryllium is one of the most incompatible trace elements in the Spor Mountain rhyolite, with a bulk partition coefficient <0.1. Volatile content of the melt (specifically F), melt composition, and the low temperature of crystallization act as the major controls of trace element partitioning. Trace element models using these partition coefficients suggests that crystal fractionation is the dominant magmatic enrichment process within the rhyolite, requiring ~45% crystallization (f = 55%) of the observed phenocrysts to get compositions from the less evolved to evolved rhyolite. Accumulation of batches of melt formed by different degrees of partial melting cannot explain the great depletion of compatible elements.
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Jian, Heng-Yu. "A multi-band fractional-N frequency synthesizer using binary-weighted digital/analog differentiator and offset-frequency delta-sigma modulator for noise and spurs cancellation." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=1835512521&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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Pu, Xiao. "A bandwidth-enhanced fractional-N PLL through reference multiplication." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-4149.

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The loop bandwidth of a fractional-N PLL is a desirable parameter for many applications. A wide bandwidth allows a significant attenuation of phase noise arising from the VCO. A good VCO typically requires a high Q LC oscillator. It is difficult to build an on-chip inductor with a high Q factor. In addition, a good VCO also requires a lot of power. Both these design challenges are relaxed with a wide loop bandwidth PLL. However a wide loop bandwidth reduces the effective oversampling ratio (OSR) between the update rate and loop bandwidth and makes quantization noise from the ΔΣ modulator a much bigger noise contributor. A wide band loop also makes the noise and linearity performance of the phase detector more significant. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this dissertation we present a new PLL architecture for bandwidth extension or phase noise reduction. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single cycle of a sinusoidal reference and used for phase updates, effectively forming a reference frequency multiplier. A higher update rate enables a higher OSR which allows for better quantization noise shaping and makes a wideband fractional-N PLL possible. However since the proposed reference multiplier utilizes the magnitude information from a sinusoidal reference to obtain phases, the derived new edges tend to cluster around the zero-crossings and form an irregular clock. This presents a challenge in lock acquisition. We have demonstrated for the first time that an irregular clock can be used to lock a PLL. The irregularity of the reference clock is taken into account in the divider by adding a cyclic divide pattern along with the ΔΣ control bits, this forces the loop to locally match the incoming patterns and achieve lock. Theoretically this new architecture allows for a 6x increase in loop BW or a 24dB improvement in phase noise. One potential issue associated with the proposed approach is the degraded spurious performance due to PVT variations, which lead to unintended mismatches between the irregular period and the divider pattern. A calibration scheme was invented to overcome this issue. In simulation, the calibration scheme was shown to lower the spurs down to inherent spurs level, of which the total energy is much less than the integrated phase noise. A test chip for proof of concept is presented and measurements are carefully analyzed.
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Chiu, Shih-Wen, and 邱仕文. "A 1.2V 5.1GHz BIST Triple-State Very Fast Locking with Fractional-Spur-Eliminated PLL." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/68058924044739688950.

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Yang, Jia-lun, and 楊佳倫. "A 1-V 2.4-GHz Fractional-N Frequency Synthesizer Chip Design with Reference Spur Reduction Techniques." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/yty4mt.

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碩士
國立臺灣科技大學
電子工程系
102
In recent year, with the rapid growing of the wireless communication system, many of PLL architectures are created. Normally, the loop filter of a conventional PLL are using continuous-time passive loop filter, it needs a large capacitance to meet system requirements. And the control node of the VCO is directly connected to the loop filter that will introduce ripples. Usually deals with a tradeoff between the settling time and the magnitude of the reference sideband that appears at the PLL output. The first chip, we introduce a 2.4 GHz fractional-N frequency synthesizer architecture with a reference spur reduction technique. It adopts a sample-hold-reset loop filter to isolate the charge pump output node and the VCO control node, which has a better linearity of PFD and CP. It achieves low spur and low phase noise performance, and save the capacitance area while a narrow loop bandwidth is used. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.21 GHz to 2.52 GHz corresponding to a frequency tuning range of 13.1%, a phase noise of -117.1 dBc/Hz at 1 MHz offset from 2.4 GHz, a reference spur of -65 dBc, a power consumption of 15.2 mW and the with pads chip area is only 1.06 mm2. The second chip, we adopt a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur. The frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage controlled oscillator to reduce the reference spur at the output of the phase-locked loop. The SSCP circuit is also utilized to reduce ripples on the control voltage to achieve low spur level. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.235 GHz to 2.579 GHz corresponding to a frequency tuning range of 14.3%, a phase noise of -113.17 dBc/Hz at 1 MHz offset from 2.41 GHz, a reference spur of -70.4 dBc, a power consumption of 9 mW and the with pads chip area is only 0.695 mm2.
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Chen, Ming-Bin, and 陳銘斌. "A Fractional-N Frequency Synthesizer with a Spur-Eliminated Topology for IEEE 802.11 a/b/g Channels." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/85849504892487680240.

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碩士
中興大學
電機工程學系所
95
In this thesis, the main purpose is to realize a LO signal with multi-channels frequency synthesizer for IEEE 802.11 a/b/g. On the instant, the loop filter in the frequency synthesizer is almost combined with the resisters and the capacitors. But, the VCO’s controlled voltage is produced by loop filter and occurs the effect of ripple. This effect will generate reference spur in the spectra, and affect the performance of transmitter. For this reason, if we displace the resistor in the loop filter, it can suppress the effect of ripple in the VCO’s controlled voltage. And then, the reference spur is decreased. So, we use the fundamental architecture of the no resistor frequency synthesizer to make some improvement in this thesis. In fractional part, phase-compensation fractional PLL is a different kind of true fractional PLL with averaging fractional PLL using D-S modulator architecture. This technique can minimum generating of quantization error which makes fractional spurs. The focus of the technique is how to generate the phase for compensation. The work presents the frequency synthesizer based on PLLs. It divided into two parts of the work. The first one applies the inductive varactor voltage-controlled oscillator and delta-sigma modulator to realize a ripple-suppressed fractional-N frequency synthesizer. The output frequency range is from 4.6GHz to 6.5GHz. It is simulated by TSMC 0.18-um standard CMOS technology and power dissipation is about 75-mW under 1.8-V supply voltage. The chip area is 1.4*1.4mm2. The other one is to realized the spur-eliminated topology base on the last architecture of frequency synthesizer. Taking advantage of multi-phase generated by a ring oscillator, it adopts with a phase generator and a phase selector which generates phase compensation to reduce fractional spur. Because of the high speed operating, the ring oscillator is accepted with dual delayed loop technique. The output frequency range is from 2.3GHz to 2.6GHz. It is fabricated with a 0.18-um standard CMOS technology and power dissipation is about 65-mW under 1.8-V supply voltage. The chip area is 0.815*0.66mm2.
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"Iterative determination of spar lines static equilibrium and improved dynamic modeling by fractional derivatives." Thesis, 2009. http://hdl.handle.net/1911/61843.

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Polyester mooring systems are used as permanent systems of floating production systems and offshore structures. Compared to other mooring systems, polyester has a highly non linear behavior, thus complicating the overall design. Three important parameters affect the polyester rope stiffness; the mean load, the load range, and the frequency of the loading. Ignoring the 'true' stiffness as influenced by these parameters, may lead to underestimate the load induced riser stresses and damage. Procedures for determining mooring line stiffness that is representative of the in service conditions are developed herein. Two stiffness values, the 'static' and 'dynamic', are iteratively calculated from real time data, and are correlated with laboratory tests. Furthermore, note that fractional derivative models have been extensively proposed in literature for accurately capturing frequency dependent behavior of materials. In this context, a modified Newmark algorithm that takes advantage of the Grunwald-Letnikov fractional derivative representation is developed to treat related structural dynamic problems. In addition, a statistical linearization approach is also developed for random vibration treatment of such systems. The modified Newmark Algorithm is used to conduct Monte Carlo studies demonstrating the reliability of the statistical linearization solution.
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Book chapters on the topic "Fractional Spur"

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Zouari, Farouk, and Amina Boubellouta. "Adaptive Neural Control for Unknown Nonlinear Time-Delay Fractional-Order Systems With Input Saturation." In Advanced Synchronization Control and Bifurcation of Chaotic Fractional-Order Systems. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-5418-9.ch003.

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This chapter focuses on the adaptive neural control of a class of uncertain multi-input multi-output (MIMO) nonlinear time-delay non-integer order systems with unmeasured states, unknown control direction, and unknown asymmetric saturation actuator. The design of the controller follows a number of steps. Firstly, based on the semi-group property of fractional order derivative, the system is transformed into a normalized fractional order system by means of a state transformation in order to facilitate the control design. Then, a simple linear state observer is constructed to estimate the unmeasured states of the transformed system. A neural network is incorporated to approximate the unknown nonlinear functions while a Nussbaum function is used to deal with the unknown control direction. In addition, the strictly positive real (SPR) condition, the Razumikhin lemma, the frequency distributed model, and the Lyapunov method are utilized to derive the parameter adaptive laws and to perform the stability proof.
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"A technique for countering the integer boundary spurs in fractional phase-locked loops with VCO." In Emerging Trends in Engineering, Science and Technology for Society, Energy and Environment. CRC Press, 2018. http://dx.doi.org/10.1201/9781351124140-118.

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Haida, Abderrazak Ben, and Philip Hodge. "The formation of cyclic oligomers during step-growth polymerization." In Polymer Chemistry. Oxford University Press, 2004. http://dx.doi.org/10.1093/oso/9780198503095.003.0010.

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Step-growth polymerization is controlled both by the efficiency of the synthetic routes chosen (as indicated in Chapter 4) and by statistical considerations. In particular, the formation of the desired polymer is almost always accompanied by a cyclic oligomer fraction. As the dilution increases, the chances of cyclization also increase, since polymerization is a second-order process involving the reaction between linear species, whereas cyclization, involving the (intramolecular) reaction between the two ends of a linear molecule, is inherently a first-order process. Cyclization is a particular feature of the early stages of a step-growth polymerization (up to extents of reaction of 98–99%), where a proportion of the end groups that react are on the same molecule. Hence, cyclics form. Since the chances of meeting of the end groups decrease rapidly as the distance between them increases, the cyclics are of relatively low molecular weight, that is, they are oligomers. Further reaction leads mainly to linear molecules, although at extremely high conversions the number of end groups is quite small and intramolecular reactions essentially terminate the process, such that it might be expected that all chains ultimately cyclize. Practically though, the levels of conversion necessary to obtain these very large rings are extremely high and difficult to obtain (either by virtue of side reactions, monomer imperfections, or simply the level of viscosity of high molecular weight polymer solutions). What is usually obtained, therefore, is a mixture of cyclics and linear molecules. However, since cyclic oligomers often differ considerably in, for example, solubility compared to their high molar mass linear homologues, separation is often relatively straightforward. The commercial importance of polymers produced by step-growth polymerization gives a particular significance to understanding the nature of such materials. The presence of cyclic oligomers can be detrimental to the polymer properties since their presence could cause problems during processing. For instance, cyclic oligomers of polyethylene terephthalate (PET) tend to migrate to the surface of spun fibres and, under certain conditions, they crystallize to produce a surface ‘bloom’ which interferes with subsequent dyeing. More recently, it is the reverse of cyclization, namely ring-opening polymerization, which has been a particular focus of attention.
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Conference papers on the topic "Fractional Spur"

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Sadatnejad, Najmeh, and Hossein Miar-Naimi. "A new fractional spur modeling in fractional-N frequency synthesizers." In 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2015. http://dx.doi.org/10.1109/ccece.2015.7129332.

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Chen, Peng, XiongChuan Huang, and Robert Bogdan Staszewski. "Fractional spur suppression in all-digital phase-locked loops." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169209.

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Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, and M. Ashburn. "A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation." In 2013 IEEE International Solid-State Circuits Conference (ISSCC 2013). IEEE, 2013. http://dx.doi.org/10.1109/isscc.2013.6487795.

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Ho, Cheng-Ru, and Mike Shuo-Wei Chen. "10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving −73dBc fractional spur and −110dBc Reference Spur in 65nm CMOS." In 2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016. http://dx.doi.org/10.1109/isscc.2016.7417971.

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Can, Basak, Balvinder S. Bisla, Satwik Patnaik, and Anthony Tsangaropoulos. "Novel Fractional Spur Relocation in All Digital Phase Locked Loops." In 2017 IEEE Wireless Communications and Networking Conference (WCNC). IEEE, 2017. http://dx.doi.org/10.1109/wcnc.2017.7925579.

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Wu, Chun-Pang, Hen-Wai Tsao, and Jingshown Wu. "A novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537330.

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Yuan, Zexin, Lei Zhang, and Yan Wang. "A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper." In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021. http://dx.doi.org/10.1109/iscas51556.2021.9401671.

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Zhang, Qiaochu, Shiyu Su, Cheng-Ru Ho, and Mike Shuo-Wei Chen. "29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur." In 2021 IEEE International Solid- State Circuits Conference (ISSCC). IEEE, 2021. http://dx.doi.org/10.1109/isscc42613.2021.9365819.

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Kennedy, Michael Peter, Hongjia Mo, Zhida Li, Guosheng Hu, Paolo Scognamiglio, and Ettore Napoli. "The noise and spur delusion in fractional-N frequency synthesizer design." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169212.

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Kennedy, Michael Peter, Hongjia Mo, and Yann Donnelly. "Phase noise and spur performance limits for fractional-N frequency synthesizers." In 2015 26th Irish Signals and Systems Conference (ISSC). IEEE, 2015. http://dx.doi.org/10.1109/issc.2015.7163783.

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