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Ratcliff, Marcus Dai Foster. "Phase locked loop analysis and design." Auburn, Ala, 2008. http://hdl.handle.net/10415/1452.
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Tang, Yiwu. "Adaptive phase locked loop in multi-standard frequency synthesizers /." The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu1486401895208464.
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Beaudoin, Francis. "Design and implementation of a gigabit-rate optical, receiver and a digital frequency-locked loop for phase-locked loop based applications." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79996.
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The large demand for high-bandwidth communication systems has brought down the cost of optical system components. To be competitive in a crowded market, implementation of the different systems of an optical transceiver on a single chip has become mandatory.<br>CMOS technologies, especially state-of-the-art processes like the 0.18mum CMOS, permit integration of huge amounts of transistors per millimeter square. Furthermore, deep-submicron CMOS processes have similar RF performances to their traditional bipolar equivalent. It is therefore a small footstep to go to congregate high-speed analog circuits with digital cores on a single die.<br>This thesis addresses two of the building blocks found in an optical communication receiver, namely the analog front-end receiver and a digital frequency-acquisition based clock-and-data recovery circuit. The latter reduces the headcount of bulky passive components needed in the implementation of the loop filter by porting the analog loop to the digital domain. This circuit has been successfully fabricated and tested.<br>Finally, an optical front-end, comprising a transimpedance amplifier and a limiting amplifier is proposed and fabricated using a standard 0.18mum CMOS process. The speed of this circuit has been pushed up to 5Gb/s. Different techniques have been employed to increase the effective bandwidth of the input amplifier, namely the use of a constant-k filter.
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Holtzman, Melinda, Bruce Johnson, and Lloyd Lautzenhiser. "A DIGITAL INTEGRATOR FOR AN S-BAND HIGH-SPEED FREQUENCY-HOPPING PHASE-LOCKED LOOP." International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/605595.
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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>Phase-locked loop (PLL) frequency synthesizers used for high-speed data transmission must rapidly
hop and lock to new frequencies. The fundamental problem is that the settling time depends
inversely on the loop bandwidth, and increasing the bandwidth causes unwanted noise interference
and stability problems for the circuit. We demonstrate the feasibility of replacing the analog
integrator in the PLL with a digital integrator. This circuit has advantages of increased hopping
speed, ability to compensate for temperature drift and system stability. PLL lock-in was
demonstrated in a prototype circuit designed and built with both discrete components and with a
programmable logic device.
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Asghar, Malik Summair. "A “Divide-by-Odd Number” Injection-Locked Frequency Divider." Thesis, Linköpings universitet, Institutionen för systemteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014.
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The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.
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Pichler, Markus. "Phase-locked-loop-based signal synthesis for frequency-modulated continuos wave radar /." Linz : Trauner, 2008. http://opac.nebis.ch/cgi-bin/showAbstract.pl?u20=9783854993889.
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Muppala, Prashanth. "High-frequency wide-range all digital phase locked loop in 90nm CMOS." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.
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Sorfleet, Winston L. Carleton University Dissertation Engineering Electrical. "Noise and transient analysis of a fractional-n phase-locked loop frequency synthesizer." Ottawa, 1991.
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Kong, Weixin. "Low phase noise design techniques for phase locked loop based integrated RF frequency synthesizers." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/2391.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.<br>Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Valero, Lopez Ari Yakov. "Design of frequency synthesizers for short range wireless transceivers." Diss., Texas A&M University, 2003. http://hdl.handle.net/1969.1/108.
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The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.
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Singh, Guneet. "High-frequency charge-pump based phase-locked loop design and it's characterization using verilog-ams." Cincinnati, Ohio : University of Cincinnati, 2006. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1155077793.
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Thesis (M.S.)--University of Cincinnati, 2006.<br>Title from electronic thesis title page (viewed Nov. 29, 2006). Includes abstract. Keywords: Phase Locked Loops, PLLs, PLL, Verilog-AMS. Includes bibliographical references.
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SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.
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Atriss, Ahmad Hussein. "A high-frequency integrated CMOS phase-locked loop independent of silicon process variations and temperature conditions." Diss., The University of Arizona, 1993. http://hdl.handle.net/10150/186575.
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The increasing demand for local high-frequency operations on microprocessor and data-communication chips has led to the need for phase-locked loops to generate on-chip high-frequency clocks controlled by a much lower-frequency externally-provided system reference clocks. A high-frequency integrated CMOS phase-locked loop, which is independent of temperature and silicon processing variations, has been designed and tested. The system-level design was based on both frequency linear analysis and transient time-domain analysis performed using MTIME simulations. The design in this work integrates a phase-frequency detector, a symmetric charge-pump, an external low-pass RC loop filter, a digital-load-controlled voltage-controlled oscillator (DLCVCO), a programmable feedback-divider, a frequency-range detector (FRD), a circuit which initializes the loop filter node to VDD, a digital-load-activation cell, and associated circuitry on a portion of one die. The DLCVCO was implemented by a ring of three inverters; frequency was controlled by digitally programming the capacitive loads connected to its inner nodes. The FRD was designed to sense the temperature and silicon process conditions of the PLL system, and control the number of capacitive loads activated to the inner nodes of the DLCVCO. A 0.8 μm CMOS process was used to implement this PLL system design. Tests demonstrated that this PLL generated frequencies in excess of 200MHz, locked onto a 2MHz reference clock, and achieved a tuning range of 12MHz to 212MHz independent of silicon process variations and temperature conditions.
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Al, Sabbagh Mhd Zaher. "0.18um phase/frequency detector and charge pump design for digital video broadcasting for handheld's phase-locked-loop systems." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1196281141.
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Burin, Amy Diana. "Bench test model of the human skull for testing the Variable Frequency Pulse Phase-Locked Loop Instrument." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1996. http://hdl.handle.net/10945/8028.
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Thesis (M.S. in Astronautical Engineering) Naval Postgraduate School, December 1996.<br>Thesis advisor(s): Sandra L. Scrivener. "December 1996." Includes bibliographical references (p. 115-116). Also available online.
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Tahir, Muhammed Imran. "Frequency and phase locking of a CW magnetron : with a digital phase locked loop using pushing characteristics." Thesis, Lancaster University, 2008. http://eprints.lancs.ac.uk/76594/.
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The main body of work presented in this thesis is precise frequency and phase control of a 1.2 kW CW cooker magnetron (National 2M137) locked to a 10 MHz reference injected with a very small RF signal (of the order of -40 dBc) creating a suitable RF source for particle accelerators and other sophisticated applications. We will go on to discuss the characterization of the magnetron with differing heater powers and load conditions when operated with a low cost switched mode power supply. We similarly identify three different regimes of the magnetron operation with respect to the heater power: firstly low noise operation for small heater powers (up to 15W), secondly unstable operation for mid-range heater powers (15W to 30W) and thirdly high noise operation at high heater powers (30W to 54W). We then introduce a novel method to lock the magnetron output frequency to the 10 MHz reference using a digital frequency synthesizer IC (Analog Devices ADF4113) in a negative feedback loop, with this method we exploit the use of the pushing mechanism where the ADF41113 controls the power supply output to vary the magnetron’s anode current, keeping its natural frequency locked to the reference. We next investigate the injection locking of the frequency locked magnetron with small injection levels (-29 dBc to -43 dBc) under differing operating conditions and observe a phase jitter performance of the order of+/-13 o for very small heater power and -29 dBc injection level. We then fast switch/ramp the injection phase and establish the maximum rate of change of the magnetron output phase. This rate was found to be 4p/us for -29 dBc injection level and 44W heater power. We finally discuss the implementation of a fast DSP based feedback control on the injection phase to improve the magnetron phase jitter performance to below 1o r.m.s.
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Pardo, Gonzalez Mauricio. "MEMS-based phase-locked-loop clock conditioner." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43643.
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Ultra narrow-band filters and the use of two loops in a cascade configuration dominate current clock conditioners based on phase-locked-loop (PLL) schemes. Since a PLL exhibits a low-pass transfer function with respect to the reference clock, the noise performance at very close-to-carrier offset frequencies is still determined by the input signal. Although better cleaning can be achieved with extremely narrow loops, an ultra low cut-off frequency could not be selected since the stability of the configuration deteriorates as the filter bandwidth is reduced. This fact suggests that a full-spectrum clock conditioning is not possible using traditional PLL architectures, and an alternative scheme is necessary to attenuate the very-close-to-carrier phase noise (PN). In addition, ultra-narrow loop filters can compromise on-chip integration because of the large size capacitors needed when chosen as passive. Input signal attenuation with relaxed bandwidth requirements becomes the main aspect that a comprehensive clock cleaner must address to effectively regenerate a reference signal.
This dissertation describes the Band-Reject Nested-PLL (BRN-PLL) scheme, a modified PLL-based architecture that provides an effective signal cleaning procedure by introducing a notch in the input transfer function through inner and outer loops and a high-pass filter (HPF). This modified response attenuates the reference-signal PN and reduces the size of the loop-filter capacitors substantially. Ultra narrow loops are no longer required because the notch size is related to the system bandwidth. The associated transfer function for the constitutive blocks (phase detectors and local oscillators) show that the output close-to-carrier and far-from-carrier PN sections are mainly dominated by the noise from the inner-PLL phase detector (PD) and local oscillator (LO) located in the outer loop, respectively. The inner-PLL PD transfer function maintains a low-pass characteristic with a passband gain inversely proportional to the PD gain becoming the main contribution around the carrier signal. On the other hand, the PN around the transition frequency is determined mainly by the reference and the inner-PLL LO. Their noise contributions to the output will depend on the associated passband local maxima, which is located at the BRN-PLL transition frequency. Hence, in this region, the inner-PLL LO is selected so that its effect can be held below that of the outer-PLL PD.
The BRN-PLL can use a high-Q MEMS-based VCO to further improve the transition region of the output PN profile and an LC-VCO as outer-PLL LO to reduce the noise floor of the output signal. In particular, two tuning mechanisms are explored for the MEMS-VCO: series tuning using varactors and phase shifting of a resonator operating in nonlinear regime. Both schemes are implemented to generate a tunable oscillator with no PN-performance degradation.
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Al, Sabbagh Mhd Zaher. "0.18μm phase/frequency detector and charge pump design for digital video broadcasting for handheld’s phase-locked-loop systems". The Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=osu1196281141.
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Dubbert, Dale F. "The RMS phase error of a phase-locked loop FM demodulator for standard NTSC video." Thesis, Kansas State University, 1986. http://hdl.handle.net/2097/9911.
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Bandy, James H. (James Henry). "Design of a phase-locked loop circuit in gallium arsenide for use in a high frequency clock distribution chip." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36564.
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Hsiao, Sen-Wen. "Built-in test for performance characterization and calibration of phase-locked loops." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51790.
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The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.
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Bueno, Átila Madureira. "Estudo do jitter de fase em redes de distribuição de sinais de tempo." Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-21072009-143554/.
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As redes de distribuição de sinais de tempo - ou redes de sincronismo - têm a tarefa de distribuir os sinais de fase e freqüência ao longo de relógios geograficamente dispersos. Este tipo de rede é parte integrante de inúmeras aplicações e sistemas em Engenharia, tais como sistemas de comunicação e transmissão de dados, navegação e rastreamento, sistemas de monitoração e controle de processos, etc. Devido ao baixo custo e facilidade de implementação, a topologia mestre-escravo tem sido predominante na implementação das redes. Recentemente, devido ao surgimento das redes sem fio - wireless - de conexões dinâmicas, e ao aumento da freqüência de operação dos circuitos integrados, topologias complexas, tais como as redes mutuamente conectadas e small world têm ganhado importância. Essencialmente cada nó da rede é composto por um PLL - Phase-Locked Loop - cuja função é sincronizar um oscilador local a um sinal de entrada. Devido ao seu comportamentamento não-linear, o PLL apresenta um jitter com o dobro da freqüência de livre curso dos osciladores, prejudicando o desempenho das redes. Dessa forma, este trabalho tem como objetivo o estudo analítico e por simulação das condições que garantam a existência de estados síncronos, e do comportamento do jitter de fase nas redes de sincronismo. São analisadas as topologias mestre-escravo e mutuamente conectada para o PLL analógico clássico.<br>Network synchronization deals with the problem of distributing time and fre- quency among spatially remote locations. This kind of network is a constituent element of countless aplications and systems in Engineering, such as communication and data transmission systems, navigation and position determination, monitoring and process control systems, etc. Due to its low cost and simplicity, the master-slave architec- ture has been widely used. In the last few years, with the growth of the dynamically connected wireless networks and the rising operational frequencies of the integrated cir- cuits, the study of the mutually connected and small world architectures are becoming relevant. Essentially, each node of a synchronization network is constituted by a PLL - Phase-Locked Loop - circuit that must automatically adjust the phase of a local oscillator to the phase of an incoming signal. Because of its nonlinear behavior the PLL presents a phase jitter with the double of the free running frequency of the oscillators, impairing the network performance. Thus, this work aims to study, both analytically and by simulation, the existence conditions of the synchronous states and the behavior of the double frequency jitter in the synchronization networks. Specifically the One Way Master Slave (OWMS) and Mutually Connected (MC) network architectures for classical analogical PLLs are analyzed.
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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.
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Frequency synthesizer is a key building block of fully-integrated wireless communication
systems. Design of a frequency synthesizer requires the understanding of
not only the circuit-level but also of the transceiver system-level considerations. This
dissertation presents a full cycle of the synthesizer design procedure starting from the
interpretation of standards to the testing and measurement results.
A new methodology of interpreting communication standards into low level circuit
specifications is developed to clarify how the requirements are calculated. A
detailed procedure to determine important design variables is presented incorporating
the fundamental theory and non-ideal effects such as phase noise and reference
spurs. The design procedure can be easily adopted for different applications.
A BiCMOS frequency synthesizer compliant for both wireless local area network
(WLAN) 802.11a and 802.11b standards is presented as a design example. The two
standards are carefully studied according to the proposed standard interpretation
method. In order to satisfy stringent requirements due to the multi-standard architecture,
an improved adaptive dual-loop phase-locked loop (PLL) architecture is
proposed. The proposed improvements include a new loop filter topology with an
active capacitance multiplier and a tunable dead zone circuit. These improvements
are crucial for monolithic integration of the synthesizer with no off-chip components.
The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time
performance while making it more suitable for monolithic integration. It opens a
new possibility of using an integer-N architecture for various other communication
standards, while maintaining the benefit of the integer-N architecture; an optimal
performance in area and power consumption.
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Imran, Saeed Sohail. "Investigation of Mechanisms for Spur Generation in Fractional-N Frequency Synthesizers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80886.
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With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.
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Konečný, Tomáš. "Návrh fázového závěsu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217873.
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Monica, G. Della, and E. Tonello. "NEW GENERATION COMMAND RECEIVER FOR SATELLITE USING BENEFITS OF DIGITAL PROCESSING." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/607344.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California<br>Presentation of Alcatel Espace last studies and developments regarding TT&C receiver
Products for satellite. This document lays on 3 parts:
· a technical point of view showing digital demodulation principles used (base band
recovery, analytical head, PM or FM demodulation) and their related offered
possibilities(digital controlling loop, lock status detection, jammer detection,....)
· a technology/design description
· a synthesis showing performance and results
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Valenta, Václav. "Frequency synthesis for cognitive multi-radio." Phd thesis, Université Paris-Est, 2010. http://tel.archives-ouvertes.fr/tel-00597461.
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This doctoral thesis deals with design aspects of a reconfigurable frequency synthesizer for flexible radio transceivers in future cognitive multi-radios. The frequency bandwidth to be covered by this multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards in the frequency band 800 MHz to 6 GHz. Since multi-standard operation is required, the synthesizer must fulfil the most stringent and sometimes conflicting requirements. Given these requirements, a novel approach for multi-mode frequency synthesis has been conceived. A hybrid phase locked loop based frequency synthesizer has been proposed and a novel switching protocol has been presented and validated on an experimental evaluation board. This approach combines fractional-N and integer-N modes of operation with switched loop filter topology. Compared to standard PLL techniques, the hybrid configuration provides a great flexibility in terms of reconfiguration and moreover, it offers relatively low circuit complexity and low power consumption. This architecture provides reconfiguration of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards. Corresponding analyses, simulations and measurements have been carried out in order to verify the performance and functionality of the proposed solution. A part from the design of the multiband frequency synthesizer, a set of regional measurements of the radio spectrum utilization has been carried out in the framework of this dissertation research. These measurements are based on the energy detection principle and provide a close look at the degree of radio spectrum utilization in different regions, namely in the city of Brno in the Czech Republic and in the city of Paris and one of its suburbs in France. The goal of the experimental measurement campaign has been to estimate the degree of radio spectrum usage in a particular environment and to point out the fact that a new approach for radio spectrum management is inevitable
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Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.
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Chen, Shih-Hsuan, and 陳世泫. "Phase Locked Loop Based Frequency Synthesizer Study." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/01715331083929486080.
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碩士<br>國立暨南國際大學<br>電機工程學系<br>91<br>ABSTRACT
The research of this thesis, “Phase Locked Loop based Frequency Synthesizer,” is focused on each subsystem circuit of the frequency synthesizer, such as the phase/frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the divider. The comparison of the characteristics between the subsystems has been done.
To design the frequency synthesizer, the behavior of the system is analyzed by using the mathematics tool, SIMULINK of MATLAB. The schematic of the circuit is simulated by using HSPICE with the parameters of TSMC 0.35μm 1P4M CMOS process model. Two kinds of voltage-controlled oscillators, which are consisted by fully differential delay cells, are used to simulate the performance of the frequency synthesizer.
The frequency synthesizer is demonstrated in TSMC 0.35μm 1P4M CMOS technology. The simulated results show that the maximum operation frequency is 400 MHz and the power consumption is 18 mW. The chip area including the test circuit and pads is 1.428 mm × 1.428 mm.
Keywords: phased locked loop (PLL), frequency synthesizer, phase/frequency detector, charge pump, loop filter, voltage-controlled oscillator, divider.
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Chen, Chia-Min, and 陳嘉旻. "Design of a Sub-Sampling Phase-Locked Loop with a Robust-Locking Frequency-Locked Loop." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t5tdy5.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>107<br>Sub-sampling technique has been adopted in the PLL to reduce in-band phase noise nowadays. Hence, the loop bandwidth can be expanded to reduce the RMS jitter furthermore. However, the sub-sampling loop (SSL) can not detect large frequency. It needs an additional frequency-locked loop (FLL) to calibrate frequency. Nevertheless, if the PLL loses lock by some reasons, it needs a long locking time while using the traditional FLL.
This thesis implements an integer-N PLL, which can achieve low in-band phase noise by the sub-sampling technique. In addition, the proposed frequency-locked loop (FLL) makes the PLL more robust. This PLL is fabricated in 90-nm CMOS technology. The active area is 0.3 mm2. The power supply is 1.2 V. The output frequency ranges from 2.22 to 2.48 GHz. From the measurement results, the in-band phase noise is -110 dBc/Hz, the RMS jitter integrated from 10 kHz to 30 MHz frequency deviation is 539.3 fs, the reference spur is -50 dBc. The power consumption is 14.6 mW at 2.42-GHz output frequency with 20-MHz input reference frequency. While switching the output frequency from 2.4 to 2.46 GHz, the locking time is about 3.2 μs。
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Chan, Chun-Ching, and 詹駿清. "Research on Millimeter-Wave Injection-Locked Oscillators and Frequency-Locked Loop." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/66777148597398694174.
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碩士<br>國立中央大學<br>電機工程學系<br>104<br>In modern communication systems, a voltage-controlled oscillator (VCO) is an essential building block. Since the demand for high speed data transmission rate is increasing, we were driven to investigate millimeter-wave communication systems. This thesis focuses on the millimeter-wave oscillator and frequency-locked loop (FLL) using an injection-locked technique to achieve low dc power consumption and low phase noise. Analysis, design and measured results for K-band high-division, broadband regenerative injection-locked frequency divider (ILFD) in Chapter 2. Analysis and design of the FLL and the sub-harmonic injection-locked K-band VCO with FLL self-alignment are presented in Chapter 3 and 4, respectively. Finally, a V-band sub-harmonic injection-locked quadrature VCO (SILQVCO) using a transformer coupled (TC) topology are proposed in Chapter 5. All of the designs in this thesis are fabricated using TSMC 90 nm GUTM CMOS process.
Several frequency dividers and the injection-locked theory are introduced in Chapter 2. The locking range of divide-by-6 and divide-by-5 ILFDs is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. The proposed K-band divide-by-6 ILFD features a locking range of 7.1 GHz and a 31.2% fractional bandwidth. The dc power consumption is about 28.8 mW.
Analysis of the FLL, including the theoretical models, transfer functions and models using ADS (advance design system) software with system setup of each blocks in FLL are proposed in Chapter 3. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Based on the FLL design methodology in Chapter 3, a sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 4. A theoretical model of the SILFLL is proposed, and the calculated phase noise and jitter are presented for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 24 to 26.1 GHz, the locking range for each control voltages is about 100 MHz. The measured output power is higher than -17 dBm over the range. When the injection-locked output frequency is 25.3 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -114.3 dBc/Hz and 56.6 fs, respectively. The total dc power consumption is about 50.4 mW, and this work has the best FOM as compared with literatures.
In Chapter 5, we proposed a V-band wide locking range SILQVCO with low dc power consumption. By using a transformer coupled (TC) topology, the proposed TC-SILQVCO features the following advantages: 1) the negative resistance of the cross-coupled pair is not degraded due to the proposed SILQVCO without source degeneration, and the TC-SILQVCO can be operated in lower dc supply voltage as compared to the conventional SILQVCOs, 2) the dc bias of the injector can be properly designed for maximizing locking range, 3) the parasitic capacitance provided by the injector can be reduced due to the impedance transformation, and 4) the larger device size of the injector can be properly chosen enhancing the third harmonic. A theoretical model of the proposed TC-SILQVCO is also established and it has been carefully verified with the experimental results. The free-running oscillation frequency of the proposed TC-SILQVCO is from 56.6 to 59 GHz with a tuning range of 2.4 GHz. As the control voltage is 0.6 V and the input power is 4 dBm with one-third output frequency, the measured locking range is 1.2 GHz. When the injection-locked output frequency is 56.6 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz~40 MHz) are -126.8 dBc/Hz and 18 fs, respectively. The minimum quadrature phase error and amplitude error are 0.32° and 0.26 dB, respectively. The dc power consumption is 19.8 mW. The FOM and FOMT are -209 and -222, respectively.
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Chiu, Yun-Hui, and 邱筠惠. "Phase Locked Loop with Frequency-shift Magnetic Biosensor." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/dg6qy5.
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Lin, Tsung-Hsien, and 林宗憲. "Research on Injection-Locked Frequency Divider and Its Phase-Locked Loop Application." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/35852582693583131349.
Full textAbstract:
碩士<br>國立中央大學<br>電機工程學系<br>102<br>This thesis focuses on the injection-locked technique for the microwave and millimeter-wave phase-locked loop (PLL). A Ka-band injection-locked frequency divider (ILFD) and its PLL application are presented in Chapter 2 and 3, respectively. Finally, The design and analysis results of a V-band injection-locked oscillator (ILO) are proposed in Chapter 4.
Several frequency dividers and the injection-locked theory are introduced in Chapter 2. The locking range of divide-by-6 and divide-by-5 ILFDs is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectiors and the amplitude of the injection signal. The proposed divide-by-6 ILFD is fabricated using TSMC 90 nm low power (LP) CMOS process and it features with a locking range of 2.9 GHz. Moreover, the proposed divide-by-6 ILFD is applied to a fully integrated Ka-band PLL. Several DC bypass networks for the measurement is discussed to further reduce the baseband /DC noise, and the effective solution is also addressed. The measured output phase is -86.4, -90.7, and -91.69 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset at 25.38 GHz. The total DC consumption of PLL is about 40 mW.
The proposed injection-locked oscillator using TSMC 90 nm LP CMOS process is presented in Chapter 4. With the body-injection technique, wider locking range can be achieved. As the oscillation frequency are 50, 60, and 70 GHz, the widest locking ranges percentage at 7.8%, 13.8% and 14.7%, respectively. The total DC power consumption is about 31.2~44.4 mW.
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Yang, Han-Sen, and 楊瀚森. "Microwave and Millimeter wave Low Phase Noise Phase Locked Loop and Divider less Sub harmonically Injection locked Quadrature Frequency locked Loop." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/48jbwg.
Full textAbstract:
碩士<br>國立中央大學<br>電機工程學系<br>107<br>This thesis focuses on the research of frequency synthesizers with different architectures, and the application of millimeter-wave injection-locked technique in the conventional phase-locked loops (PLL) and the combination of divider-less frequency tracking loop method to realize frequency-locked loops (FLL), and further realize a quadrature outputs LO with low dc power consumption, low circuit complexicity, low phase noise, and low jitter.
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Liu, Cheng-Yu, and 劉晟佑. "Multiplied Delay Locked Loop Based Fractional-N Frequency Synthesizer." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/81114399005886347890.
Full textAbstract:
碩士<br>國立交通大學<br>電子研究所<br>99<br>These days the clock generator integrated with other system is needed to realize high speed computation. Spurious tones and phase noise often play a critical role in measuring quality. Random jitter is significantly reduced in Multiplying Delay-Locked Loops (MDLL), phase realigning clock multipliers, compared to that in typical Phase-Locked Loops (PLL). This is performed by launching the reference edge directly into their voltage controlled oscillators (VCO) or their delayline. However, the timing mismatch in singal path to the detector as well as non-idealities of analog property in the circuits casuse a significant increase in deterministic jitter. So dealing with the spurious tone the same as deterministic jitter is this research topic. On the other hand, the channel efficiency of communication system used by the fractional-N frequency synthesizer is much higher than that used by the integer-N frequency synthesizer. The sigma delta modulator adopted in fractional- N frequency synthesizer achieves the resolution of fractional-N by generating the fractional number in average and have the property of programmable. Yet the frequency of the reference clock is not limited and not confined within the modulation signal, which gives greater design flexibility at the system level. Recently fractional- N frequency synthesizer mainly uses fractional- N frequency PLL to serve as the supply of the clock. How to reduce to phase noise contributed from jitter accumulation of the PLL/MDLL on commutation systems is the main point of our invention.
The realization of the concept of the adjustment of the reference clock on fractional- N based MDLL is that, first to know quantized information compared between the reference clock and the divided clock, generated from divider having divider ratios modulated by the sigma delta modulator (ΣΔ) to achieve fractional – N resolution. Reload the reference clock correctly or not that cause serious problems of phase offset. We modify the sigma delta modulator (ΣΔ) to predict the signal of the residue (residue[k]), which is synchronized with the error compared between the reference clock and the divided clock. The modified sigma delta modulator (ΣΔ) consists of three parts, the sigma delta modulator changing the divider ratio, the accumulator counting the reference edge, and the residual sigma delta modulator on the feedback loop. The point is this feedback loop make the the residue (residue[k]) avoiding the phase offset to align the reference edge. The residue (residue[k]) is used to determine the time of the reload of the reference clock, and let the delay line has the ability of the alignment. Because of the elimination of jitter accumulation, quantization noise of the sigma delta modulator and the noise from the reference clock induced phase noise is the bottleneck in state-of the-art synthesizer design.
Under this circumstance we propose a general form of MDLLs, which have the adjustment by reference clock, and can keep the advantage to prune away jitter accumulation. This general form composes of a multi-phase generator, a delay line, and the digital controller. The clock phases from the multi-phase generator can be reloaded in the delay line and the digital controller determines the allowance to reload the clock phase and the order of reload. If the order is random pattern, the spurs caused by the adjustment can attenuate effectively. The value of attenuation can be predicted by the theorem of Markov Chain. For example, the multi-phase generator implemented by a delay line which is rounded by delay cells use the order N+ΔN, ΔN is random variable, to inject the second delay line to reduce the spurs. The amount of the reduction of spurs and the phase increment are verified under both behavior simulation and math, and less than 6dB.
Note that the invention is not limited to ADC system, but is applicable to other systems and integrated circuits that have low noise, fractional – N resolution of MDLL.
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Chen, Ying-Chieh, and 陳穎傑. "A Study of Delay-Locked Loop based Frequency Multiplier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/28375054858861740368.
Full textAbstract:
碩士<br>國立彰化師範大學<br>電子工程學系<br>100<br>In this thesis, a frequency multiplier is studied, which consists of the delay-locked loop with pre-charged circuit and frequency multiplying circuits. The output frequency varies from 0.5 to 4 times of input frequency, step-up by 0.5. So totally, there are eight selectable frequency ranges. The TSMC 0.18 μm Mixed Signal 1P6M process parameter is used to simulate the multiplier circuit. The input frequency of delay-locked loop ranges from 345 MHz to 434 MHz, and output frequency of frequency multiplier ranges from 173 MHz ~ 1.73 GHz. For the power supply voltage equals to 1.8 V, 400 MHz input frequency, and 1.6 GHz output frequency, the simulation results show that the power consumption of the frequency multiplier is 4.6 mW, lock time is 0.5 s, the phase error is 62.7 ps, cycle to cycle jitter is 61.7 ps.
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Liang, Ming-Hui, and 梁明惠. "Design of a Delay-Locked Loop Based Frequency Multiplier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/62026976905031107652.
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碩士<br>國立東華大學<br>電機工程學系<br>94<br>A frequency multiplier based on a delay-locked loop (DLL) is proposed in this thesis. DLLs have been widely used for clock deskew in stead of phase-locked loops (PLLs) for the advantages of inherent stability and design simplicity. The frequency multiplier realized by a multiphase edge combiner multiplies the frequency of input signal without a jitter accumulation problem. An external multiplication factor control circuit selects the signal for multiplexer(MUX) and the transition detector. Appropriate phases for DLL locking are selected by MUX. With those function, the frequency multiplier can change the multiple rate dynamically. The DLL-core keeps the latency of one clock cycle delay.
The proposed DLL-based frequency multiplier is designed and simulated with tsmc 0.18um CMOS process parameters. The circuit can be operated at the supply voltage of 1.8V. The output frequencies of the proposed circuit are from 192MHz to 1.946GHz. The input operation frequency range of DLL-core is from 192MHz to 278MHz. The locking time is 2.72us at eighth stage of 250MHz, 0.84us at seventh stage of 250MHz, 0.66us at sixth stage of 250MHz, and 1.35us at fifth stage of 250MHz. The peak to peak jitter is 58ps. The cycle to cycle jitter is 46ps. RMS jitter is 16.2ps. The duty cycle is 49.42%~50.51% at 250MHz. The power consumption of the DLL-core is 2.45mW . The power consumption of the frequency multiplier is less than 5.8mW.
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Lin, Hong-Yu, and 林宏育. "High-Speed Frequency Divider for Phase-Locked Loop Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/43683373139710653600.
Full textAbstract:
碩士<br>國立清華大學<br>電子工程研究所<br>94<br>ABSTRACT
The demand of the high data capacity and high transmitting rate makes the operation frequency of the communication system increases rapidly. The frequency divider, typically used for phase-locked loop, plays an important role in a communication system. The frequency divider reduces the high frequency to low frequency for certain application.
The main focus of this work is to design various frequency dividers based on a standard CMOS technology. The basic theory of the Phase Locked Loop (PLL) is introduced in the beginning, which illustrates the importance of a frequency divider, and the advantage of using high frequency divider for PLL. A fully integrated frequency divider is implemented by a 0.18-mm CMOS technology and demonstrates an operation frequency up to 20GHz for Local Multipoint Distribution System (LMDS) applications. The proposed frequency divider consists of both analog circuit and digital circuit with a function of divided by 4 in the frequency range from18.8GHz ~ 23.2GHz.
Second, a frequency divider with active inductor is implemented in CMOS technology. The proposed frequency divider replaces the passive spiral inductor with active inductor to reduce the required chip area significantly. The methodology of source degeneration is used to increase the operation frequency. From measurement results, the proposed frequency divider has the function of divided by 2 in the frequency range from 5.4GHz ~ 6.4GHz. Compared with other works, this work has the smaller chip area under the same circuit topology.
A frequency divider with feedback resistor is designed, which employs a feedback resistor to increase the operation frequency. From simulation results, the feedback resistor can increase operation frequency effectively. The proposed frequency divider can operate in the frequency range from 12GHz to 20GHz. Compared with other works, this work has the smaller chip area under the same operation frequency.
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Chen, Xiang-En, and 陳祥恩. "A Vital-Sign Sensor using Frequency-Locked Loop Technique." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/r4rn39.
Full textAbstract:
碩士<br>國立中山大學<br>電機工程學系研究所<br>107<br>This thesis presents a non-contact vital sign sensing system that use a frequency- locked loop (FLL) to improve the signal-to-noise ratio (SNR). The vital signs are the phase change caused by the small movement of the chest. The small movement comes from the respiration and heartbeats.
Generally, the detected vital signs degraded as the measurement distance increases. Under this condition, the detected vital sign will probably be cover by the phase noise of radar. The FLL can efficiently suppress the phase noise of the voltage-controlled oscillator (VCO) within the bandwidth of FLL, so that the frequency of the oscillation source can be more stable, and reduce its own frequency deviation. This thesis utilize this characteristic to improve the radar system. Besides, the FLL structure can simultaneously amplify the vital-sign signal, and reduce the phase noise of the radar system. Then make the SNR of the radar system better. These advantages make that the effective detection distance of the radar is extended to more than 5 m.
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Lee, Hsien-Hsing, and 李賢興. "A Delay-Locked Loop Frequency Synthesizer for WCDMA Applications." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/67213742631769414672.
Full textAbstract:
碩士<br>國立彰化師範大學<br>電機工程學系<br>93<br>This thesis proposes a multiple frequency channel selector based delay-locked loop frequency synthesizer designed in 0.18-μm CMOS process with 1.8V supply voltage. DLL has several inherent advantages over the PLL, i.e., no jitter accumulation, fast locking, stable loop operation and easy integration of the loop filter. This proposed architecture uses a multiple frequency channel selector to down convert the RF receiver signal. In order to obtain twelve frequency channels, we design a novel multiple frequency circuit for WCDMA application. The novel multiple frequency circuit can generate N multiple frequency. In addition, we improve the other circuits to increase the whole efficiency. These circuits include waveform converter, buffer circuit, and voltage-controlled delay line. The waveform converter transforms a square wave signal to produce in-phase and quadrature-phase sinusoidal signal outputs. The multiple frequency channels are generated from 422MHz to 434MHz. The frequency multiplication of waveform converter is set five in the structure, and the output receiver frequency operates from 2.11GHz to 2.17GHz. The bandwidth of channel is 5MHz. When the output frequency is 2.11GHz, the phase noise at 100kHz offset from the carrier is –128dBc/Hz, and the power consumption is 5.8mW with 350ns locked time.
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Tasi, Tai-Hsuan, and 蔡岱烜. "A Novel Frequency-Locked Loop Using Injection-Locking Oscillator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/26098257125883264170.
Full textAbstract:
碩士<br>國立高雄第一科技大學<br>電腦與通訊工程研究所<br>102<br>This paper discussed the characteristic of injection locking oscillator (ILO) primary. It depends on the output power of voltage-controlled oscillator (VCO) , the Q-factor of VCO , the maximum locking bandwidth , injection power and injection frequency. The characteristic contains the stabilizing angle and locking time of ILO. And then we can apply the delay time characteristic of injection locked techniques to replace the delay line of frequency discriminator. And using the ILO to replace the delay line of traditional frequency-locked loop (FLL) . This paper demonstrated the phase noise measurement result of both FLL structure. The traditional FLL and propose FLL suppress the phase noise of VCO which performance was 5 dBC and 9 dBC @ 1 MHz offset frequency, respectively. At the same time the stabilizing angle of ILO affects locking time，and the phase noise has the best suppressing effect when the angle at 90°.
Keyword：Injection locking oscillator、Voltage controlled oscillator、Frequency locked loop、Frequency discriminator、Stabilizing angle、Delay time、Phase noise
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Li, Sheng-Ming, and 李昇洺. "Design of V- and D-Band High-Division-Ratio Injection-Locked Frequency Dividers and Quadrature Frequency-Locked Loop." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/15279932894892251216.
Full textAbstract:
碩士<br>國立中央大學<br>電機工程學系<br>105<br>In recent years, the research of millimeter-wave transceiver is increasing to serve a vast range of applications for high data rate wireless communication. A phase-lock loop (PLL) is widely used as a local oscillator (LO) in modern communication transceivers. The LO needs low power consumption and low phase noise for frequency synthesis in most of the transceivers. The high-division-ratio divider chain is also needed in a millimeter-wave PLL. This thesis focuses on the millimeter-wave frequency divider and frequency-locked loop (FLL) using an injection-locked technique to achieve low power consumption and low phase noise. Analysis, design and measured results for V-band high-division-ratio divide-by-10 injection-locked frequency divider (ILFD) in Chapter 2. Analysis, design and measured results of the sub-harmonic injection-locked VCO with FLL self-alignment (SILFLL) are presented in Chapter 3. Finally, a D-band ILFD are proposed in Chapter 4. The V-band divide-by-10 ILFD and SILFLL in this thesis are fabricated using TSMC 90 nm GUTM CMOS process. The D-band ILFD is fabricated using TSMC 40 nm GUTM CMOS process.
First, several frequency dividers and the injection-locked theory are introduced in Chapter 2. Then, the locking range of divide-by-5 is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. Using harmonic peaking inductor improves the locking range of divide-by-10 and divide-by-5 ILFDs. The proposed V-band divide-by-10 ILFD features a locking range of 4.2 GHz and a 6.9% fractional bandwidth. The power consumption is about 16 mW.
A sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 3. First, the theoretical models and transfer functions of FLL are introduced, then using ADS (advance design system) software with system setup analyses FLL. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Furthermore, a theoretical model of the SILFLL is proposed, and used to calculate phase noise and jitter for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 48.8 to 51.1 GHz and locking range for each control voltage is about 30 MHz. The measured output power is higher than -11 dBm over the range. When the injection-locked output frequency is 49.7 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -103.4 dBc/Hz and 124.8 fs, respectively. The total power consumption is about 75.4 mW.
In Chapter 4, we proposed a D-band wide locking range divide-by-4 ILFD with low power consumption. The locking range is proportional to the device size of the injectors and the amplitude of the injection signal like in Chapter 2. The free-running oscillation frequency of the proposed ILFD is about 35.8 GHz and phase noise is -60.9 dBc/Hz. The measured locking range is about 2.5 GHz from 142.5 to 145 GHz with an input power -5 dBm. When the input signal is 144 GHz, the measured input and output phase noises at 100 kHz offset are respectively -91.3 and -102.6 dBc/Hz. The phase noise difference between input and output is about 12 dB, and it agrees with the theoretical calculation (20log4). The core power consumption is about 2.2 mW.
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Chen, Yen-hung, and 陳燕虹. "Design and Analysis of Phase-Locked-Loop-Based Frequency Synthesizer." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85399902295213114533.
Full textAbstract:
碩士<br>朝陽科技大學<br>資訊工程系碩士班<br>97<br>ABSTRACT
In this thesis we design a frequency synthesizer based on phase-locked- loop. The PLLs are important components widely used in the electronic and communication circuits. They are used to solve the clock skew and frequency synthesis problems of ICs in a fast operation speed and highly integrated environment. The application of the frequency synthesizer is extensive, for example: Television select platform device, so long as wireless network card ,etc. concern locking of frequency have existence of it, the purpose of this thesis lies in recommending the theory of the frequency synthesizer to analysis and the actual design process of a frequency synthesizer.
The TSMC 0.35 um BiCMOS Mixed Signal SiGe 2P4M process is used to implement the frequency synthesizer； its consumption power of the frequency synthesizer is 40mW with the 3.3V power supply. A wide range of ring VCO operation frequency, 1.1GHz-2.8GHz, is designed to ensure that the VCO still can generate the desired frequency even when the process conditions vary. Simulation results demonstrate that the synthesizer obtains a steady output signal under dierent corner models. The phase noise is obtained to be -106dBc/Hz.
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Wu, Chia-Che, and 吳嘉哲. "DESIGN OF THE PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER FOR 802.11a." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/21729362255888179132.
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碩士<br>大同大學<br>電機工程學系(所)<br>100<br>In this thesis, we refer to the IEEE 802.11a standard and design a 5.8GHz phase-locked loops frequency synthesizer fitting the specification. The phase-locked loops frequency synthesizer consists of a phase-frequency detector, charge pump, loop filter, LC-tank VCO, injection locked frequency divider and a pulse-swallow architecture frequency divider with only one counter.
The proposed LC-tank voltage-controlled oscillator adopts NMOS cross-coupled pair in order to get larger output voltage swing and using injection locked frequency divider in order to get low phase noise. The injection-locked frequency divider can decrease power consumption and operate in high frequency, but the operation range of bandwidth is limited.
The frequency synthesizer is implemented by TSMC 0.18-μm single-poly six-metal CMOS process. The ADS simulation results justify the feasibility of the proposed phase-locked loops frequency synthesizer.
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Su, Jiun-Yi, and 蘇浚毅. "A 2.4 GHz CMOS FREQUENCY SYNTHESIZER BY PHASE-LOCKED LOOP." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/57202797504644922187.
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碩士<br>大同大學<br>電機工程研究所<br>89<br>In this thesis, a frequency synthesizer by using phase-locked loop is designed. This frequency synthesizer is realized by 0.35mm TSMC CMOS process. An improved charge pump circuit is presented, it can reduce the problem causing by charge injection of the switch. The voltage- controlled oscillator adopts the LC oscillator topology. It has larger voltage swing because containing a NMOS pair and a PMOS pair rather than a NMOS pair circuit only. The divider uses the swallow counter topology. The operation frequency of the divider is improved more than 2.4GHz and has six channels selection.
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Huang, Shu-Yan, and 黃書彥. "Design of Frequency-Locked Loop and Track-and-Hold Amplifier." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/7994kg.
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碩士<br>國立中央大學<br>電機工程學系<br>103<br>This thesis focuses on the sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) for microwave and millimeter-wave applications and the high speed track-and-hold amplifier (THA) for front-end of analog-to-digital converter (ADC). The analysis, simulation and measurement of the SILVCO with FLL are presented in Chapter 2 and 3, respectively. The design and analysis of a broadband CMOS THA are proposed in Chapter 4.
The theoretical model of SILVCO with FLL are proposed in Chapter 2. The transfer functions of the other blocks in SILVCO with FLL are presented. The SILVCO with FLL is designed using the proposed model, and the calculated results are presented to verify the loop stability. The proposed SILVCO with FLL demonstrates good robustness versus process, voltage, and temperature variations. The proposed SILVCO with FLL is fabricated using TSMC 90 nm CMOS general purpose (GP) process. The measurements of the SILVCO with FLL and phase-locked loop (PLL) are completely presented. As the output frequency is 10.4 GHz, the proposed SILVCO with FLL features a phase noise of -130.38 dBc/Hz and the minimum jitter features 30.25 fs when output frequency is 10.3 GHz. The dc power consumption of the proposed SILVCO with FLL is 26 mW.
The design and analysis of the proposed THA are presented in Chapter 4. The distributed amplifier (DA) is adopted to enhance the bandwidth of the proposed THA. The dummy switch topology is also adopted in the track-and-hold stage to avoid the charge injection. The cascode amplifier is used to enhance the linearity of the proposed THA. The proposed THA is fabricated using TSMC 90 nm CMOS low power (LP) CMOS process. The proposed THA features a 3-dB bandwidth from 0 to 17 GHz. The measured spurious-free dynamic ranges (SFDR) of the proposed THA are -42.1 dB and -41.9 when the sampling rates are 12 GS/s and 6 GS/s, respectively. The dc power consumption of the proposed THA is 216 mW.
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Lee, Yu-Yun, and 李豫勇. "Detection of instantaneous frequency in EEG using phase locked loop." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/50570372098348872133.
Full textAbstract:
碩士<br>國立交通大學<br>控制工程系<br>84<br>In this thesis, we discuss the fundamental theory and
characteristicof phase locked loop ( PLL ), detection of the
frequency of EEG signals,and hardware implementation of PLL
circuits. We apply PLL to detectionof the frequency of EEG
signals. PLL has been widely used in communicationsystems. In
general, PLL performs well for high-frequency, pure
sinusoidalsignals. However, EEG is a low-frequency and multi-
component signal. In consideration of developing a real-time
instantaneous frequency detection for EEG analysis, we begin
with investigation of fundamental propertiesof PLL through
computer simulatiion. The performance of PLL under both low-
frequency and high-frequency situation is analyzed. It is found
a modification of the PLL enables detection of time-varying
frequency ofEEG. To further verify results of simulation, a
hardware-realized system isdesigned and implemented to simulated
low-frequency signals. Results of frequency detection by the
hardware PLL system agree with which of computersimulation. From
this preliminary research work, PLL is feasible for real-
timedetection of EEG's frequency.
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Wang, Hui-Min, and 王惠民. "A Digital Frequency Modulator Based On A Phase-Locked Loop." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/40493039639107860789.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>91<br>This thesis implements a spread spectrum clock generator (SSCG) with new algorithm of digital frequency modulation. The spread spectrum clock generator is composed of 200MHz phase look loop (PLL), parallel data queue, and digital frequency modulator. Conventional method of generating spread-spectrum clock is that modulating voltage controlled oscillator (VCO) directly by a triangular wave with a constant modulation frequency. Common application of spread-spectrum technique is mainly in the generation of system clock signals. In this thesis, this SSCG is utilized for spreading both clock signals and the data in spectrum for reducing EMI when these signals are transmitted on transmission line. These data are simultaneously synchronized by the clock signals. To match this new application, a new algorithm of implementing spread spectrum clock generator is proposed. In this algorithm, the triangular wave is generated by detecting phase error of two clock signals, which are input reference clock and the clock generated by VCO, respectively. The major characteristic of using this technique is that controlling the phase error of two clock signals smaller than a value decided by algorithm of digital frequency modulation. The phase error controlled is used to keep the data of parallel data queues transmitted correctly. Therefore, the SSCG can not only generate a spread spectrum clock but also control the data sequence synchronized by the clock in parallel data queues.
This SSCG is fabricated in 0.25μm 1P5M CMOS technology and occupies an area of 1.05mm x 1.08mm. By simulation, the power consumption is 42mW at 2.5 supply voltage and the spread rate is 12% at 200MHz center frequency. The amplitude is attenuated about 15dB at the spectrum analysis
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Uttarwar, Tushar. "A digital multiplying delay locked loop for high frequency clock generation." Thesis, 2011. http://hdl.handle.net/1957/25739.
Full textAbstract:
As Moore���s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area.
The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a ��-�� DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to-peak jitter and -50dbC/Hz reference spurs.<br>Graduation date: 2012
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Wu, Hsu-Heng, and 吳旭珩. "Fractional Frequency Synthesizer Based on All Digital Phase-Locked Loop (ADPLL)." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/05658100710312003208.
Full textAbstract:
碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>90<br>The frequency synthesizer is used to generate more one frequency from an input reference source for the applications of accuracy clock requirement, such as clock generator and transceiver. With the rapidly growth of wireless communication system and the high performance in clock accuracy and stability, the frequency synthesizer have became more important.
In this thesis, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A novel phase frequency detector (PFD) is developed for replacing the two independent detections of phase and frequency to improve the ADPLL performance. A modified phase frequency acquisition (PFA) is involved by the modified binary search algorithm (MBSA) with initial half-step size to speed up the convergence in both phase and frequency. The digital control oscillator (DCO) is investigated to have good linearity to further the ADPLL stability. And, the dual modulus frequency divider with divided by four or by five is applied to perform the variable fraction and to increase the accuracy of frequency synthesizer. Experimental results of overall simulation are well matched to our specification.
The frequency synthesizer is implemented to be a chip with TSMC 0.35μm 1p4m CMOS technology. The chip area is 1.3 x 1.3 mm². With the TimeMill and PowerMill tools, we got the more encourage simulation results. The power consumption is only 15mW, and the jitter is 90ps at 300MHz, and the locked time is less then 20 reference cycles.