Relevant bibliographies by topics / Fringing capacitance

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Fringing capacitance'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

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Journal articles on the topic "Fringing capacitance"

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Kumar, Arun, P. S. T. N. Srinivas, Shiv Bhushan, Sarvesh Dubey, Yatendra Kumar Singh, and Pramod Kumar Tiwari. "Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects." Journal of Nanoelectronics and Optoelectronics 14, no. 11 (2019): 1555–64. http://dx.doi.org/10.1166/jno.2019.2658.

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In this paper, an analytical threshold voltage model of double gate-all-around metal-oxide-semiconductorfield-effect-transistors (DGAA MOSFETs) including the fringing field effects is developed. The total fringing capacitance arising due to induced fringing fields in the device is divided into inner, outer and bottom fringing capacitance. A simple expression for each fringe capacitance is developed individually. The 3-D Poisson's equation has been solved in the channel region using the parabolic potential approximation method to develop the surface potential expressions. The effects of fringin
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Garbini, J. L., L. J. Albrecht, J. E. Jorgensen, and G. F. Mauer. "Surface Profilometry Based on Fringing Capacitance Measurement." Journal of Dynamic Systems, Measurement, and Control 107, no. 3 (1985): 192–99. http://dx.doi.org/10.1115/1.3140720.

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A rugged, compact sensor for in-process measurement of surface finish profiles is proposed. The concept is based on the detection of variations in the fringe electric field generated between the surface and a perpendicular, ceramic-encased electrode. An analysis of both static and spatial dynamic characteristics of this “capacitive profilometer” is presented. For some surfaces, the device acts as a low-pass spatial filter, attenuating the higher spatial frequencies. A method of dynamic compensation, based on Fourier transform techniques, is developed. Experimental results demonstrate the valid
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Vishvakarma, Babau R., Arif Ahmed Al-Fitiani, and K. V. Ravi Kumar. "Analysis of Microstrip Antenna Based on Fringing Capacitance." IETE Technical Review 10, no. 3 (1993): 205–8. http://dx.doi.org/10.1080/02564602.1993.11437325.

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Kim, Hyun Woo, and Daewoong Kwon. "Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer." Applied Sciences 10, no. 9 (2020): 3054. http://dx.doi.org/10.3390/app10093054.

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Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on th
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Rahman, Md Mosaddequr, and Sazzadur Chowdhury. "Square Diaphragm CMUT Capacitance Calculation Using a New Deflection Shape Function." Journal of Sensors 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/581910.

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A new highly accurate closed-form capacitance calculation model has been developed to calculate the capacitance of capacitive micromachined ultrasonic transducers (CMUTs) built with square diaphragms. The model has been developed by using a two-dimensional polynomial function that more accurately predicts the deflection curve of a square diaphragm deformed under the influence of a uniform external pressure and also takes account of the fringing field capacitances. The model has been verified by comparing the model-predicted deflection profiles and capacitance values with experimental results p
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Wakita, Naoki, and Naoyuki Shigyo. "Verification of overlap and fringing capacitance models for MOSFETs." Solid-State Electronics 44, no. 6 (2000): 1105–9. http://dx.doi.org/10.1016/s0038-1101(99)00331-7.

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Mahony, J. D. "Static fringing capacitance of a dielectric loaded coaxial termination." IEE Proceedings A Physical Science, Measurement and Instrumentation, Management and Education, Reviews 135, no. 7 (1988): 448. http://dx.doi.org/10.1049/ip-a-1.1988.0070.

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Lee, KwangWon, TaeYoon An, SoYeon Joo, Kee-Won Kwon, and SoYoung Kim. "Modeling of Parasitic Fringing Capacitance in Multifin Trigate FinFETs." IEEE Transactions on Electron Devices 60, no. 5 (2013): 1786–89. http://dx.doi.org/10.1109/ted.2013.2252467.

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Dean, Robert, Aditi Rane, Colin Stevens, Michael Baginski, Zane Hartzog, and David Elton. "Implementing Fringing Field Sensors in PCB Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 000579–98. http://dx.doi.org/10.4071/2010dpc-ta22.

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Interdigitated electrode structures are well suited for realizing capacitors where a significant percentage of the total capacitance in due to the out of plane fringing fields. An object that interferes with the fringing fields will then change the measurable capacitance between the electrodes. Therefore this configuration can be used as a sensor for the object that interferes with the fringing fields and is called a capacitive fringing field sensor. These types of sensors have been used in many applications, such as water detection, moisture content measurement and as proximity switches. Prin
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Ducu, D. O., R. J. Donahue, and J. B. Ghandhi. "Design of Capacitance Probes for Oil Film Thickness Measurements Between the Piston Ring and Linear in Internal Combustion Engines." Journal of Engineering for Gas Turbines and Power 123, no. 3 (2000): 633–43. http://dx.doi.org/10.1115/1.1368116.

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Measurement of the capacitance formed between the piston ring and a probe mounted in the cylinder liner provides an accurate means of determining the oil film thickness provided that the region between the ring and probe is flooded with oil and the dielectric constant of the oil is known. All aspects of the design, construction, installation of capacitance probes, and analysis of the resulting measurements are reviewed in this paper. Biases introduced due to the fringing of the electric field, curvature of the ring face profile, roughness of the ring profile, and the tilt angle of the ring fac
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Dissertations / Theses on the topic "Fringing capacitance"

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Cho, Ming-Hsiang, and 卓銘祥. "High-Frequency Modeling and Fringing-Capacitance Estimation of Embedded Capacitors in Multilayer Structures." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/12346091452185028836.

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碩士<br>國立交通大學<br>電信工程系<br>89<br>An accurate high-frequency equivalent-circuit model based on the concept of coupled transmission lines and a novel tech- nique for estimating the fringing capacitance of embedded capac-itors are presented in this investigation. To analyze the char-acteristics and high-frequency behavior of buried passive el-ement, the finite-difference time-domain (FD-TD) approach and moment method (MoM) are applied. Excellent agreement between the numerical results and equivalent-circuit models is observed over a wide range of spectrum.
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Chen, Jian-Zhong, and 陳建中. "Analysis of the Capacitance Behavior of Narrow-Channel FD SOI NMOS Device Considering the 3D Fringing Capacitances Using 3-D Simulation." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/42895815630262704875.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>94<br>This thesis reports the analysis of the Gate-Source/Drain and Source/Drain-Gate capacitance behavior of narrow channel FD SOI NMOS Device considering the fringing capacitance. The first chapter introduces the characteristic of the SOI Device and the Mesa Isolation SOI Device. Moreover, we also account for the impact of Fringing Electric Field Effect on the Small- Geometry SOI Device. The second chapter compares the impact on the total capacitance behavior of different channel width SOI Device due to the Fringing Capacitance Effect .we also compute out
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Wang, Chang-Wen, and 王昶文. "The Interconnect Fringing Capacitance Model and Its Applications to the Study of Pull-in Voltage of Micro Devices." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/55754710000378302748.

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碩士<br>國立臺灣大學<br>應用力學研究所<br>96<br>This research aims at developing empirical formulas for parallel-plate capacitor precisely, including two- and three-dimensional fringing capacitance effects. The derivation was started from massive numerical simulations of different geometry, and then we can derive two- and three- dimensional fringing capacitance formulas from choosing appropriate parameters to curve-fitting on results obtained from simulations. The relative errors of two- and three-dimensional fringing capacitance formulas are within 2 and 4 percent comparing with numerical simulations, respe
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Bekal, Prasanna. "Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices." Thesis, 2012. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215.

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In order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models. Although 3D device simulation can be used to extract such parasitics, it is expensive and does not consider the effects of nearby interconnect and devices in a layout. Conventional rule-based layout parasitic extraction (LPE) tools which are used for interconnect extraction are inaccurate in modeling 3D effects near devices. In this thesis, we propose a methodology which combines 3D field solver based extraction with the abi
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Book chapters on the topic "Fringing capacitance"

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"Appendix D: Fringing Capacitance." In Mosfet Models for Spice Simulation, Including BSIM3v3 and BSIM4. IEEE, 2010. http://dx.doi.org/10.1109/9780470547182.app4.

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Conference papers on the topic "Fringing capacitance"

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Salas, S., J. C. Tinoco, A. G. Martinez-Lopez, J. Alvarado, and J. Raskin. "Fringing gate capacitance model for triple-gate FinFET." In 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF). IEEE, 2013. http://dx.doi.org/10.1109/sirf.2013.6489442.

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Chen, Chung-Ping, and D. F. Wong. "Optimal wire-sizing function with fringing capacitance consideration." In the 34th annual conference. ACM Press, 1997. http://dx.doi.org/10.1145/266021.266295.

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Tinoco, J. C., A. G. Martinez-Lopez, G. Lezama, M. Estrada, and A. Cerdeira. "Extraction procedure for MOS structure fringing gate capacitance components." In 2015 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC). IEEE, 2015. http://dx.doi.org/10.1109/ropec.2015.7395129.

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Inoue, Takashi, Akio Wakejima, Katsumi Yamanoguchi та Norihiko Samoto. "Robust 0.13-μm Gate HJFET with Low Fringing Capacitance". У 2001 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2001. http://dx.doi.org/10.7567/ssdm.2001.e-5-2.

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Hattori, J., K. Fukuda, T. Ikegami, et al. "Fringing Field Effects in Ferroelectric Negative Capacitance Field-Effect Transistors." In 2017 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2017. http://dx.doi.org/10.7567/ssdm.2017.e-4-03.

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Maj, Cezary, and Michal Szermer. "Influence of Fringing Fields on Parallel Plate Capacitance for Capacitive MEMS Accelerometers." In 2020 IEEE XVIth International Conference on the Perspective Technologies and Methods in MEMS Design (MEMSTECH). IEEE, 2020. http://dx.doi.org/10.1109/memstech49584.2020.9109500.

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Ji, Feng, Jing-ping Xu, P. t. Lai, and Chun-xia Li. "Influence of Gate-Electrode Fringing Capacitance on Threshold Voltage of Nano-MOSFET." In 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306147.

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Elsaadi, Mussa, Mazhar B. Tayel, and D. P. Steenson. "An Empirical Formula of Fringing Field Capacitance for MEMS Tunable Capacitor Actuators." In 2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA. IEEE, 2021. http://dx.doi.org/10.1109/mi-sta52233.2021.9464509.

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Gaidhane, Amol D., Girish Pahwa, Amit Verma, and Yogesh Singh Chauhan. "Modeling of Inner Fringing Charges and Short Channel Effects in Negative Capacitance MFIS Transistor." In 2019 Electron Devices Technology and Manufacturing Conference (EDTM). IEEE, 2019. http://dx.doi.org/10.1109/edtm.2019.8731214.

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Orfao, B., B. G. Vasallo, D. Moro-Melgar, et al. "Technological Parameters and Edge Fringing Capacitance in GaN Schottky Barrier Diodes: Monte Carlo Simulations." In 2021 13th Spanish Conference on Electron Devices (CDE). IEEE, 2021. http://dx.doi.org/10.1109/cde52135.2021.9455727.

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