Relevant bibliographies by topics / Full subtractor

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  2. Dissertations / Theses
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  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Full subtractor'

Author: Grafiati
Published: 3 June 2025
Last updated: 1 August 2025

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Journal articles on the topic "Full subtractor"

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Monfared, Asma Taheri, and Majid Haghparast. "Design of New Quantum/Reversible Ternary Subtractor Circuits." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650014. http://dx.doi.org/10.1142/s0218126616500146.

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Ternary quantum circuits play a significant role in future quantum computing technology because they have many advantages over binary quantum circuits. Subtraction is considered as being one of the key arithmetic operations; hence, subtractors are very essential for the construction of various computational units of quantum computers and other complex computational systems. In this paper, we have proposed the realization of a quantum reversible ternary half-subtractor circuit using a generalized ternary gate, a ternary Toffoli gate, and a ternary C2NOT gate. Based on the realization of the ter
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Ye, Yichen, Tingting Song, Yiyuan Xie, and Chuandong Li. "Design of All-Optical Subtractors Utilized with Plasmonic Ring Resonators for Optical Computing." Photonics 10, no. 7 (2023): 724. http://dx.doi.org/10.3390/photonics10070724.

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In this paper, a novel plasmonic all-optical half-subtractor and full-subtractor are designed for optical computing. The structure of plasmonic subtractors consists of a metal–insulator–metal (MIM) waveguide and rectangular ring resonators covered by a graphene layer. Due to the nonlinear optical properties of graphene, the states of the plasmonic resonators can be controlled by the pump intensity of a pump beam focused on the graphene layer. The resonators can work as all-optical switches with an ultra-fast response time to constitute optical logic devices according to the directed logic mech
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V.Naga Lakshmi, E., and Dr N.Siva Sankara Reddy. "Estimation of Power for Reversible Subtractors." International Journal of Engineering & Technology 7, no. 4.5 (2018): 102. http://dx.doi.org/10.14419/ijet.v7i4.5.20021.

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In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG). Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gat
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Vinay, M. "Design and Implementation of 1-bit Full Subtractor Using FinFET." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 768–75. http://dx.doi.org/10.22214/ijraset.2024.63208.

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Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cou
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Doshanlou, Abdollah Norouzi, Majid Haghparast, Mehdi Hosseinzadeh, and Midia Reshadi. "Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor." International Journal of Quantum Information 17, no. 05 (2019): 1950048. http://dx.doi.org/10.1142/s0219749919500485.

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In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quan
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G., Hemanth Kumar, Gopi K., Gowtham P., and Naveen Balaji G. "Area Efficient Full Subtractor Based on Static 125nm CMOS Technology." International Journal of Trend in Scientific Research and Development 2, no. 6 (2018): 1371–74. https://doi.org/10.31142/ijtsrd18860.

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A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed wit
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Cheng, Kai-Wen, and Chien-Cheng Tseng. "Quantum full adder and subtractor." Electronics Letters 38, no. 22 (2002): 1343. http://dx.doi.org/10.1049/el:20020949.

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FathimaThuslim, A. "A Novel Design of SET-CMOS Half Subtractor and Full Subtractor." International Journal of Computer Applications 114, no. 12 (2015): 33–37. http://dx.doi.org/10.5120/20032-2134.

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Kaur, Sanmukh. "All-optical binary full subtractor using logic operations based on nonlinear properties of semiconductor optical amplifier." Journal of Nonlinear Optical Physics & Materials 25, no. 01 (2016): 1650003. http://dx.doi.org/10.1142/s021886351650003x.

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We propose a new and potentially integrable scheme for the realization of an all-optical binary full subtractor employing two half-subtractors and an additional OR gate. The half-subtractor comprises an XOR gate, an AND gate, and a NOT gate. The XOR gate is realized using semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometer (MZI). The AND, OR, and NOT gates are based on nonlinear properties of semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a borrow bit from the previous less significant bit order position. In our proposed design,
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Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power
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Dissertations / Theses on the topic "Full subtractor"

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Merriam, Ezekiel G. "Fully Compliant Mechanisms for Bearing Subtraction in Robotics and Space Applications." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/3564.

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Robotics and space applications represent areas where compliant mechanisms can continue to make a significant impact by reducing costs and weight while improving performance. Because of the nature of these applications, a common need is for bearing replacement mechanisms, or mechanisms that perform the function of a bearing without the complexity and failure modes associated with bearings. Static balancing is a design strategy that attempts to reduce the actuation effort of a mechanism, and has been applied to compliant mechanisms in some applications. Monolithic construction, especially by me
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Henri, Christopher J. "Application of stereoscopic digital subtraction angiography to stereotactic neurosurgery planning." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=55692.

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Mawko, G. M. "Three-dimensional analysis of digital subtraction angiograms for stereotactic neurosurgery planning." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74238.

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Geometric and tomographic methods of reconstructing three-dimensional cerebral blood vessels from two-dimensional digital subtraction angiograms are studied experimentally.<br>Three-dimensional vessel geometry is reconstructed from center-line coordinates of corresponding vessel branches in both stereo and biplane angiogram pairs. The problem associated with finding corresponding vessel branches in biplane images was shown to be reduced by re-projection of stereoscopically reconstructed vessels. Results indicate that the limiting factor in reconstruction accuracy is the degree of vessel foresh
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Chen, Yung-jiang, and 陳永江. "The Simulation of Full Adder and Full Subtractor Based on Artificial Neural Networks and Fuzzy Logic Control." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/80675180367498077380.

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碩士<br>國立高雄第一科技大學<br>電腦與通訊工程所<br>97<br>The purpose of this thesis is the simulation of full-adder and full-subtractor with program. Both the Artificial Neural Network and Fuzzy Logic Control are adopted in order to complete the truth table of such logic circuit.It is useful of Back Propagation Network in the application of Artificial Neural Network.And fuzzifier,inference engine,rule base,defuzzifier are the importat concept of Fuzzy Logic Control.
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Books on the topic "Full subtractor"

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mary, boved. Double Digit Addition and Subtraction Grades 1-3, +1500 Problems: Workbook, Worksheets Full of Math Practice Drills, Timed Tests, Learn to Add and Subtract, Addition and Subtraction Problem Worksheets, 2 Digit. Independently Published, 2020.

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Arts, Sk. Math Workbook for Grade 1 Full Colored: Addition and Subtraction Activity Book, Math for 1st Grade, Practice Math Activities, Full Colored. Lulu.com, 2021.

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Kindergarten Math Workbook Full Color: Addition, Subtraction, Shapes, and Counting Practice Sheets and Activity Book. Independently Published, 2021.

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Arts, Sk. Workbook for Grade 2 - Addition and Subtraction Full Colored: Grade 2 Activity Book, Second Grade Math Workbook, Fun Math Books for 2nd Grade, Full Colored. Lulu.com, 2021.

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Manning, James. Best Books for Two Year Olds (Kindergarten Subtraction/taking away Level 2): 30 full color preschool/kindergarten subtraction worksheets (includes 8 printable kindergarten PDF books worth $60.71). Kindergarten Workbooks, 2019.

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Addition and Subtraction Practice Workbook: 50 Math Games and Exercises to Learn Math - Activity Workbook for Kids - Kindergarten to First Grade - Full Colour. Independently Published, 2020.

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Addition and Subtraction Practice Workbook: 50 Math Games and Exercises to Learn Math - Activity Workbook for Kids - Kindergarten to First Grade - Full Colour. Independently Published, 2020.

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Preschool Beginner Math Workbook for Toddlers: Math Practice for Kids with Worksheets Full of Practice Drills / Addition, Subtraction, Comparison, Tracing Numbers, Coloring and More! Independently Published, 2020.

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book, preschooll. First Grade Math Work Book Full Year: Ages 5 to 7, 1st Grade, Numbers, Addition, Subtraction, Word Problems, Time, Money, Symmetries and More- 190 Pages. Independently Published, 2020.

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Fuson, Karen C., Aki Murata, and Dor Abrahamson. Using Learning Path Research to Balance Mathematics Education. Edited by Roi Cohen Kadosh and Ann Dowker. Oxford University Press, 2014. http://dx.doi.org/10.1093/oxfordhb/9780199642342.013.003.

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This chapter is an overview of central research-based perspectives that support teaching-learning for understanding and for fluency. We summarize the Class Learning Path Model that integrates two theoretical foci – a Piagetian focus on learning and a Vygotskiian focus on teaching – and specifies phases in learning that reflect Vygotsky’s assertion about the move from spontaneous to scientific concepts. Major aspects of the model were drawn from national research-based reports. This model connects understanding and fluency with a focus on mathematically important but also accessible methods in
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Book chapters on the topic "Full subtractor"

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AnanthaLakshmi, A. V., and G. F. Sudha. "Design of a Novel Reversible Full Adder and Reversible Full Subtractor." In Advances in Computing and Information Technology. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31600-5_61.

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Bhagya Lakshmi, K., D. Ajitha, and Y. Sujatha. "Novel Area Effective Designs for Full Adder and Full Subtractor Using QCA." In Advances in Communication, Devices and Networking. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2004-2_1.

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Wang, Yanfeng, Xing Li, Chun Huang, Guangzhao Cui, and Junwei Sun. "One-Bit Full Adder-Full Subtractor Logical Operation Based on DNA Strand Displacement." In Bio-inspired Computing – Theories and Applications. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3611-8_4.

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Sun, Junwei, Xing Li, Chun Huang, Guangzhao Cui, and Yanfeng Wang. "Two-Digit Full Subtractor Logical Operation Based on DNA Strand Displacement." In Bio-inspired Computing – Theories and Applications. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3611-8_3.

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Surya, Sri Sai, A. Arun Kumar Gudivada, and Durgesh Nandan. "Systematic Review on Full-Subtractor Using Quantum-Dot Cellular Automata (QCA)." In Proceedings of International Conference on Recent Trends in Machine Learning, IoT, Smart Cities and Applications. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7234-0_58.

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Pramanik, Amit Kumar, Jayanta Pal, and Bibhash Sen. "Synthesis and Analysis of Regular Clocking-Based Full Subtractor in QCA." In Communications in Computer and Information Science. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-94121-4_16.

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Pardhasaradhi, P., G. V. Ganesh, V. V. S. Krishna, M. Naga Sai Kiran, and K. Manikanta Sai. "Design of Hybrid Logic Full Subtractor Using 10 T XOR – XNOR Cell." In Advanced Technologies and Societal Change. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-4522-9_2.

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Akshitha and Niju Rajan. "Low-Power Analysis of Full Adder and Subtractor Design Using Adiabatic Logic Styles." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0626-0_30.

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Sarkar, Shubham, Sujan Sarkar, Arun Atta, Tuhin Pahari, Nishanta Majumdar, and Sourav Mondal. "9T and 8T Full Subtractor Design Using Modified GDI and 3T XOR Technique." In Advances in Computer, Communication and Control. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3122-0_49.

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Weik, Martin H. "full subtracter." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_7767.

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Conference papers on the topic "Full subtractor"

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Seyedi, Saeid, and Hatam Abdoli. "Approximate Full-Adder, Full-Subtractor, and Full-Adder/Subtractor Circuits Based on QCA." In 2025 29th International Computer Conference, Computer Society of Iran (CSICC). IEEE, 2025. https://doi.org/10.1109/csicc65765.2025.10967408.

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Goel, Mohit Kumar, and Kulbhushan Sharma. "Performance Analysis of Ternary Full Subtractor Implemented Using FinFET models." In 2024 Asian Conference on Intelligent Technologies (ACOIT). IEEE, 2024. https://doi.org/10.1109/acoit62457.2024.10941540.

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Furukawa, Hirotaka, Hisaya Sawada, Naruaki Hokari, Tatsuya Hasegawa, Daishi Nishiguchi, and Fukuhara Masaaki. "A Neuron CMOS Type Full Subtractor with Floating Gate Calibration Circuit." In 2024 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). IEEE, 2024. https://doi.org/10.1109/ispacs62486.2024.10868467.

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K., Paramasivam, Nithya N., Jana Priya S, Sanjay S, and Kavin Prasanth S. "Design and Simulation of an Efficient Memristor based Full subtractor using Hybrid logic." In 2025 Fourth International Conference on Smart Technologies, Communication and Robotics (STCR). IEEE, 2025. https://doi.org/10.1109/stcr62650.2025.11020009.

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Teja, Buchepalli Sai, and Madhusudan Singh. "Design of Low Power and High Speed 1-Bit Full Subtractor Using Zipper Logic Technology." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11009372.

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Basha, Mohammed Mahaboob, Krishna Samalla, Srinivasulu Gundala, Nouchu Rahul, Dadapak Sriya, and Salluri Deepika. "Exploring energy efficient area optimized one-bit full Subtractor circuit for Signal processing application using CMOS and FinFET Technology." In 2024 2nd International Conference on Networking, Embedded and Wireless Systems (ICNEWS). IEEE, 2024. http://dx.doi.org/10.1109/icnews60873.2024.10730942.

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Endo, Mamoru, Takefumi Nomura, Tatsuki Sonoyama, et al. "Multi-Photon Subtraction from Squeezed Light toward Full Quantum State Engineering." In Quantum 2.0. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/quantum.2024.qm4a.2.

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We have applied up to four annihilation operations to squeezed light by photon subtraction. The presence of negative values in the Wigner function for all states indicates the successful implementation of quantum manipulation.
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Yamazaki, Asumi, Hana Nakajima, Masashi Seki, and Takayuki Ishida. "Fully automated AI-based dual-energy subtraction system for chest radiography." In Physics of Medical Imaging, edited by John M. Sabol, Shiva Abbaszadeh, and Ke Li. SPIE, 2025. https://doi.org/10.1117/12.3044427.

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Emam, Maii T., and Layle A. A. Elsayed. "Reversible Full Adder/Subtractor." In 2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD). IEEE, 2010. http://dx.doi.org/10.1109/sm2acd.2010.5672298.

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Nissi, Vesapaga Grace, Sarada Musala, and Veerayya J. "Memristor based full subtractor." In 2022 International Conference on Communication, Computing and Internet of Things (IC3IoT). IEEE, 2022. http://dx.doi.org/10.1109/ic3iot53935.2022.9767971.

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