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Journal articles on the topic 'Full subtractor'

Author: Grafiati

Published: 3 June 2025

Last updated: 1 August 2025

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1

Monfared, Asma Taheri, and Majid Haghparast. "Design of New Quantum/Reversible Ternary Subtractor Circuits." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650014. http://dx.doi.org/10.1142/s0218126616500146.

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Ternary quantum circuits play a significant role in future quantum computing technology because they have many advantages over binary quantum circuits. Subtraction is considered as being one of the key arithmetic operations; hence, subtractors are very essential for the construction of various computational units of quantum computers and other complex computational systems. In this paper, we have proposed the realization of a quantum reversible ternary half-subtractor circuit using a generalized ternary gate, a ternary Toffoli gate, and a ternary C2NOT gate. Based on the realization of the ter

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2

Ye, Yichen, Tingting Song, Yiyuan Xie, and Chuandong Li. "Design of All-Optical Subtractors Utilized with Plasmonic Ring Resonators for Optical Computing." Photonics 10, no. 7 (2023): 724. http://dx.doi.org/10.3390/photonics10070724.

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In this paper, a novel plasmonic all-optical half-subtractor and full-subtractor are designed for optical computing. The structure of plasmonic subtractors consists of a metal–insulator–metal (MIM) waveguide and rectangular ring resonators covered by a graphene layer. Due to the nonlinear optical properties of graphene, the states of the plasmonic resonators can be controlled by the pump intensity of a pump beam focused on the graphene layer. The resonators can work as all-optical switches with an ultra-fast response time to constitute optical logic devices according to the directed logic mech

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3

V.Naga Lakshmi, E., and Dr N.Siva Sankara Reddy. "Estimation of Power for Reversible Subtractors." International Journal of Engineering & Technology 7, no. 4.5 (2018): 102. http://dx.doi.org/10.14419/ijet.v7i4.5.20021.

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In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG). Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gat

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4

Vinay, M. "Design and Implementation of 1-bit Full Subtractor Using FinFET." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 768–75. http://dx.doi.org/10.22214/ijraset.2024.63208.

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Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cou

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5

Doshanlou, Abdollah Norouzi, Majid Haghparast, Mehdi Hosseinzadeh, and Midia Reshadi. "Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor." International Journal of Quantum Information 17, no. 05 (2019): 1950048. http://dx.doi.org/10.1142/s0219749919500485.

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In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quan

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6

G., Hemanth Kumar, Gopi K., Gowtham P., and Naveen Balaji G. "Area Efficient Full Subtractor Based on Static 125nm CMOS Technology." International Journal of Trend in Scientific Research and Development 2, no. 6 (2018): 1371–74. https://doi.org/10.31142/ijtsrd18860.

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A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed wit

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7

Cheng, Kai-Wen, and Chien-Cheng Tseng. "Quantum full adder and subtractor." Electronics Letters 38, no. 22 (2002): 1343. http://dx.doi.org/10.1049/el:20020949.

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8

FathimaThuslim, A. "A Novel Design of SET-CMOS Half Subtractor and Full Subtractor." International Journal of Computer Applications 114, no. 12 (2015): 33–37. http://dx.doi.org/10.5120/20032-2134.

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9

Kaur, Sanmukh. "All-optical binary full subtractor using logic operations based on nonlinear properties of semiconductor optical amplifier." Journal of Nonlinear Optical Physics & Materials 25, no. 01 (2016): 1650003. http://dx.doi.org/10.1142/s021886351650003x.

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We propose a new and potentially integrable scheme for the realization of an all-optical binary full subtractor employing two half-subtractors and an additional OR gate. The half-subtractor comprises an XOR gate, an AND gate, and a NOT gate. The XOR gate is realized using semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometer (MZI). The AND, OR, and NOT gates are based on nonlinear properties of semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a borrow bit from the previous less significant bit order position. In our proposed design,

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10

Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power

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K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power

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12

Mahajan, Rita. "Design of Fault Tolerant Full Adder and Full Subtractor." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (2018): 292–301. http://dx.doi.org/10.22214/ijraset.2018.4053.

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13

Rebecca Florance, D., B. Prabhakar, and Manoj Kumar Mishra. "Design and Implementation of ALU Using Graphene Nanoribbon Field-Effect Transistor and Fin Field-Effect Transistor." Journal of Nanomaterials 2022 (July 1, 2022): 1–17. http://dx.doi.org/10.1155/2022/3487853.

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Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry

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14

Rupsa Roy, Swarup Sarkar,. "QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology." Psychology and Education Journal 58, no. 2 (2021): 813–23. http://dx.doi.org/10.17762/pae.v58i2.1916.

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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, c

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15

Fahrezi, Tommy Fadel, and Yoana Nurul Asri. "Pembuatan Alat Simulasi Trainer Adder dan Subtractor." Jurnal Pendidikan Fisika dan Sains (JPFS) 2, no. 2 (2019): 72–79. http://dx.doi.org/10.52188/jpfs.v2i2.72.

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Pada dunia pendidikan khususnya elektronika memerlukan alat penunjang praktik seperti alat praktik rangkaian digital salah satunya ialah trainer. Dasar dari pembentukan sistem digital trainer adalah gerbang logika. Rangkaian digital terdiri dari sekelompok gerbang logika, yang beroperasi dalam bilangan biner. Untuk membuat trainer ini di butuhkan gerbang logika. Gerbang logika yang dipergunakan untuk membuat trainer adder dan subtractor yaitu: Inverting Gate, AND Gate, OR Gate, dan Exclusive-OR Gate. Untuk menjalankan trainer adder dan subtractor ini dibutuhkan tegangan 220 VAC dan menghasilka

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16

Vahabi, Mohsen, Pavel Lyakhov, and Ali Newaz Bahar. "Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology." Applied Sciences 11, no. 18 (2021): 8717. http://dx.doi.org/10.3390/app11188717.

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One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite

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17

Abdullah-Al-Shafi, Md, and Ali Newaz Bahar. "An Architecture of 2-Dimensional 4-Dot 2-Electron QCA Full Adder and Subtractor with Energy Dissipation Study." Active and Passive Electronic Components 2018 (September 24, 2018): 1–10. http://dx.doi.org/10.1155/2018/5062960.

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Quantum-dot cellular automata (QCA) is the beginning of novel technology and is capable of an appropriate substitute for orthodox semiconductor transistor technology in the nanoscale extent. A competent adder and subtractor circuit can perform a substantial function in devising arithmetic circuits. The future age of digital techniques will exercise QCA as preferred nanotechnology. The QCA computational procedures will be simplified with an effective full adder and subtractor circuit. The deficiencies of variations and assembly still endure as a setback in QCA based outlines, and being capricio

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18

Altarawneh, Ziyad, and Mutaz Al-Tarawneh. "Improved QCA-Based Full Adder/Subtractor Structures." International Review of Electrical Engineering (IREE) 16, no. 4 (2021): 391. http://dx.doi.org/10.15866/iree.v16i4.20525.

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19

Bomble, Laëtitia, David Lauvergnat, Françoise Remacle, and Michèle Desouter-Lecomte. "Controlled full adder–subtractor by vibrational computing." Physical Chemistry Chemical Physics 12, no. 48 (2010): 15628. http://dx.doi.org/10.1039/c003687k.

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20

SIVAKUMAR, S., B. VYSHNAVI NANDAN, Y. TEJASWINI, and D. SURESH KUMAR REDDY. "HYBRID FULL SUBTRACTOR CIRCUIT USING FULL SWING XOR-XNOR CELL." International Journal of Advanced Scientific Technologies in Engineering and Management Sciences 7, no. 3 (2021): 8. http://dx.doi.org/10.22413/ijastems/2020/v7/i3/1.

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21

Wang, Yanfeng, Junwei Sun, Xuncai Zhang, and Guangzhao Cui. "Full Adder and Full Subtractor Operations by DNA Self-Assembly." Advanced Science Letters 4, no. 2 (2011): 383–90. http://dx.doi.org/10.1166/asl.2011.1251.

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22

Maji, Kajal, and Kousik Mukherjee. "Design and analysis of all optical 2D Photonic crystals based full subtractor." Journal of Integrated Circuits and Systems 19, no. 3 (2024): 1–6. https://doi.org/10.29292/jics.v19i3.865.

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The all-optical subtractor is a crucial component of optical computation. In this paper, an all-optical full subtractor using 2-dimensional photonic crystals has been proposed and designed. The proposed structure operates on the principle of the interference method and it is simulated using the Finite-Difference Time-Domain (FDTD) method. To analyze the structure, we have determined the contrast ratio and amplitude modulation. The contrast ratio (CR) is 28.24 dB and the amplitude modulation (AM) is 0.504 dB for the Difference output, while for the Borrow output of the full subtractor, the CR i

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23

Kumar, G. Hemanth, K. Gopi, and P. Gowtham G. Naveen Balaji. "Area Efficient Full Subtractor Based on Static 125nm CMOS Technology." International Journal of Trend in Scientific Research and Development Volume-2, Issue-6 (2018): 1371–74. http://dx.doi.org/10.31142/ijtsrd18860.

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24

Sadeghi, Mostafa, Keivan Navi, and Mehdi Dolatshahi. "A Novel Full Subtractor /Full Adder Design in Quantum Cellular Automata." Majlesi Journal of Electrical Engineering 15, no. 1 (2021): 33–37. http://dx.doi.org/10.52547/mjee.15.1.33.

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25

Zivarian, Hossein, and Abbas Zarifkar. "Electro-optical full-adder/full-subtractor based on graphene–silicon switches." Journal of Nanophotonics 12, no. 01 (2018): 1. http://dx.doi.org/10.1117/1.jnp.12.016022.

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26

Haghparast, Majid, and Ali Bolhassani. "Optimized parity preserving quantum reversible full adder/subtractor." International Journal of Quantum Information 14, no. 03 (2016): 1650019. http://dx.doi.org/10.1142/s0219749916500192.

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Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible full adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversib

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Gupta, Roshani, Rockey Gupta, and Susheel Sharma. "High performance full subtractor using floating-gate MOSFET." Microelectronic Engineering 162 (August 2016): 75–78. http://dx.doi.org/10.1016/j.mee.2016.05.011.

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28

Sadeghi, Mostafa, Keivan Navi, and Mehdi Dolatshahi. "Novel efficient full adder and full subtractor designs in quantum cellular automata." Journal of Supercomputing 76, no. 3 (2019): 2191–205. http://dx.doi.org/10.1007/s11227-019-03073-4.

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Zoka, Saeid, and Mohammad Gholami. "A novel efficient full adder–subtractor in QCA nanotechnology." International Nano Letters 9, no. 1 (2018): 51–54. http://dx.doi.org/10.1007/s40089-018-0256-0.

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Seyedi, Saeid, and Hatam Abdoli. "Efficient design and implementation of approximate FA, FS, and FA/S circuits for nanocomputing in QCA." PLOS ONE 19, no. 9 (2024): e0310050. http://dx.doi.org/10.1371/journal.pone.0310050.

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Recently, there has been a lot of research in Quantum Cellular Automata (QCA) technology because it promises low power consumption, low complexity, low latency, and compact space. Simultaneously, approximate arithmetic, a new paradigm in computing, streamlines the computational process and emerges as a low-power, high-performance design approach for arithmetic circuits. Furthermore, the XOR gate has been widely used in digital design and is a basic building block that can be used in many upcoming technologies. The full adder (FA) circuit is a key component of QCA technology and is utilized in

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31

Gassoumi, Ismail, Lamjed Touil, and Abdellatif Mtibaa. "An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation." Journal of Electrical and Computer Engineering 2021 (January 7, 2021): 1–9. http://dx.doi.org/10.1155/2021/8856399.

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The continuous market demands for high performance and energy-efficient computing systems have steered the computational paradigm and technologies towards nanoscale quantum-dot cellular automata (QCA). In this paper, novel energy- and area-efficient QCA-based adder/subtractor designs have been proposed. First, a QCA-based 3-input XOR gate is designed and then a full adder and a full subtractor are realized. The power consumption of the proposed design was tested via the QCAPro estimator tool with different kind of energy (γ = 0.5 Ek, γ = 1.0 Ek, and γ = 1.5 Ek) at temperature T = 2 in Kelvin.

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Gassoumi, Ismail, Lamjed Touil, and Abdellatif Mtibaa. "An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation." Journal of Electrical and Computer Engineering 2021 (January 7, 2021): 1–9. http://dx.doi.org/10.1155/2021/8856399.

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The continuous market demands for high performance and energy-efficient computing systems have steered the computational paradigm and technologies towards nanoscale quantum-dot cellular automata (QCA). In this paper, novel energy- and area-efficient QCA-based adder/subtractor designs have been proposed. First, a QCA-based 3-input XOR gate is designed and then a full adder and a full subtractor are realized. The power consumption of the proposed design was tested via the QCAPro estimator tool with different kind of energy (γ = 0.5 Ek, γ = 1.0 Ek, and γ = 1.5 Ek) at temperature T = 2 in Kelvin.

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Kumar, Santosh, Lokendra Singh, Sanjeev Kumar Raghuwanshi, and Nan-Kuang Chen. "Design of Full-Adder and Full-Subtractor Using Metal-Insulator-Metal Plasmonic Waveguides." Plasmonics 12, no. 4 (2016): 987–97. http://dx.doi.org/10.1007/s11468-016-0350-y.

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Margulies, David, Galina Melman, and Abraham Shanzer. "A Molecular Full-Adder and Full-Subtractor, an Additional Step toward a Moleculator." Journal of the American Chemical Society 128, no. 14 (2006): 4865–71. http://dx.doi.org/10.1021/ja058564w.

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35

SinghNarwariya, Anand, and Shyam Akashe. "Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique." International Journal of Computer Applications 110, no. 9 (2015): 45–49. http://dx.doi.org/10.5120/19348-1071.

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Mirizadeh, Seyyed Mohammad Amir, and Parvaneh Asghari. "Fault-tolerant quantum reversible full adder/subtractor: Design and implementation." Optik 253 (March 2022): 168543. http://dx.doi.org/10.1016/j.ijleo.2021.168543.

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37

Khajeheian, Niloofar, Jasem Jamali, Mohammadhossein Fatehi-Dindarlou, and Mehdi Taghizadeh. "An all optical full subtractor based on nonlinear photonic crystals." Optik 245 (November 2021): 167751. http://dx.doi.org/10.1016/j.ijleo.2021.167751.

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Umadevi, Gurram, Kanaka Durga Ganapavarapu, and Chandra Sekhar Paidimarry. "Area Efficient Full Subtractor Design for Quantum-Dot Cellular Automata." International Journal of Electrical and Electronics Engineering 11, no. 12 (2024): 53–60. https://doi.org/10.14445/23488379/ijeee-v11i12p105.

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Arabani, Shiva Rahbar, Mohammad Reza Reshadinezhad, and Majid Haghparast. "Design of a parity preserving reversible full adder/subtractor circuit." International Journal of Computational Intelligence Studies 7, no. 1 (2018): 19. http://dx.doi.org/10.1504/ijcistudies.2018.090164.

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Haghparast, Majid, Mohammad Reza Reshadinezhad, and Shiva Rahbar Arabani. "Design of a parity preserving reversible full adder/subtractor circuit." International Journal of Computational Intelligence Studies 7, no. 1 (2018): 19. http://dx.doi.org/10.1504/ijcistudies.2018.10011247.

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Montaser, Rasha, Ahmed Younes, and Mahmoud Abdel-Aty. "New Design of Reversible Full Adder/Subtractor Using R Gate." International Journal of Theoretical Physics 58, no. 1 (2018): 167–83. http://dx.doi.org/10.1007/s10773-018-3921-1.

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Mosleh, Mohammad. "A Novel Full Adder/Subtractor in Quantum-Dot Cellular Automata." International Journal of Theoretical Physics 58, no. 1 (2018): 221–46. http://dx.doi.org/10.1007/s10773-018-3925-x.

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Kumar, S. Naresh, and Dr Mahesh Kaumr Porwal. "EMBEDDED SYSTEM BASED 1-BIT FULL SUBTRACTOR FOR ARITHMETIC APPLICATIONS." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 11, no. 3 (2020): 2825–37. http://dx.doi.org/10.61841/turcomat.v11i3.14587.

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In today's VLSI design, static or leakage power consumption is a crucial metric due to component shrinkage. This research proposes and compares a 10-transistor 1-bit complete circuit to alternatives that employ 20 and 14 transistors.Microwind 3.1, a CAD program, was utilized for every circuit simulation.Reductor layout for feature size The 90nm technology has been applied to determine the values of certain parameters.The energy efficiency of the suggested 10-transistor complete subtractor is higher than that of its competitors.

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Sadeq, Salma Ali, Mohsen Hayati, and Saba Khosravi. "High Transmission All-Optical Combinational Logic Circuits Based on a Nanoring Multi-Structure at 1.31 µm." Micromachines 14, no. 10 (2023): 1892. http://dx.doi.org/10.3390/mi14101892.

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The main purpose of this study is to design combinational logic gates based on a novel configuration of insulator–metal–insulator (IMI) nanoring plasmonic waveguides. Plasmonic logic gates are half adder, full adder, half subtractor, full subtractor, and one-bit comparator and are realized in one structure. The performance of the logic circuits is based on constructive and destructive interferences between the input and control signals. The transmission threshold value is assumed to be 0.35 at the resonance wavelength of 1.310 μm. The transmission spectrum, contrast loss (CL), insertion loss (

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45

Vahabi, Mohsen, Ehsan Rahimi, Pavel Lyakhov, Ali Newaz Bahar, Khan A. Wahid, and Akira Otsuki. "Novel Quantum-Dot Cellular Automata-Based Gate Designs for Efficient Reversible Computing." Sustainability 15, no. 3 (2023): 2265. http://dx.doi.org/10.3390/su15032265.

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Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due to the correspondence between features of reversible and QCA circuits. This work aims to push forward the state-of-the-art of the QCA-based reversible circuits implementation by proposing a novel QCA design of a reversible full adder\full subtractor (FA\FS). At first, we consider an efficient XOR-gate, and based on this, new QCA circuit layouts of Feynman, Toffoli, Peres, PQR, TR, RUG, URG,

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Maity, Heranmoy, Mousam Chatterjee, Susmita Biswas, et al. "A New Approach to Design of Cost-Efficient Reversible Quantum Dual-Full Adder and Subtractor." International Journal of Mathematical, Engineering and Management Sciences 9, no. 2 (2024): 341–51. http://dx.doi.org/10.33889/ijmems.2024.9.2.018.

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This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innov

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Choubey, Sonika, and Rajesh Kumar Paul. "Design of Controlled Adder /Subtractor Cell Using Shannon Based Full Adder." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 02 (2015): 738–42. http://dx.doi.org/10.15662/ijareeie.2015.0402033.

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Basha, M. Mahaboob, K. Venkata Ramanaiah, and P. Ramana Reddy. "Design of CMOS full subtractor using 10T for object detection application." International Journal of Reasoning-based Intelligent Systems 10, no. 3/4 (2018): 286. http://dx.doi.org/10.1504/ijris.2018.096223.

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Reddy, P. Ramana, K. Venkata Ramanaiah, and M. Mahaboob Basha. "Design of CMOS full subtractor using 10T for object detection application." International Journal of Reasoning-based Intelligent Systems 10, no. 3-4 (2018): 286. http://dx.doi.org/10.1504/ijris.2018.10017512.

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Sun, DeGui. "Butterfly interconnection implementation for an n-bit parallel full adder/subtractor." Optical Engineering 31, no. 7 (1992): 1568. http://dx.doi.org/10.1117/12.57689.

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