Relevant bibliographies by topics / Fully-depleted silicon-on-insulator (FD-SOI)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Fully-depleted silicon-on-insulator (FD-SOI)'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 May 2024

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Journal articles on the topic "Fully-depleted silicon-on-insulator (FD-SOI)"

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Kuzmicz, Wieslaw. "Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies." Electronics 10, no. 15 (July 27, 2021): 1800. http://dx.doi.org/10.3390/electronics10151800.

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Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.
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Goffioul, Michael, Gilles Dambrine, Danielle Vanhoenacker, and Jean-Pierre Raskin. "Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs." Journal of Telecommunications and Information Technology, no. 3-4 (December 30, 2000): 72–80. http://dx.doi.org/10.26636/jtit.2000.3-4.25.

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The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD) and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lengths and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 um FD SOI n-MOSFETs with a total gate width of 100 um present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for Vds=0.75
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Maleville, Christophe, Eric Neyret, Daniel Delprat, and Ludovic Ecarnot. "High Temperature RTP Application in SOI Manufacturing." Materials Science Forum 573-574 (March 2008): 61–74. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.61.

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Significant performance enhancements are offered by silicon on insulator (SOI) or strained silicon, SOI being adopted for advanced devices in sustaining Moore’s law. Sub-45 nm device options are including fully depleted (FD) devices, that are stressing even more specifications for thickness uniformity. Nano-uniformity, considering thickness variation contributions from device level to wafer scale, has been introduced in substrate optimization and latest Unibond products are verifying FD requirements. Rapid Thermal Processing (RTP) based surface smoothing has been introduced in Unibond processing to combine thickness control and product quality requirements.
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Xu, Hui Fang, Guo Wei Cui, Yong Li, and Chao He. "Two-dimensional analytical model for fully depleted SOI MOSFETs with vertical trapezoid doping including effects of the interface trapped charges." Japanese Journal of Applied Physics 62, no. 12 (November 24, 2023): 124001. http://dx.doi.org/10.35848/1347-4065/ad0746.

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Abstract The two-dimensional (2D) potential distribution for vertical trapezoidal doping thin-body fully depleted (FD) silicon-on-insulator (SOI) devices is derived by adopting the evanescent mode analysis method, in which the 2D effects in gate oxide region, channel region and buried oxide region are taken into account. Moreover, the effects of interface trapped charge are considered. Using this potential model, the subthreshold performance of the device including subthreshold current, and subthreshold swing under various conditions have been studied. The result shows that the analytical model is good agreement with the simulated results. Therefore, it provides a feasible way of developing new 2D models for vertical trapezoidal doping thin-body FD SOI devices. Besides offering the physical insight into device physics, the analytical model provides the basic designing guidance for vertical trapezoidal doping thin-body FD SOI devices.
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Junior, Nilton Graziano, Jeverson Cardoso da Silva, Everson Martins, and Maria Glória Caño De Andrade. "UTBB FD-SOI MOSFET with SELBOX in DTMOS Configuration." Journal of Integrated Circuits and Systems 17, no. 3 (January 25, 2023): 1–5. http://dx.doi.org/10.29292/jics.v17i3.641.

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Abstract— For the first time, Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) n-channel with Dynamic Threshold MOS configuration (DTMOS) using the SELBOX (Selective Buried OXide) substrate will be analyzed. The drain and substrate current, transconductance (gm) and Subthreshold Slope (SS) will be compared in the DTMOS mode and the standard biasing configuration for different gap width (WGAP) of SELBOX. Additionally, the output conductance and the transconductance gain also studied through numerical simulations. The results indicate that the SELBOX structure in DTMOS mode is competitive candidates for analog applications.
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Itocazu, V. T., K. R. A. Sasaki, V. Sonnenberg, J. A. Martino, E. Simoen, and C. Claeys. "Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation." Journal of Integrated Circuits and Systems 12, no. 2 (December 28, 2017): 101–6. http://dx.doi.org/10.29292/jics.v12i2.458.

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This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.
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Ballo, Andrea, Alfio Dario Grasso, Salvatore Pennisi, and Chiara Venezia. "High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS." Journal of Low Power Electronics and Applications 10, no. 3 (September 3, 2020): 27. http://dx.doi.org/10.3390/jlpea10030027.

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Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.
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Kevkić, Tijana S., Vojkan R. Nikolić, Vladica S. Stojanović, Dragana D. Milosavljević, and Slavica J. Jovanović. "Modeling electrostatic potential in FDSOI MOSFETS: An approach based on homotopy perturbations." Open Physics 20, no. 1 (January 1, 2022): 106–16. http://dx.doi.org/10.1515/phys-2022-0012.

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Abstract Modeling of the electrostatic potential for fully depleted (FD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is presented in this article. The modeling is based on the analytical solution of two-dimensional Poisson’s equation obtained by using the homotopy perturbation method (HPM). The HPM with suitable boundary conditions results in the so-called HPM solution in general and closed-form, independent of the surface potential. The HPM solution has been applied in modeling the output characteristics of the FDSOI MOSFET, which show good agreement compared with the numerical results.
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Ragonese, Egidio. "Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies." Applied Sciences 12, no. 4 (February 17, 2022): 2103. http://dx.doi.org/10.3390/app12042103.

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This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs.
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Fan, Linjie, Jinshun Bi, Kai Xi, and Gangping Yan. "Investigation of Radiation Effects on FD-SOI Hall Sensors by TCAD Simulations." Sensors 20, no. 14 (July 16, 2020): 3946. http://dx.doi.org/10.3390/s20143946.

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This work investigates the responses of the fully-depleted silicon-on-insulator (FD-SOI) Hall sensors to the three main types of irradiation ionization effects, including the total ionizing dose (TID), transient dose rate (TDR), and single event transient (SET) effects. Via 3D technology computer aided design (TCAD) simulations with insulator fixed charge, radiation, heavy ion, and galvanomagnetic transport models, the performances of the transient current, Hall voltage, sensitivity, efficiency, and offset voltage have been evaluated. For the TID effect, the Hall voltage and sensitivity of the sensor increase after irradiation, while the efficiency and offset voltage decrease. As for TDR and SET effects, when the energy deposited on the sensor during a nuclear explosion or heavy ion injection is small, the transient Hall voltage of the off-state sensor first decreases and then returns to the initial value. However, if the energy deposition is large, the transient Hall voltage first decreases, then increases to a peak value and decreases to a fixed value. The physical mechanisms that produce different trends in the transient Hall voltage have been analyzed in detail.
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Dissertations / Theses on the topic "Fully-depleted silicon-on-insulator (FD-SOI)"

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Shin, Minju. "Caractérisation électrique et modélisation des transistors FDSOI sub-22nm." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT098/document.

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Parmi les architectures candidates pour les générations sub-22nm figurent les transistors sur silicium sur isolant (SOI). A cette échelle, les composants doivent intégrer des films isolants enterrés (BOX) et des canaux de conduction (Body) ultra-minces. A ceci s'ajoute l'utilisation d'empilements de grille avancés (diélectriques à haute permittivité / métal de grille) et une ingénierie de la contrainte mécanique avec l'utilisation d'alliages SiGe pour le canal des transistors de type P. La mise au point d'une telle technologie demande qu'on soit capable d'extraire de façon non destructive et avec précision la qualité du transport électronique et des interfaces, ainsi que les valeurs des paramètres physiques (dimensions et dopages), qui sont obtenues effectivement en fin de fabrication. Des techniques d'extraction de paramètres ont été développées au cours du temps. L'objectif de cette thèse est de reconsidérer et de faire évoluer ces techniques pour les adapter aux épaisseurs extrêmement réduites des composants étudiés. Elle combine mesures approfondies et modélisation en support. Parmi les résultats originaux obtenus au cours de cette thèse, citons notamment l'adaptation de la méthode split CV complète qui permet désormais d'extraire les paramètres caractérisant l'ensemble de l'empilement SOI, depuis le substrat et son dopage jusqu'à la grille, ainsi qu'une analyse extrêmement détaillée du transport grâce à des mesures en régime de couplage grille arrière à température variable ou l'exploitation de la magnétorésistance de canal depuis le régime linéaire jusqu'en saturation. Le mémoire se termine par une analyse détaillée du bruit basse fréquence
Silicon on insulator (SOI) transistors are among the best candidates for sub-22nm technology nodes. At this scale, the devices integrate extremely thin buried oxide layers (BOX) and body. They also integrate advanced high-k dielectric / metal gate stacks and strain engineering is used to improve transport properties with, for instance, the use of SiGe alloys in the channel of p-type MOS transistors. The optimization of such a technology requires precise and non-destructive experimental techniques able to provide information about the quality of electron transport and interface quality, as well as about the real values of physical parameters (dimensions and doping level) at the end of the process. Techniques for parameter extraction from electrical characteristics have been developed over time. The aim of this thesis work is to reconsider these methods and to further develop them to account for the extremely small dimensions used for sub-22nm SOI generations. The work is based on extended characterization and modelling in support. Among the original results obtained during this thesis, special notice should be put on the adaptation of the complete split CV method which is now able to extract the characteristic parameters for the entire stack, from the substrate and its doping level to the gate stack, as well as an extremely detailed analysis of electron transport based on low temperature characterization in back-gate electrostatic coupling conditions or the exploitation of channel magnetoresistance from the linear regime of operation to saturation. Finally, a detailed analysis of low-frequency noise closes this study
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Malherbe, Victor. "Multi-scale modeling of radiation effects for emerging space electronics : from transistors to chips in orbit." Thesis, Aix-Marseille, 2018. http://www.theses.fr/2018AIXM0753/document.

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En raison de leur impact sur la fiabilité des systèmes, les effets du rayonnement cosmique sur l’électronique ont été étudiés dès le début de l’exploration spatiale. Néanmoins, de récentes évolutions industrielles bouleversent les pratiques dans le domaine, les technologies standard devenant de plus en plus attrayantes pour réaliser des circuits durcis aux radiations. Du fait de leurs fréquences élevées, des nouvelles architectures de transistor et des temps de durcissement réduits, les puces fabriquées suivant les derniers procédés CMOS posent de nombreux défis. Ce travail s’attelle donc à la simulation des aléas logiques permanents (SEU) et transitoires (SET), en technologies FD-SOI et bulk Si avancées. La réponse radiative des transistors FD-SOI 28 nm est tout d’abord étudiée par le biais de simulations TCAD, amenant au développement de deux modèles innovants pour décrire les courants induits par particules ionisantes en FD-SOI. Le premier est principalement comportemental, tandis que le second capture des phénomènes complexes tels que l’amplification bipolaire parasite et la rétroaction du circuit, à partir des premiers principes de semi-conducteurs et en accord avec les simulations TCAD poussées.Ces modèles compacts sont alors couplés à une plateforme de simulation Monte Carlo du taux d’erreurs radiatives (SER) conduisant à une large validation sur des données expérimentales recueillies sous faisceau de particules. Enfin, des études par simulation prédictive sont présentées sur des cellules mémoire et portes logiques en FD-SOI 28 nm et bulk Si 65 nm, permettant d’approfondir la compréhension des mécanismes contribuant au SER en orbite des circuits intégrés modernes
The effects of cosmic radiation on electronics have been studied since the early days of space exploration, given the severe reliability constraints arising from harsh space environments. However, recent evolutions in the space industry landscape are changing radiation effects practices and methodologies, with mainstream technologies becoming increasingly attractive for radiation-hardened integrated circuits. Due to their high operating frequencies, new transistor architectures, and short rad-hard development times, chips manufactured in latest CMOS processes pose a variety of challenges, both from an experimental standpoint and for modeling perspectives. This work thus focuses on simulating single-event upsets and transients in advanced FD-SOI and bulk silicon processes.The soft-error response of 28 nm FD-SOI transistors is first investigated through TCAD simulations, allowing to develop two innovative models for radiation-induced currents in FD-SOI. One of them is mainly behavioral, while the other captures complex phenomena, such as parasitic bipolar amplification and circuit feedback effects, from first semiconductor principles and in agreement with detailed TCAD simulations.These compact models are then interfaced to a complete Monte Carlo Soft-Error Rate (SER) simulation platform, leading to extensive validation against experimental data collected on several test vehicles under accelerated particle beams. Finally, predictive simulation studies are presented on bit-cells, sequential and combinational logic gates in 28 nm FD-SOI and 65 nm bulk Si, providing insights into the mechanisms that contribute to the SER of modern integrated circuits in orbit
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Malherbe, Victor. "Multi-scale modeling of radiation effects for emerging space electronics : from transistors to chips in orbit." Electronic Thesis or Diss., Aix-Marseille, 2018. http://www.theses.fr/2018AIXM0753.

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En raison de leur impact sur la fiabilité des systèmes, les effets du rayonnement cosmique sur l’électronique ont été étudiés dès le début de l’exploration spatiale. Néanmoins, de récentes évolutions industrielles bouleversent les pratiques dans le domaine, les technologies standard devenant de plus en plus attrayantes pour réaliser des circuits durcis aux radiations. Du fait de leurs fréquences élevées, des nouvelles architectures de transistor et des temps de durcissement réduits, les puces fabriquées suivant les derniers procédés CMOS posent de nombreux défis. Ce travail s’attelle donc à la simulation des aléas logiques permanents (SEU) et transitoires (SET), en technologies FD-SOI et bulk Si avancées. La réponse radiative des transistors FD-SOI 28 nm est tout d’abord étudiée par le biais de simulations TCAD, amenant au développement de deux modèles innovants pour décrire les courants induits par particules ionisantes en FD-SOI. Le premier est principalement comportemental, tandis que le second capture des phénomènes complexes tels que l’amplification bipolaire parasite et la rétroaction du circuit, à partir des premiers principes de semi-conducteurs et en accord avec les simulations TCAD poussées.Ces modèles compacts sont alors couplés à une plateforme de simulation Monte Carlo du taux d’erreurs radiatives (SER) conduisant à une large validation sur des données expérimentales recueillies sous faisceau de particules. Enfin, des études par simulation prédictive sont présentées sur des cellules mémoire et portes logiques en FD-SOI 28 nm et bulk Si 65 nm, permettant d’approfondir la compréhension des mécanismes contribuant au SER en orbite des circuits intégrés modernes
The effects of cosmic radiation on electronics have been studied since the early days of space exploration, given the severe reliability constraints arising from harsh space environments. However, recent evolutions in the space industry landscape are changing radiation effects practices and methodologies, with mainstream technologies becoming increasingly attractive for radiation-hardened integrated circuits. Due to their high operating frequencies, new transistor architectures, and short rad-hard development times, chips manufactured in latest CMOS processes pose a variety of challenges, both from an experimental standpoint and for modeling perspectives. This work thus focuses on simulating single-event upsets and transients in advanced FD-SOI and bulk silicon processes.The soft-error response of 28 nm FD-SOI transistors is first investigated through TCAD simulations, allowing to develop two innovative models for radiation-induced currents in FD-SOI. One of them is mainly behavioral, while the other captures complex phenomena, such as parasitic bipolar amplification and circuit feedback effects, from first semiconductor principles and in agreement with detailed TCAD simulations.These compact models are then interfaced to a complete Monte Carlo Soft-Error Rate (SER) simulation platform, leading to extensive validation against experimental data collected on several test vehicles under accelerated particle beams. Finally, predictive simulation studies are presented on bit-cells, sequential and combinational logic gates in 28 nm FD-SOI and 65 nm bulk Si, providing insights into the mechanisms that contribute to the SER of modern integrated circuits in orbit
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Lecat-Mathieu, de Boissac Capucine. "Developing radiation-hardening solutions for high-performance and low-power systems." Electronic Thesis or Diss., Aix-Marseille, 2021. http://www.theses.fr/2021AIXM0413.

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De nouveaux acteurs industriels déploient de larges constellations de satellites, tandis que d'autres domaines comme l'industrie automobile développent des systèmes robustes. Ces systèmes s'appuient sur des technologies avancées, telles que le UTBB FD-SOI, afin d'atteindre les performances nécessaires. La complexité et la vitesse croissantes des systèmes nécessitent une caractérisation précise de ces technologies, ainsi qu'une adaptation des techniques traditionnelles de durcissement. L'objectif est l'étude des effets des radiations dans les technologies FD-SOI et bulk, ainsi que la recherche de mécanismes innovants de durcissement. Une structure intégrée de mesures des SETs, auto-calibrée et conçue grâce à un flot de conception automatisé est d'abord présentée. Elle permet la caractérisation de 4 technologies. La réponse aux radiations des cellules numériques est ensuite évaluée par des tests sous faisceau et par le biais de simulations TCAD, permettant d'étudier l'influence de la tension, de la fréquence de fonctionnement ainsi que l'application d'une tension en face arrière sur la sensibilité. Le TID est également étudié à l'aide d'un bloc de mesure intégré. Les différents résultats sont ensuite utilisés afin de proposer une nouvelle solution de durcissement pour les systèmes sur puce, qui rassemble les précédents blocs de mesure dans un module d'évaluation en temps réel du milieu radiatif. Une unité de gestion de l'énergie pour adapter les modes de fonctionnement au profil de mission. Enfin, une utilisation détournée du détecteur de SETs est proposée dans un contexte de sécurité des systèmes pour détecter et contrer les attaques laser
New actors have accelerated the pace of putting new satellites into orbit, and other domains like the automotive industry are at the origin of this development. These new actors rely on advanced technologies, such as UTBB FD-SOI in order to be able to achieve the necessary performance to accomplish the tasks. Albeit disruptive in terms of intrinsic soft-error resistance, the growing density and complexity of spaceborne and automotive systems require an accurate characterization of technologies, as well as an adaptation of traditional hardening techniques. This PhD focuses on the study of radiation effects in advanced FD-SOI and bulk silicon processes, and on the research of innovative protection mechanisms. A custom, self-calibrating transient measurements structure with automated design flow is first presented, allowing for the characterization of four different technologies during accelerated tests. The soft-error response of 28~nm FD-SOI and 40~nm bulk logic and storage cells is then assessed through beam testing and with the help of TCAD simulations, allowing to study the influence of voltage, frequency scaling and the application of forward body biasing on sensitivity. Total ionizing dose is also investigated through the use of an on-chip monitoring block. The test results are then utilized to propose a novel hardening solution for system on chip, which gathers the monitoring structures into a real-time radiation environment assessment and a power management unit for power mode adjustments. Finally, as an extension of the SET sensors capability, an implementation of radiation monitors in a context of secure systems is proposed to detect and counteract laser attacks
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Book chapters on the topic "Fully-depleted silicon-on-insulator (FD-SOI)"

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"FD-SOI teasers." In Fully Depleted Silicon-On-insulator, 349–52. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00016-1.

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Cristoloveanu, Sorin. "FD-SOI technology." In Fully Depleted Silicon-On-insulator, 3–37. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00006-9.

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Cristoloveanu, Sorin. "Characterization methods for FD-SOI MOSFET." In Fully Depleted Silicon-On-insulator, 201–38. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00012-4.

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Andrieu, F. "Planar fully depleted (FD) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology." In Silicon-On-Insulator (SOI) Technology, 124–66. Elsevier, 2014. http://dx.doi.org/10.1533/9780857099259.1.124.

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Conference papers on the topic "Fully-depleted silicon-on-insulator (FD-SOI)"

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Jafar, Norsyahida, and Norhayati Soin. "Design considerations of Sub-100nm Dual Material Gate Fully Depleted Silicon On Insulator (DMG-FD-SOI)." In 2008 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2008. http://dx.doi.org/10.1109/smelec.2008.4770279.

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"Enhanced comparative performance analysis of Double Gate (DG) MOSFET over Fully Depleted Silicon on Insulator (FD-SOI) MOSFET." In 2022 4th International Conference on Electrical, Computer & Telecommunication Engineering (ICECTE). IEEE, 2022. http://dx.doi.org/10.1109/icecte57896.2022.10114559.

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Ouyang, Liang-Wei, Jill C. Mayeda, Clint Sweeney, Gokul Somasundaram, Donald Y. C. Lie, and Jerry Lopez. "A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) CMOS." In 2023 Sixth International Symposium on Computer, Consumer and Control (IS3C). IEEE, 2023. http://dx.doi.org/10.1109/is3c57901.2023.00067.

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Tabashum, Labiba, Zisan Ibrahim, and Safayat-Al Imam. "A Comparative Analysis of High-k Gate Dielectrics on 30nm Fully Depleted Silicon on Insulator (FD SOI) MOSFET and NMOS Devices." In 2023 6th International Conference on Electrical Information and Communication Technology (EICT). IEEE, 2023. http://dx.doi.org/10.1109/eict61409.2023.10427610.

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Rajavendra Reddy, Gaurav, Jin Wallner, Katherina Babich, and Yiorgos Makris. "Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0443.

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Abstract Continued technology scaling has led to exposure of many ‘weak-points’ in the designs fabricated in some of the most advanced technology nodes. Weak-points are certain layout patterns which are found to be sensitive to process non-idealities and have a higher tendency to cause defects. They may be coded in the form of Pattern Matching (PM) rules and included within the Design for Manufacturability Guidelines (DFMGs) to ensure product manufacturability. Often, during Integrated Circuit (IC) design, a trade-off is made between meeting performance specifications and complying with DFMGs. As a result, designs may reach the foundry with some DFMG violations. Fixing such violations generally causes a ‘ripple effect’ where one change requires many changes in other metal layers, making the process tedious. Therefore, providing a ranked list of guidelines to the designers helps them in assessing the criticality of violations, prioritizing, and fixing them accordingly. Past research suggests using diagnosis data to determine the impact of DFMG violations. However, this is a reactive approach wherein DFMGs are ranked only based on their hard-defect causing nature. To make the ranking process more robust, we propose a proactive silicon validation based approach which not only considers the yield loss due to hard-defects but also takes into account the parametric and reliability degradation caused by DFMG violations. We evaluate the effectiveness of the proposed methodology through on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node.
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