Journal articles: 'Fully-depleted silicon-on-insulator (FD-SOI)'

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Kuzmicz, Wieslaw. "Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies." Electronics 10, no. 15 (July 27, 2021): 1800. http://dx.doi.org/10.3390/electronics10151800.

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Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.

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Goffioul, Michael, Gilles Dambrine, Danielle Vanhoenacker, and Jean-Pierre Raskin. "Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs." Journal of Telecommunications and Information Technology, no. 3-4 (December 30, 2000): 72–80. http://dx.doi.org/10.26636/jtit.2000.3-4.25.

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The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD) and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lengths and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 um FD SOI n-MOSFETs with a total gate width of 100 um present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for Vds=0.75

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Maleville, Christophe, Eric Neyret, Daniel Delprat, and Ludovic Ecarnot. "High Temperature RTP Application in SOI Manufacturing." Materials Science Forum 573-574 (March 2008): 61–74. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.61.

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Significant performance enhancements are offered by silicon on insulator (SOI) or strained silicon, SOI being adopted for advanced devices in sustaining Moore’s law. Sub-45 nm device options are including fully depleted (FD) devices, that are stressing even more specifications for thickness uniformity. Nano-uniformity, considering thickness variation contributions from device level to wafer scale, has been introduced in substrate optimization and latest Unibond products are verifying FD requirements. Rapid Thermal Processing (RTP) based surface smoothing has been introduced in Unibond processing to combine thickness control and product quality requirements.

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Xu, Hui Fang, Guo Wei Cui, Yong Li, and Chao He. "Two-dimensional analytical model for fully depleted SOI MOSFETs with vertical trapezoid doping including effects of the interface trapped charges." Japanese Journal of Applied Physics 62, no. 12 (November 24, 2023): 124001. http://dx.doi.org/10.35848/1347-4065/ad0746.

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Abstract The two-dimensional (2D) potential distribution for vertical trapezoidal doping thin-body fully depleted (FD) silicon-on-insulator (SOI) devices is derived by adopting the evanescent mode analysis method, in which the 2D effects in gate oxide region, channel region and buried oxide region are taken into account. Moreover, the effects of interface trapped charge are considered. Using this potential model, the subthreshold performance of the device including subthreshold current, and subthreshold swing under various conditions have been studied. The result shows that the analytical model is good agreement with the simulated results. Therefore, it provides a feasible way of developing new 2D models for vertical trapezoidal doping thin-body FD SOI devices. Besides offering the physical insight into device physics, the analytical model provides the basic designing guidance for vertical trapezoidal doping thin-body FD SOI devices.

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Junior, Nilton Graziano, Jeverson Cardoso da Silva, Everson Martins, and Maria Glória Caño De Andrade. "UTBB FD-SOI MOSFET with SELBOX in DTMOS Configuration." Journal of Integrated Circuits and Systems 17, no. 3 (January 25, 2023): 1–5. http://dx.doi.org/10.29292/jics.v17i3.641.

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Abstract— For the first time, Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) n-channel with Dynamic Threshold MOS configuration (DTMOS) using the SELBOX (Selective Buried OXide) substrate will be analyzed. The drain and substrate current, transconductance (gm) and Subthreshold Slope (SS) will be compared in the DTMOS mode and the standard biasing configuration for different gap width (WGAP) of SELBOX. Additionally, the output conductance and the transconductance gain also studied through numerical simulations. The results indicate that the SELBOX structure in DTMOS mode is competitive candidates for analog applications.

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Itocazu, V. T., K. R. A. Sasaki, V. Sonnenberg, J. A. Martino, E. Simoen, and C. Claeys. "Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation." Journal of Integrated Circuits and Systems 12, no. 2 (December 28, 2017): 101–6. http://dx.doi.org/10.29292/jics.v12i2.458.

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This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

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Ballo, Andrea, Alfio Dario Grasso, Salvatore Pennisi, and Chiara Venezia. "High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS." Journal of Low Power Electronics and Applications 10, no. 3 (September 3, 2020): 27. http://dx.doi.org/10.3390/jlpea10030027.

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Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

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Kevkić, Tijana S., Vojkan R. Nikolić, Vladica S. Stojanović, Dragana D. Milosavljević, and Slavica J. Jovanović. "Modeling electrostatic potential in FDSOI MOSFETS: An approach based on homotopy perturbations." Open Physics 20, no. 1 (January 1, 2022): 106–16. http://dx.doi.org/10.1515/phys-2022-0012.

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Abstract Modeling of the electrostatic potential for fully depleted (FD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is presented in this article. The modeling is based on the analytical solution of two-dimensional Poisson’s equation obtained by using the homotopy perturbation method (HPM). The HPM with suitable boundary conditions results in the so-called HPM solution in general and closed-form, independent of the surface potential. The HPM solution has been applied in modeling the output characteristics of the FDSOI MOSFET, which show good agreement compared with the numerical results.

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Ragonese, Egidio. "Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies." Applied Sciences 12, no. 4 (February 17, 2022): 2103. http://dx.doi.org/10.3390/app12042103.

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This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs.

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Fan, Linjie, Jinshun Bi, Kai Xi, and Gangping Yan. "Investigation of Radiation Effects on FD-SOI Hall Sensors by TCAD Simulations." Sensors 20, no. 14 (July 16, 2020): 3946. http://dx.doi.org/10.3390/s20143946.

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This work investigates the responses of the fully-depleted silicon-on-insulator (FD-SOI) Hall sensors to the three main types of irradiation ionization effects, including the total ionizing dose (TID), transient dose rate (TDR), and single event transient (SET) effects. Via 3D technology computer aided design (TCAD) simulations with insulator fixed charge, radiation, heavy ion, and galvanomagnetic transport models, the performances of the transient current, Hall voltage, sensitivity, efficiency, and offset voltage have been evaluated. For the TID effect, the Hall voltage and sensitivity of the sensor increase after irradiation, while the efficiency and offset voltage decrease. As for TDR and SET effects, when the energy deposited on the sensor during a nuclear explosion or heavy ion injection is small, the transient Hall voltage of the off-state sensor first decreases and then returns to the initial value. However, if the energy deposition is large, the transient Hall voltage first decreases, then increases to a peak value and decreases to a fixed value. The physical mechanisms that produce different trends in the transient Hall voltage have been analyzed in detail.

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ZAFARI, LEILY, JALAL JOMAAH, GERARD GHIBAUDO, and OLIVIER FAYNOT. "ANALYSIS OF SPATIAL AND ENERGY SLOW TRAP PROFILE IN HfO2/SiO2 METAL-OXIDE-SILICON DEVICES BY LOW FREQUENCY NOISE MEASUREMENTS." Fluctuation and Noise Letters 08, no. 02 (June 2008): L99—L105. http://dx.doi.org/10.1142/s0219477508004350.

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A specific model for the low frequency (LF) noise in SiO 2/ HfO 2 metal-oxide-semiconductor devices on fully depleted silicon-on-insulator (FD-SOI) is proposed based on a proper spatial and energy slow trap profile. This model relates the spatial position of the probed traps with the applied vertical electric field in the gate dielectric via their energy distribution and thereby enables to explain the behaviour of LF noise regarding the front and back gate voltages. The dependence of the trap profile and thus the noise level on the interfacial layer thickness is also analysed by the model.

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Kilchytska, Valeriya, Joaquin Alvarado, Otilia Militaru, Guy Berger, and Denis Flandre. "Effects of High–Energy Neutrons on Advanced SOI MOSFETs." Advanced Materials Research 276 (July 2011): 95–105. http://dx.doi.org/10.4028/www.scientific.net/amr.276.95.

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This work discusses the degradations caused by high-energy neutrons in advanced MOSFETs and compares them with damages created by γ-rays reviewing the original researches performed in our laboratory during last years [1-6]. Fully–depleted (FD) Silicon-on-Insulator (SOI) MOSFETs and Multiple-Gate (MuG) FETs with different geometries (notably gate lengths down to 50 nm) have been considered. The impact of radiation on device behavior has been addressed through the variation of threshold voltage (VT), subthreshold slope (S), transconductance maximum (Gmmax) and drain-induced barrier lowering (DIBL). First, it is shown that degradations caused by high-energy neutrons in FD SOI and MuG MOSFETs are largely similar to that caused by γ-rays with similar doses [1,3]. Second, it is revealed that, contrarily to their generally-believed immunity to irradiation [7, 8], very short-channel MuGFETs with thin gate oxide can become extremely sensitive to the total dose effect [2,3]. The possible reason is proposed. Third, a comparative investigation of high-energy neutrons effects on strained and non-strained devices demonstrates a clear difference in their response to high-energy neutrons exposure [6]. Finally, based on simulations and modeling of partially –depleted (PD) SOI CMOS D Flip-Flop, we show how radiation-induced oxide charge and interface states build-up can affect well-known tolerance of SOI devices to transient effects [4,5].

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Fan, Linjie, Jinshun Bi, Kai Xi, Sandip Majumdar, and Bo Li. "Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations." Sensors 20, no. 10 (May 12, 2020): 2751. http://dx.doi.org/10.3390/s20102751.

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This work investigates the behavior of fully depleted silicon-on-insulator (FD-SOI) Hall sensors with an emphasis on their physical parameters, namely the aspect ratio, doping concentration, and thicknesses. Via 3D-technology computer aided design (TCAD) simulations with a galvanomagnetic transport model, the performances of the Hall voltage, sensitivity, efficiency, offset voltage, and temperature characteristics are evaluated. The optimal structure of the sensor in the simulation has a sensitivity of 86.5 mV/T and an efficiency of 218.9 V/WT at the bias voltage of 5 V. In addition, the effects of bias, such as the gate voltage and substrate voltage, on performance are also simulated and analyzed. Optimal structure and bias design rules are proposed, as are some adjustable trade-offs that can be chosen by designers to meet their own Hall sensor requirements.

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Sharma, Rajneesh, Rituraj S. Rathore, and Ashwani K. Rana. "Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET." Journal of Circuits, Systems and Computers 27, no. 04 (December 6, 2017): 1850063. http://dx.doi.org/10.1142/s0218126618500639.

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The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

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Ritter, Philipp. "Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS." International Journal of Microwave and Wireless Technologies 13, no. 6 (February 11, 2021): 523–31. http://dx.doi.org/10.1017/s1759078721000088.

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AbstractNext-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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Panetas-Felouris, Orfeas, and Spyridon Vlassis. "A 3rd-Order FIR Filter Implementation Based on Time-Mode Signal Processing." Electronics 11, no. 6 (March 14, 2022): 902. http://dx.doi.org/10.3390/electronics11060902.

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This paper presents the hardware implementation of a 3rd-order low-pass finite impulse response (FIR) filter based on time-mode signal processing circuits. The filter topology consists of a set of novel building blocks that perform the necessary functions in time-mode including z−1 operation, time addition and time multiplication. The proposed time-mode low-pass FIR filter was designed in a 28 nm Samsung fully-depleted silicon-on-insulator FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate the theoretical analysis. The FIR filter achieves a signal-to-noise-plus-distortion ratio (SNDR) of 38.6 dB at the input frequency of 50 KHz consuming around 200 μW.

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Zhang, Guohe, Junhua Lai, Yali Su, Binhong Li, Bo Li, Jianhui Bu, and Cheng-Fu Yang. "Study on the Thermal Conductivity Characteristics for Ultra-Thin Body FD SOI MOSFETs Based on Phonon Scattering Mechanisms." Materials 12, no. 16 (August 15, 2019): 2601. http://dx.doi.org/10.3390/ma12162601.

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The silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer intensive self-heating effects due to the reduced thermal conductivity of the silicon layer while the feature sizes of devices scale down to the nanometer regime. In this work, analytical models of thermal conductivity considering the self-heating effect (SHE) in ultra-thin body fully depleted (UTB-FD) SOI MOSFETs are presented to investigate the influences of impurity, free and bound electrons, and boundary reflection effects on heat diffusion mechanisms. The thermal conductivities of thin silicon films with different parameters, including temperature, depth, thickness and doping concentration, are discussed in detail. The results show that the thermal dissipation associated with the impurity, the free and bound electrons, and especially the boundary reflection effects varying with position due to phonon scattering, greatly suppressed the heat loss ability of the nanoscale ultra-thin silicon film. The predictive power of the thermal conductivity model is enhanced for devices with sub-10-nm thickness and a heavily doped silicon layer while considering the boundary scattering contribution. The absence of the impurity, the electron or the boundary scattering leads to the unreliability in the model prediction with a small coefficient of determination.

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Dolatpoor Lakeh, Mohammadreza, Jean-Baptiste Kammerer, Enagnon Aguénounon, Dylan Issartel, Jean-Baptiste Schell, Sven Rink, Andreia Cathelin, Francis Calmon, and Wilfried Uhring. "An Ultrafast Active Quenching Active Reset Circuit with 50% SPAD Afterpulsing Reduction in a 28 nm FD-SOI CMOS Technology Using Body Biasing Technique." Sensors 21, no. 12 (June 10, 2021): 4014. http://dx.doi.org/10.3390/s21124014.

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An ultrafast Active Quenching—Active Reset (AQAR) circuit is presented for the afterpulsing reduction in a Single Photon Avalanche Diode (SPAD). The proposed circuit is designed in a 28 nm Fully Depleted Silicon On Insulator (FD-SOI) CMOS technology. By exploiting the body biasing technique, the avalanche is detected very quickly and, consequently, is quenched very fast. The fast quenching decreases the avalanche charges, therefore resulting in the afterpulsing reduction. Both post-layout and experimental results are presented and are highly in accordance with each other. It is shown that the proposed AQAR circuit is able to detect the avalanche in less than 40 ps and reduce the avalanche charge and the afterpulsing up to 50%.

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Giustolisi, Gianluca, Giuseppe Scotti, and Gaetano Palumbo. "Simple and Accurate Model for the Propagation Delay in MCML Gates." Electronics 12, no. 12 (June 15, 2023): 2680. http://dx.doi.org/10.3390/electronics12122680.

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In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively.

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Cristoloveanu, Sorin, Joris Lacord, Sébastien Martinie, Carlos Navarro, Francisco Gamiz, Jing Wan, Hassan Dirani, Kyunghwa Lee, and Alexander Zaslavsky. "A Review of Sharp-Switching Band-Modulation Devices." Micromachines 12, no. 12 (December 11, 2021): 1540. http://dx.doi.org/10.3390/mi12121540.

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This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.

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Ouyang, Liang-Wei, Jill C. Mayeda, Clint Sweeney, Donald Y. C. Lie, and Jerry Lopez. "A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS." Applied Sciences 14, no. 7 (April 6, 2024): 3080. http://dx.doi.org/10.3390/app14073080.

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This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

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Nocera, Claudio, Giuseppe Papotto, and Giuseppe Palmisano. "Two-Path 77-GHz PA in 28-nm FD-SOI CMOS for Automotive Radar Applications." Electronics 11, no. 8 (April 18, 2022): 1289. http://dx.doi.org/10.3390/electronics11081289.

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This paper presents a 77 GHz two path power amplifier (PA) for automotive radar applications. It was fabricated in 28-nm fully depleted silicon-on-insulator CMOS technology, which provides transistors with a transition frequency of about 270 GHz and a general-purpose low cost back-end-of-line. The proposed PA consists of a 50 Ω input buffer followed by two power units, which are made up of a current-reuse common source driver for improved efficiency and a stacked cascode power stage for enhanced output power. A peak detector was also embedded into the PA for output power monitoring. The designed PA achieved a saturated output power as high as 17.4 dBm at 77 GHz with an excellent power added efficiency of 19%, while drawing 150 mA from a 2 V power supply. The core die size was 500 μm × 300 μm.

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Nguyen, Bich-Yen, Philippe Flatresse, Jamie Schaeffer, Franck Arnaud, Souhir Mhira, Vincent Huart, Olivier Weber, Manuel Sellier, and Christophe Maleville. "A Path to Energy Efficiency and Reliability for ICs: Fully Depleted Silicon-on-Insulator (FD-SOI) Devices Offer Many Advantages." IEEE Solid-State Circuits Magazine 10, no. 4 (2018): 24–33. http://dx.doi.org/10.1109/mssc.2018.2867405.

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Schmidt, Alexander, Holger Kappert, and Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000122–33. http://dx.doi.org/10.4071/hiten-ta14.

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Analog circuit realized in a PD-SOI (Partially-Depleted Silicon-on-Insulator) CMOS process for a wide temperature range up to 400 °C are significantly affected by the MOSFET device characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, e.g. intrinsic gain and bandwidth tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that reverse body biasing (RBB) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300 °C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS process by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400 °C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, basic current mirrors, a two-stage operational amplifier and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. The method has also been applied to basic analog circuits. It has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400 °C.

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Schmidt, Alexander, Holger Kappert, and Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing." Journal of Microelectronics and Electronic Packaging 10, no. 4 (October 1, 2013): 171–82. http://dx.doi.org/10.4071/imaps.389.

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Analog circuits realized in a PD-SOI (partially-depleted silicon-on-insulator) CMOS technology for a wide temperature range up to 400°C are significantly affected by the transistor characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, for example, intrinsic gain and bandwidth, tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that RBB (reverse body biasing) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300°C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS technology by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400°C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, current mirrors, a two-stage operational amplifier, and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby, the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. As the method has also been applied to essential analog circuits, it has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400°C.

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Barboni, Leonardo. "Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors." Journal of Low Power Electronics and Applications 10, no. 2 (May 15, 2020): 17. http://dx.doi.org/10.3390/jlpea10020017.

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The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramifications on the field of process modeling, simulation and circuit design.

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Priya, Anjali, Nilesh Anand Srivastava, and Ram Awadh Mishra. "Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics." Journal of Nanotechnology 2019 (March 28, 2019): 1–12. http://dx.doi.org/10.1155/2019/4935073.

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In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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Parisi, Alessandro, Giuseppe Papotto, Egidio Ragonese, and Giuseppe Palmisano. "A 1-V 7th-Order SC Low-Pass Filter for 77-GHz Automotive Radar in 28-nm FD-SOI CMOS." Electronics 10, no. 12 (June 18, 2021): 1466. http://dx.doi.org/10.3390/electronics10121466.

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This paper presents a switched capacitor low-pass filter in a 28-nm fully depleted silicon on insulator CMOS technology for 77-GHz automotive radar applications. It is operated at a power supply as low as 1 V and guarantees 5-dB in-band voltage gain while providing out-of-band attenuation higher than 36 dB and a programmable passband up to 30 MHz. A double sampling technique is adopted, which allows high operating frequency to be achieved while saving power. Moreover, low-voltage biasing and common-mode feedback circuits are exploited to guarantee an almost rail-to-rail output voltage swing. The proposed filter provides an output 1-dB compression point as high as 8.7 dBm with a power consumption of 9 mW. To the authors’ knowledge, this is the first SC-based implementation of a low pass filter for automotive radar applications.

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Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini, and Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors." Electronics 10, no. 17 (August 31, 2021): 2114. http://dx.doi.org/10.3390/electronics10172114.

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This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

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Widmann, Daniel, Markus Grözing, and Manfred Berroth. "High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology." Advances in Radio Science 16 (September 4, 2018): 99–108. http://dx.doi.org/10.5194/ars-16-99-2018.

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Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

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31

Johannsen, Lucas, Claus Kestel, Oliver Griebel, Timo Vogt, and Norbert Wehn. "Partial Order-Based Decoding of Rate-1 Nodes in Fast Simplified Successive-Cancellation List Decoders for Polar Codes." Electronics 11, no. 4 (February 12, 2022): 560. http://dx.doi.org/10.3390/electronics11040560.

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Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. The decoding of Rate-1 nodes belongs to the most complex tasks in SCL decoding. In this paper, we present a new algorithm that largely reduces the number of considered candidates in a Rate-1 node and generate all required candidates in parallel. For this purpose, we use a partial order of the candidate paths to prove that only a specified number of candidates needs to be considered. Further complexity reductions are achieved by an extended threshold-based path exclusion scheme at the cost of negligible error-correction performance loss. We present detailed Application-Specific Integrated Circuit (ASIC) implementation data on a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide-Semiconductor (CMOS) technology for decoders with code length 128. We show that the new decoders outperform state-of-the-art reference decoders. For list size 8, improvements of up to 158.8% and 62.5% in area and energy efficiency are observed, respectively.

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Mayeda, Jill, Donald Y. C. Lie, and Jerry Lopez. "Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT." Electronics 11, no. 5 (February 23, 2022): 683. http://dx.doi.org/10.3390/electronics11050683.

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Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and >20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE > 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and >12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. POUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications.

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Monsees, Tobias, Oliver Griebel, Matthias Herrmann, Dirk Wübben, Armin Dekorsy, and Norbert Wehn. "Minimum-Integer Computation Finite Alphabet Message Passing Decoder: From Theory to Decoder Implementations towards 1 Tb/s." Entropy 24, no. 10 (October 12, 2022): 1452. http://dx.doi.org/10.3390/e24101452.

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In Message Passing (MP) decoding of Low-Density Parity Check (LDPC) codes, extrinsic information is exchanged between Check Node (CNs) and Variable Node (VNs). In a practical implementation, this information exchange is limited by quantization using only a small number of bits. In recent investigations, a novel class of Finite Alphabet Message Passing (FA-MP) decoders are designed to maximize the Mutual Information (MI) using only a small number of bits per message (e.g., 3 or 4 bits) with a communication performance close to high-precision Belief Propagation (BP) decoding. In contrast to the conventional BP decoder, operations are given as discrete-input discrete-output mappings which can be described by multidimensional LUT (mLUTs). A common approach to avoid exponential increases in the size of mLUTs with the node degree is given by the sequential LUT (sLUT) design approach, i.e., by using a sequence of two-dimensional Lookup-Table (LUTs) for the design, leading to a slight performance degradation. Recently, approaches such as Reconstruction-Computation-Quantization (RCQ) and Mutual Information-Maximizing Quantized Belief Propagation (MIM-QBP) have been proposed to avoid the complexity drawback of using mLUTs by using pre-designed functions that require calculations over a computational domain. It has been shown that these calculations are able to represent the mLUT mapping exactly by executing computations with infinite precision over real numbers. Based on the framework of MIM-QBP and RCQ, the Minimum-Integer Computation (MIC) decoder design generates low-bit integer computations that are derived from the Log-Likelihood Ratio (LLR) separation property of the information maximizing quantizer to replace the mLUT mappings either exactly or approximately. We derive a novel criterion for the bit resolution that is required to represent the mLUT mappings exactly. Furthermore, we show that our MIC decoder has exactly the communication performance of the corresponding mLUT decoder, but with much lower implementation complexity. We also perform an objective comparison between the state-of-the-art Min-Sum (MS) and the FA-MP decoder implementations for throughput towards 1 Tb/s in a state-of-the-art 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology. Furthermore, we demonstrate that our new MIC decoder implementation outperforms previous FA-MP decoders and MS decoders in terms of reduced routing complexity, area efficiency and energy efficiency.

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YEH, Wenchang, and Masato Ohya. "Characteristics and deviation of low temperature FD-SOI-MOSFETs using sputtering SiO₂ gate insulator." Japanese Journal of Applied Physics, January 13, 2023. http://dx.doi.org/10.35848/1347-4065/acb2d3.

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Abstract Fully depleted silicon on insulator (FD-SOI) MOSFET using low temperature sputtering SiO2 gate insulator (GI) was fabricated with resistless process without cleanroom and showed a characteristic comparable to that using plasma enhanced CVD. Resultant average characteristics with standard deviations were, field effect mobility µn of 612±37 cm2/Vs and subthreshold swing ss of 135±18 mV/dec. These were compared with our previous single crystal thin-film transistors (TFTs) on glass substrate with µn of 339±116 cm2/Vs and ss of 255±24 mV/dec, and it was cleared that inferior ss in TFTs was originated from bad bottom Si/SiO2 interface quality with a trap density of 1×1012 cm-2V-1. It was also shown that to achieve TFT characteristics the same as the FD-SOI-MOSFET, top interface trap density and bottom interface quality had better lower than 1×1011 cm-2V-1.

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35

Shin, Hyun-Jin, Sunil Babu Eadi, Yeong-Jin An, Tae-Gyu Ryu, Do-woo Kim, Hi-Deok Lee, and Hyuk-Min Kwon. "Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET." Scientific Reports 12, no. 1 (November 2, 2022). http://dx.doi.org/10.1038/s41598-022-22575-5.

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AbstractTunneling field-effect transistors (TFETs) are a promising candidate for the next generation of low-power devices, but their performance is very sensitive to traps near the tunneling junction. This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silicon-on-insulator p-type TFET. Without high-pressure annealing, the typical noise power spectral density exhibited two Lorentzian spectra that were affected by fast and slow trap sites. With high-pressure annealing, the interface trap density related to fast trap sites was reduced. The passivation of traps near the tunneling junction indicates that high-pressure H2 and D2 annealing improves the electrical performance and LFN properties, and it may become a significant and necessary step for realizing integrated TFET technology in the future.

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Artieda, John P., Lionel Trojman, Felice Crupi, and Lars-Åke Ragnarsson. "Caracterización eléctrica de nano-MOSFETs en tecnología SOI." ACI Avances en Ciencias e Ingenierías 4, no. 2 (December 28, 2012). http://dx.doi.org/10.18272/aci.v4i2.107.

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En esta investigación se reporta sobre la extensa caracterización eléctrica realizada, con poca distorsión y mayor fiabilidad, a dispositivos MOSFET de tamaño nanométrico con arquitectura ultra delgada tipo Fully Depleted (FD) en tecnología Silicon-On-Insulator (SOI) para reducir los efectos de canal corto. Se comparan los parámetros de dispositivos tipo nMOS, con tamaño de compuerta 10x1 μm2, con dieléctrico convencional (SiON) y dieléctrico alternativo de alto κ (HfO2). Los parámetros que se extraen son: espesor equivalente de óxido (EOT), voltaje umbral (VT) en función del voltaje de cuerpo SOI (VB), transconductancia (gm), pico de transconductancia (gm,max) y su relación con la movilidad. El objetivo es encontrar si los métodos de caracterización eléctrica clásicos pueden ser aplicables para estos nuevos dispositivos superando los retos y dificultades físicas que impone la tecnología de construcción SOI y demostrar si su funcionamiento es como el de los MOSFET convencionales. Los dispositivos semiconductores analizados fueron provistos por el consorcio IMEC en Bélgica y han sido caracterizados en el nuevo laboratorio de nanoelectrónica de la Universidad San Francisco de Quito (USFQ) en Ecuador.

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Gauthier, Owen, Sébastien Haendler, Quentin Rafhay, and Christoforos Theodorou. "Universality of trap-induced mobility fluctuations between 1/f noise and random telegraph noise in nanoscale FD-SOI MOSFETs." Applied Physics Letters 122, no. 23 (June 5, 2023). http://dx.doi.org/10.1063/5.0152734.

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Low frequency noise (LFN) and random telegraph noise (RTN) are investigated statistically on nanoscale MOSFETs of 28 nm fully depleted silicon-on-insulator technology. The analysis reveals that the mean noise level is well described by the carrier number fluctuations with a correlated mobility fluctuations model. As for the RTN, it is shown that the mean amplitude of signals is driven by correlated mobility fluctuations in strong inversion. The comparison between the extracted parameters of the LFN and RTN analysis demonstrates that the remote Coulomb scattering impact due to the trapped and detrapped charges remains the same on average for this technology, whether it is the average noise spectrum of all devices or the average amplitude of the detected RTN signals.

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38

Torres, Florent, Eric Kerhervé, Andreia Cathelin, and Magali De Matos. "A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications." International Journal of Microwave and Wireless Technologies, August 25, 2020, 1–18. http://dx.doi.org/10.1017/s1759078720001087.

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Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

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39

Mayeda, Jill, Clint Sweeney, Donald Y. C. Lie, and Jerry Lopez. "Broadband High-Efficiency Millimeter-Wave Power Amplifiers in 22-nm CMOS FD-SOI with Fixed and Adaptive Biasing." International Journal of Electrical and Electronic Engineering & Telecommunications., 2022, 385–91. http://dx.doi.org/10.18178/ijeetc.11.6.385-391.

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The design of broadband highly-efficient millimeter-wave (mm-Wave) Power Amplifiers (PA) in 22-nm CMOS FD-SOI (fully depleted silicon-on-insulator) is discussed. One design uses fixed biasing while the other utilizes an adaptive biasing network to improve its Power-Added-Efficiency (PAE) in power backoff. These designs aim to cover the key Fifth-Generation (5G) FR2 (Frequency Range 2) band (e.g., from 24.25 GHz to 43.5 GHz). In measurement, the PAs obtain very broadband 3-dB BW, ranging from 19.1 GHz to 46.5 GHz for the fixed-bias design and 18.8 GHz to 41.9 GHz for the adaptively biased design. The adaptively biased design is able to achieve enhanced output 1-dB compression point (OP1dB) and PAE@P1dB because of its adaptive biasing network. Measurements on the fixed-biased PA at 24/28/37/39 GHz yield max. PAE of 22.2/22.4/19.7/19.8%, and POUT,SAT of 14.9/15.3/14.7/14.7 dBm, with OP1dB of 11.8/11.6/12/11.6 dBm, and PAE@P1dB of 14.1/13.4/14.5/13.5%. Measurements on the adaptively biased PA at 24/28/37/39 GHz yield max. PAE of 20.1/15.2/10.3/7.9%, and POUT,SAT of 14.6/14.2/12.5/11.2 dBm, with improved OP1dB of 13.1/12.3/12.1/11.2 dBm, and PAE@P1dB of 19.1/14.4/10.3/7.9%. Data from body bias voltage VB on the PA performance is also presented. These measurement results are compared with post-layout parasitic-extraction (PEX) simulations, and also against other novel silicon broadband mm-Wave PAs in literature.

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40

Petropoulos, N., X. Wu, A. Sokolov, P. Giounanlis, I. Bashir, A. K. Mitchell, M. Asker, D. Leipold, R. B. Staszewski, and E. Blokhina. "Nanoscale single-electron box with a floating lead for quantum sensing: Modeling and device characterization." Applied Physics Letters 124, no. 17 (April 22, 2024). http://dx.doi.org/10.1063/5.0203421.

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We present an in-depth analysis of a single-electron box (SEB) biased through a floating node technique that is common in charge-coupled devices. The device is analyzed and characterized in the context of single-electron charge sensing techniques for integrated silicon quantum dots (QD). The unique aspect of our SEB design is the incorporation of a metallic floating node, strategically employed for sensing and precise injection of electrons into an electrostatically formed QD. To analyze the SEB, we propose an extended multi-orbital Anderson impurity model (MOAIM), adapted to our nanoscale SEB system, that is used to predict theoretically the behavior of the SEB in the context of a charge sensing application. The validation of the model and the sensing technique has been carried out on a QD fabricated in a fully depleted silicon on insulator process (FD-SOI) on a 22-nm CMOS technology node. We demonstrate the MOAIM's efficacy in predicting the observed electronic behavior and elucidating the complex electron dynamics and correlations in the SEB. The results of our study reinforce the versatility and precision of the model in the realm of nanoelectronics and highlight the practical utility of the metallic floating node as a mechanism for charge injection and detection in integrated QDs. Finally, we identify the limitations of our model in capturing higher order effects observed in our measurements and propose future outlooks to reconcile some of these discrepancies.

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"Ультратонкие скрытые стеки оксидов гафния и алюминия в полевых структурах кремний-на-изоляторе / Попов В.П., Антонов В.А., Ильницкий М.А., Мяконьких А.В., Руденко К.В." Тезисы докладов XIV РОССИЙСКОЙ КОНФЕРЕНЦИИ ПО ФИЗИКЕ ПОЛУПРОВОДНИКОВ «ПОЛУПРОВОДНИКИ-2019», August 20, 2019, 174. http://dx.doi.org/10.34077/semicond2019-174.

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Ультратонкие слои кремния и скрытого окисла (Ultra Thin Body and Buried oxide - UTBB) в структурах кремний-на-изоляторе (КНИ) с эквивалентной толщиной встроенного оксида (Equivalent Oxide Thickness - EOT) менее 10 нм являются перспективными для энергоэффективных высокопроизводительных микросхем на основе полностью обедняемых двухзатворных КНИ полевых транзисторов (two gate fully depleted silicon-on-insulator field effect transistors - 2G FD SOI FETs), работающих в симметричном или асимметричном режиме и для снижения напряжения питания встроенной энергонезависимой памяти (embedded non-volatile memory - е-NVM). Однако снижение толщины диоксида кремния до ЕОТ < 10 нм приводит к появлению разнообразных дефектов в КНИ слое после высокотемпературной обработки за счет перенасыщения оксида атомами водорода и их накопления в газовых блистерах на гетерограницах Si/SiO2, а также растворения сверхтонкого диоксида кремния при высокотемпературном отжиге [1]. Чтобы избежать подобных дефектов в структурах типа UTBB SOI было предложено использовать вместо диоксида кремния более толстый диэлектрик с высокими теплопроводностью и диэлектрической постоянной (high-k) [2]. Минимальное значение EOT = 7.9 нм было получено для стека с аморфным Al2O3 из-за относительно толстых слоев SiO2, нанесенных для достижения низкой плотности состояний (interface states – IFS) на гетерогранице Si/SiO2~ 5x1011eV−1 cm−2 . Кроме того, высокая эффективная плотность отрицательного заряда 3x1012 см−2 сохранялась даже после отжига при 1200o C. Ранее был предложен подход к уменьшению собственного заряда в high- k стеке с помощью диполей на гетерогранице между разнородными диэлектриками [3]. Нам не удалось обнаружить публикаций о поведении стеков из high- k диэлектриков в случае использования их в качестве встроенного окисла в КНИ структурах при высокотемпературных термообработках. Такие КНИ структуры с EOT < 5 нм впервые сформированы нами водородным переносом слоя кремния на пластины кремния со стеками HfO2/Al2O3. Быстрыми термообработками (БТО) при Т > 900о С встроенный заряд снижен до < 1012 см−2 , а подвижность увеличена до 100 см2 /(Вс). Утечки в подложку наблюдаются при полях > 106 В/см. Заметный гистерезис сток-затворных характеристик может быть связан с перезарядкой IFS или диполей на границах раздела и формированием сегнетоэлектрической фазы оксида гафния. С целью разделения этих эффектов проведены эксперименты с различными толщинами и порядком high-k слоев в диэлектрических стеках КНИ структур. Подтверждено присутствие электрических диполей на гетерограницах оксидов металла и кремния, центров захвата и переноса носителей заряда, а также присутствие сегнетоэлектрической фазы в изолирующих слоях [4].

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Journal articles on the topic 'Fully-depleted silicon-on-insulator (FD-SOI)'

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