Relevant bibliographies by topics / Fully Depleted Silicon-on-Insulator (FDSOI)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Fully Depleted Silicon-on-Insulator (FDSOI)'

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Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Fully Depleted Silicon-on-Insulator (FDSOI)"

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Kambham, Ajay Kumar, Dan Flatoff, and Bianzhu Fu. "Application of Atom Probe on Fully Depleted Silicon-On-Insulator (FDSOI) Structures." Microscopy and Microanalysis 22, S3 (2016): 696–97. http://dx.doi.org/10.1017/s1431927616004335.

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Lin, Jyi-Tsong, Yi-Chuen Eng, and Po-Hsieh Lin. "A Novel Nanoscale FDSOI MOSFET with Block-Oxide." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/627873.

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We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI structure is in fact shown to behave similarly to an ultrathin body (UTB) SOI but without the associated disadvantages and technological challenges of the ultrathin film, because a thick Si body allows for reduced sensitivity to self-heating, thereby improving thermal stability.
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Wang, Hanbin, Jinshun Bi, Mengxin Liu, and Tingting Han. "Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure." Electronics 10, no. 13 (2021): 1585. http://dx.doi.org/10.3390/electronics10131585.

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This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.
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Almeida, Luciano M., Katia R. A. Sasaki, M. Aoulaiche, Eddy Simoen, Cor Clayes, and João Antonio Martino. "One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect." Journal of Integrated Circuits and Systems 7, no. 2 (2012): 113–20. http://dx.doi.org/10.29292/jics.v7i2.363.

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This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.
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Litty, Antoine, Sylvie Ortolland, Dominique Golanski, Christian Dutto, Alexandres Dartigues, and Sorin Cristoloveanu. "Towards High-Voltage MOSFETs in Ultrathin FDSOI." International Journal of High Speed Electronics and Systems 25, no. 01n02 (2016): 1640005. http://dx.doi.org/10.1142/s012915641640005x.

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High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.
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Xu, Jingyan, Yang Guo, Ruiqiang Song, Bin Liang, and Yaqing Chi. "Supply Voltage and Temperature Dependence of Single-Event Transient in 28-nm FDSOI MOSFETs." Symmetry 11, no. 6 (2019): 793. http://dx.doi.org/10.3390/sym11060793.

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Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.
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Olejarz, Piotr, Kyoungchul Park, Samuel MacNaughton, Mehmet R. Dokmeci, and Sameer Sonkusale. "0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process." Journal of Low Power Electronics and Applications 2, no. 2 (2012): 155–67. http://dx.doi.org/10.3390/jlpea2020155.

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Wei, Zhaopeng, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Jerome Prouvee, and Benjamin Blampey. "Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits." Active and Passive Electronic Components 2019 (July 4, 2019): 1–9. http://dx.doi.org/10.1155/2019/4578501.

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.
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Lederer, Maximilian, Thomas Kämpfe, Norman Vogel, et al. "Structural and Electrical Comparison of Si and Zr Doped Hafnium Oxide Thin Films and Integrated FeFETs Utilizing Transmission Kikuchi Diffraction." Nanomaterials 10, no. 2 (2020): 384. http://dx.doi.org/10.3390/nano10020384.

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The microstructure of ferroelectric hafnium oxide plays a vital role for its application, e.g., non-volatile memories. In this study, transmission Kikuchi diffraction and scanning transmission electron microscopy STEM techniques are used to compare the crystallographic phase and orientation of Si and Zr doped HfO2 thin films as well as integrated in a 22 nm fully-depleted silicon-on-insulator (FDSOI) ferroelectric field effect transistor (FeFET). Both HfO2 films showed a predominately orthorhombic phase in accordance with electrical measurements and X-ray diffraction XRD data. Furthermore, a stronger texture is found for the microstructure of the Si doped HfO2 (HSO) thin film, which is attributed to stress conditions inside the film stack during crystallization. For the HSO thin film fabricated in a metal-oxide-semiconductor (MOS) like structure, a different microstructure, with no apparent texture as well as a different fraction of orthorhombic phase is observed. The 22 nm FDSOI FeFET showed an orthorhombic phase for the HSO layer, as well as an out-of-plane texture of the [111]-axis, which is preferable for the application as non-volatile memory.
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Yan, Gangping, Jinshun Bi, Gaobo Xu, et al. "Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor." IEEE Access 8 (2020): 154898–905. http://dx.doi.org/10.1109/access.2020.3018714.

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Dissertations / Theses on the topic "Fully Depleted Silicon-on-Insulator (FDSOI)"

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Nier, Olivier. "Development of TCAD modeling for low field electronics transport and strain engineering in advanced Fully Depleted Silicon On Insulator (FDSOI) CMOS transistors." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT141/document.

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La conception des dispositifs nanométriques CMOS apporte de nouveaux défis à la communauté TCAD. En effet, de nos jours, les améliorations des performances des transistors ne sont plus simplement dû à une simple diminution des dimensions des dispositifs, mais aussi à l'introduction de boosters de technologies tels que des nouvelles architectures (FDSOI, trigate), des oxydes de grille à forte permittivité, l'ingénierie de la contrainte ou de nouveaux matériaux de canal (Ge, III-V). Pour faire face à tous ces nouveaux défis technologiques, la modélisation TCAD (Technology Computer Aided Design) est un outil puissant pour guider le développement mais aussi pour réduire les coûts. Dans ce contexte, ce travail de thèse vise à améliorer la modélisation TCAD pour les technologies 28/14 et 10FDSOI, avec une attention particulière sur les impacts des contraintes mécaniques sur leurs performances. Dans un premier temps, les différents mécanismes impactant la mobilité des technologies FDSOI ont été étudiés en détail. Les modèles implémentés dans des outils de simulations avancés (NEGF, Multi subbands Monte Carlo, Kubo-Greenwood) sont étudiés, comparés et des développements du logiciel interne à STMicroelectronics (UTOXPP) sont proposés. Dans un second temps, une approche « top down » a été mis en place. Elle consiste à calibrer les modèles TCAD empiriques non pas sur des mesures mais sur des outils de simulations avancés (Kubo-Greenwood). Les modèles TCAD calibrés montrent de très bons accords avec les mesures de mobilité (split-CV) en variant la température, la polarisation du substrat et l’épaisseur de l’IL (Interfacial layer). Dans un troisième temps, les méthodes utilisées lors de cette thèse pour modéliser les contraintes induites par le procédé de fabrications sont décrites. Enfin, la dernière partie concerne la modélisation TCAD des technologies 28 et 14FDSOI. Des simulations mécaniques sont effectuées pour modéliser les profils de contraintes dans les transistors. Des solutions pour optimiser la configuration des contraintes dans le canal pour ces technologies sont proposées<br>The design of nanoscale CMOS devices brings new challenges to TCAD community. Indeed, nowadays, CMOS performances improvements are not simply due to device scaling but also to the introduction of new technology “boosters” such as new transistors architectures (FDSOI, trigate), high-k dielectric gate stacks, stress engineering or new channel material (Ge, III-V). To face all these new technological challenges, Technology Computer Aided Design (TCAD) is a powerful tool to guide the development of advanced technologies but also to reduce development time and cost. In this context, this PhD work aimed at improving the modeling for 28/14 and 10FDSOI technologies, with a particular attention on mechanical strain impacts. In the first section, a summary of the main models implemented in state of the art device simulators is performed. The limitations and assumptions of these models are highlighted and developments of the in-house STMicroelectronics KG solvers are discussed. In the second section, a “top down” approach has been set-up. It has consisted in using advanced physical-based solvers as a reference for TCAD empirical models calibration. Calibrated TCAD reproduced accurately split-CV mobility measurements varying the temperature, the back bias and the Interfacial Layer (IL) thickness. The third section deals with a description of the methodologies used during this thesis to model stress induced by the process flow. Simulations are compared to nanobeam diffraction (NBD) strain measurements. The use and calibration of available TCAD models to efficiently model the impact of stress on mobility in a large range of stress (up to 2GPa) is also discussed in this section. The last part deals with TCAD modeling of advanced CMOS devices for 28/14 and 10FDSOI technology development. Mechanical simulations are performed to model the stress profile in transistors and several solutions to optimize the stress configuration in sSOI and SiGe-based devices have been presented
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Bartra, Walter Enrique Calienes. "Modelamento do single-Event effiects em circuitos de memória FDSOI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/159203.

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Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e células de memória 6T SRAM feitas com estes dispositivos. Para conseguir isso, foram usadas ferramentas TCAD para simular falhas transientes devido a impacto de íons pesados a nível dispositivo e nível circuito. As simulações neste ambiente tem como vantagem a simulação dos fatos e mecanismos que produz as falhas transientes e seus efeitos nos dispositivos, além de também servir para projetar virtualmente estes dispositivos e caraterizar eles para estas simulações. Neste caso, foram projetados três dispositivos para simulação: um transistor NMOS de 32nm Bulk, um transistor NMOS de 28nm FDSOI e um transistor NMOS de 28nm FDSOI High-K para fazer comparações entre eles. Estes dispositivos foram projetados, caraterizados e testados contra o impacto de íons pesados a níveis dispositivo e circuito. Como resultado obtido, transistor Bulk de 32nm teve, no pior caso, uma carga coletada de 7.57 e 7.19 vezes maior que a carga coletada pelo dispositivo FDSOI de 28nm e FDSOI High-K de 28nm respectivamente atingido pelo mesmo íon pesado de 100MeV-cm2/mg. Com estes dados foi possível modelar o comportamento da carga coletada de ambos dispositivos usando este íon pesado, atingindo os terminais de Fonte e Dreno em distintos lugares e ângulos. Usando a mesma ferramenta e os dados obtidos de carga coletada pelos testes anteriores, foram projetadas células de memória SRAM de 6 transistores. Isso foi para testar elas contra os efeitos do impacto de íons pesados nos transistores NMOS de armazenagem da dados. Neste caso, a Transferência Linear de Energia (LET) do íon necessária para fazer que o dado armazenado na SRAM Bulk mude é 12.8 vezes maior que no caso da SRAM FDSOI e 10 maior no caso da SRAM FDSOI High-K, embora a quantidade de carga coletada necessária para que o dado mude em ambas células seja quase a mesma. Com estes dados foi possível modelar os efeitos dos íons pesados em ambos circuitos, descobrir a Carga Crítica destes e qual é o mínimo LET necessário para que o dado armazenado nestas SRAMs mude.<br>This work shows a comparison of faults due to Single-Event Effects in 28nm Fully Depleted SOI (FDSOI), 28nm FDSOI High-K and 32nm Bulk CMOS devices, and in 6T SRAM memory cells made with these devices. To provide this, was used TCAD tools to simulate transient faults due to heavy ion impacts on device and circuit levels. The simulations in that environment have the advantage to simulate the facts and mechanisms which produce the transient faults and this effects on the electronic devices, it also allow to simulate the virtual device fabrication and to characterize them. In this case, two devices were created for the simulations: a 32nm Bulk NMOS transistor and a 28nm FDSOI NMOS transistor for compare them. These devices were created, characterized and tested against heavy ion impacts at device and circuit levels. The results show that 32nm Bulk transistor has, in the worst case, a collected charge 7.57 and 7.19 times greater than the 28nm FDSOI and 28nm FDSOI High-K respectively collected charge with the same 100MeV-cm2/mg heavy ion. With these data it was possible to model the behavior of the collected charge in both devices with the same heavy-ion, reach the Source and Drain Terminal in different places and angles. Using the same tools and the obtained collected charge data of previous simulations, it was designed 6 transistors SRAM Memory Cells. That is done to test these circuits against the heavy ion effects on the data-storage NMOS transistor. In this case, the necessary Ion Linear Energy Transfer (LET) to flip the Bulk SRAM is 12.8 greater than the FDSOI SRAM and 10 times greater than the FDSOI High- K SRAM case, although the amount of charge to flip the cells is almost the same in both cases. With these data it was possible to model the heavy-ion effects in both circuits, discover the Critical Charge of them and the minimum LET to flips these SRAMs.
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Shin, Minju. "Caractérisation électrique et modélisation des transistors FDSOI sub-22nm." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT098/document.

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Parmi les architectures candidates pour les générations sub-22nm figurent les transistors sur silicium sur isolant (SOI). A cette échelle, les composants doivent intégrer des films isolants enterrés (BOX) et des canaux de conduction (Body) ultra-minces. A ceci s'ajoute l'utilisation d'empilements de grille avancés (diélectriques à haute permittivité / métal de grille) et une ingénierie de la contrainte mécanique avec l'utilisation d'alliages SiGe pour le canal des transistors de type P. La mise au point d'une telle technologie demande qu'on soit capable d'extraire de façon non destructive et avec précision la qualité du transport électronique et des interfaces, ainsi que les valeurs des paramètres physiques (dimensions et dopages), qui sont obtenues effectivement en fin de fabrication. Des techniques d'extraction de paramètres ont été développées au cours du temps. L'objectif de cette thèse est de reconsidérer et de faire évoluer ces techniques pour les adapter aux épaisseurs extrêmement réduites des composants étudiés. Elle combine mesures approfondies et modélisation en support. Parmi les résultats originaux obtenus au cours de cette thèse, citons notamment l'adaptation de la méthode split CV complète qui permet désormais d'extraire les paramètres caractérisant l'ensemble de l'empilement SOI, depuis le substrat et son dopage jusqu'à la grille, ainsi qu'une analyse extrêmement détaillée du transport grâce à des mesures en régime de couplage grille arrière à température variable ou l'exploitation de la magnétorésistance de canal depuis le régime linéaire jusqu'en saturation. Le mémoire se termine par une analyse détaillée du bruit basse fréquence<br>Silicon on insulator (SOI) transistors are among the best candidates for sub-22nm technology nodes. At this scale, the devices integrate extremely thin buried oxide layers (BOX) and body. They also integrate advanced high-k dielectric / metal gate stacks and strain engineering is used to improve transport properties with, for instance, the use of SiGe alloys in the channel of p-type MOS transistors. The optimization of such a technology requires precise and non-destructive experimental techniques able to provide information about the quality of electron transport and interface quality, as well as about the real values of physical parameters (dimensions and doping level) at the end of the process. Techniques for parameter extraction from electrical characteristics have been developed over time. The aim of this thesis work is to reconsider these methods and to further develop them to account for the extremely small dimensions used for sub-22nm SOI generations. The work is based on extended characterization and modelling in support. Among the original results obtained during this thesis, special notice should be put on the adaptation of the complete split CV method which is now able to extract the characteristic parameters for the entire stack, from the substrate and its doping level to the gate stack, as well as an extremely detailed analysis of electron transport based on low temperature characterization in back-gate electrostatic coupling conditions or the exploitation of channel magnetoresistance from the linear regime of operation to saturation. Finally, a detailed analysis of low-frequency noise closes this study
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Baudot, Sophie. "MOSFETs contraints sur SOI : analyse des déformations par diffraction des rayons X et étude des propriétés électriques." Phd thesis, Grenoble, 2010. http://tel.archives-ouvertes.fr/tel-00557963.

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L'introduction d'une contrainte mécanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacité dépend de la géométrie et des règles de dessin du dispositif. L'impact des étapes du procédé de fabrication des transistors (gravure des zones actives, formation de la grille métallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a été mesuré par diffraction des rayons X en incidence rasante (GIXRD). Parallèlement, le gain en performances de MOSFETs sur sSOI a été quantifié par rapport au SOI (100% de gain en mobilité pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain à saturation (IDsat) pour des nMOS courts et étroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi été étudiées. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est démontré par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'épaisseur. Des mesures GIXRD, couplées à des simulations mécaniques, ont permis d'étudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterrée précontrainte (en SiGe ou en nitrure) vers le canal.
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Feki, Anis. "Conception d’une mémoire SRAM en tension sous le seuil pour des applications biomédicales et les nœuds de capteurs sans fils en technologies CMOS avancées." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0018/document.

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L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis<br>Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal
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Ayele, Getenet Tesega. "Developing ultrasensitive and CMOS compatible ISFETs in the BEOL of industrial UTBB FDSOI transistors." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI026/document.

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En exploitant la fonction d’amplification intrinsèque fournie par les transistors UTBB FDSOI, nous avons présenté des ISFET ultra sensibles. L'intégration de la fonctionnalité de détection a été réalisée en back end of line (BEOL), ce qui offre les avantages d'une fiabilité et d'une durée de vie accrues du capteur, d'une compatibilité avec le processus CMOS standard et d'une possibilité d'intégration d'un circuit diviseur capacitif. Le fonctionnement des MOSFETs, sans une polarisation appropriée de la grille avant, les rend vulnérables aux effets de grilles flottantes indésirables. Le circuit diviseur capacitif résout ce problème en polarisant la grille avant tout en maintenant la fonctionnalité de détection sur la même grille par un couplage capacitif au métal commun du BEOL. Par conséquent, le potentiel au niveau du métal BEOL est une somme pondérée du potentiel de surface au niveau de la grille de détection et de la polarisation appliquée au niveau de la grille de contrôle. Le capteur proposé est modélisé et simulé à l'aide de TCAD-Sentaurus. Un modèle mathématique complet a été développé. Il fournit la réponse du capteur en fonction du pH de la solution (entrée du capteur) et des paramètres de conception du circuit diviseur capacitif et du transistor UTBB FDSOI. Dans ce cas, des résultats cohérents ont été obtenus des travaux de modélisation et de simulation, avec une sensibilité attendue de 780 mV / pH correspondant à un film de détection ayant une réponse de Nernst. La modélisation et la simulation du capteur proposé ont également été validées par une fabrication et une caractérisation du capteur de pH à grille étendue avec validation de son concept. Ces capteurs ont été développés par un traitement séparé du composant de détection de pH, qui est connecté électriquement au transistor uniquement lors de la caractérisation du capteur. Ceci permet une réalisation plus rapide et plus simple du capteur sans avoir besoin de masques et de motifs par lithographie. Les capteurs à grille étendue ont présenté une sensibilité de 475 mV/pH, ce qui est supérieur aux ISFET de faible puissance de l'état de l’art. Enfin, l’intégration de la fonctionnalité de détection directement dans le BEOL des dispositifs FDSOI UTBB a été poursuivie. Une sensibilité expérimentale de 730 mV/pH a été obtenue, ce qui confirme le modèle mathématique et la réponse simulée. Cette valeur est 12 fois supérieure à la limite de Nernst et supérieure aux capteurs de l'état de l’art. Les capteurs sont également évalués pour la stabilité, la résolution, l'hystérésis et la dérive dans lesquels d'excellentes performances sont démontrées<br>Exploiting the intrinsic amplification feature provided by UTBB FDSOI transistors, we demonstrated ultrahigh sensitive ISFETs. Integration of the sensing functionality was made in the BEOL which gives the benefits of increased reliability and life time of the sensor, compatibility with the standard CMOS process, and possibility for embedding a capacitive divider circuit. Operation of the MOSFETs without a proper front gate bias makes them vulnerable for undesired floating body effects. The capacitive divider circuit addresses these issues by biasing the front gate simultaneously with the sensing functionality at the same gate through capacitive coupling to a common BEOL metal. Therefore, the potential at the BEOL metal would be a weighted sum of the surface potential at the sensing gate and the applied bias at the control gate. The proposed sensor is modeled and simulated using TCAD-Sentaurus. A complete mathematical model is developed which provides the output of the sensor as a function of the solution pH (input to the sensor), and the design parameters of the capacitive divider circuit and the UTBB FDSOI transistor. In that case, consistent results have been obtained from the modeling and simulation works, with an expected sensitivity of 780 mV/pH corresponding to a sensing film having Nernst response. The modeling and simulation of the proposed sensor was further validated by a proof of concept extended gate pH sensor fabrication and characterization. These sensors were developed by a separated processing of just the pH sensing component, which is electrically connected to the transistor only during characterization of the sensor. This provides faster and simpler realization of the sensor without the need for masks and patterning by lithography. The extended gate sensors showed 475 mV/pH sensitivity which is superior to state of the art low power ISFETs. Finally, integration of the sensing functionality directly in the BEOL of the UTBB FDSOI devices was pursued. An experimental sensitivity of 730 mV/pH is obtained which is consistent with the mathematical model and the simulated response. This is more than 12-times higher than the Nernst limit, and superior to state of the art sensors. Sensors are also evaluated for stability, resolution, hysteresis, and drift in which excellent performances are demonstrated
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El, Ghouli Salim. "UTBB FDSOI mosfet dynamic behavior study and modeling for ultra-low power RF and mm-Wave IC Design." Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD015/document.

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Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHz<br>This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz
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Chaves, De Albuquerque Tulio. "Integration of Single Photon Avalanche Diodes in Fully Depleted Silicon-on-Insulator Technology." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI091.

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Ce travail a pour objectif la conception, la simulation, la modélisation et la caractérisation électrique de diodes à avalanche à photon unique (Single Photon Avalanche Diodes - SPAD) intégrées dans une technologie CMOS Fully Depleted Silicon on Insulator - FDSOI. Les SPAD sont des diodes (jonctions PN) polarisées en inverse au-delà de la tension de claquage, fonctionnant dans le mode Geiger. Grace à leur haute sensibilité et rapidité, les SPAD sont utiles pour plusieurs applications, telles que les mesures de temps de vol (Time of Flight - ToF), l’imagerie médicale (Fluorescence Lifetime Imaging Microscopy - FLIM), ainsi que la détection de particules chargées, dans le domaine de la physique de haute énergie. L’intégration de SPAD dans une technologie CMOS FDSOI permet d’obtenir une intégration 3D monolithique intrinsèque avec la diode sous l’oxyde enterré, et l’électronique associée dans le film silicium, en optimisant ainsi le facteur de remplissage. Afin d’analyser le comportement des SPAD FDSOI, plusieurs cellules ont été conçues, respectant les principales règles de dessin imposées par la fonderie, mais présentant des variantes structurelles telles que la zone d'intégration, la géométrie, la distance de garde et le circuit d’étouffement. Des simulations TCAD et des calculs analytiques ont été effectués afin d'estimer les principales figures du mérite de SPAD. Plusieurs modèles d'avalanche et de génération de porteurs ont été étudiés pour une meilleure adaptation du modèle simulé aux dispositifs fabriqués. Des caractérisations électriques ont été réalisées pour estimer des paramètres importants tels que la tension de claquage, le taux de comptage dans l'obscurité (DCR) et la réponse en l'électroluminescence. Bien que les résultats obtenus restent inférieurs par rapport à l'état de l’art, la faisabilité d’intégration de SPAD dans une technologie FDSOI a été démontrée comme preuve de concept, mais des améliorations sont nécessaires et certaines pistes sont proposées<br>This work aims at the design, simulation, modelling and electrical characterization of Single Photon Avalanche Diodes (SPAD) in an advanced Fully Depleted Silicon on Insulator (FDSOI) technology. SPADs are PN junctions reversed bias above breakdown voltage, operating in the so-called Geiger mode. Such an implementation should provide an intrinsic monolithic integration of those devices, along with their mandatory associated electronics, thanks to the buried oxide layer present in that technology, optimizing fill factor. Due to its high sensitivity, SPAD are useful for several applications, such as Time of Flight (ToF) and Fluorescence Lifetime Imaging Microscopy (FLIM) measurements, as well as the detection of charged particles, in high-energy physics domain. The designed cells follow the main design rules imposed by the foundry and present variations in aspect as integration zone, geometry, guard distance and quenching circuit. TCAD simulations were performed in order to estimate some of the SPAD main Figures of Merit. Several avalanche and carrier generation models were studied for better adapting the simulated model to the actual fabricated devices. Electrical characterizations were realized for estimating important parameters such as breakdown voltage, Dark Count Rate (DCR) and electroluminescence response. Although the obtained results are still poor when compared to State-of-the-Art, its feasibility was demonstrated and can be used as a proof of concept, at the same time that improvements are proposed
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9

Lundberg, Kent Howard. "A high-speed, low-power analog-to-digital converter in fully depleted silicon-on-insulator technology." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/87328.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.<br>Includes bibliographical references (p. 193-200).<br>This thesis demonstrates a one-volt, high-speed, ultra-low-power, six-bit flash analog-to-digital converter fabricated in a fully depleted silicon-on-insulator CMOS technology. Silicon-on-insulator CMOS technology provides a number of benefits for low-power low-voltage analog design. The full dielectric isolation of the silicon island, where the transistors are built,allows higher layout packing density and reduces parasitic junction capacitances. Fully depleted silicon-on-insulator (SOI) exhibits improved subthreshold slope, which allows for lower transistor threshold voltages. Significant savings in power consumption can be obtained by leveraging these advantages. However, the floating-body effect can create significant problems in analog circuits, leading to potential circuit malfunction. A single-ended auto-zeroed comparator topology is optimized to leverage the advantages of fully depleted SOI technology and avoid the floating-body effect. Using this comparator topology and other circuit techniques that operate with a one-volt supply, a six-bit 500-MS/s flash A/D converter is designed with the lowest power-consumption figure of merit in its class. Consuming only 32 mA from a one-volt supply, the quantization energy figure of merit for this design is calculated to be EQ = 2 pJ. Test chips were fabricated in MIT Lincoln Laboratory's 0.25 [mu]m fully depleted SOI CMOS process. Testing of this design demonstrates the potential of SOI technology for the production of high-speed, low-power analog-to-digital converters.<br>by Kent H. Lundberg.<br>Ph.D.
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10

Gomez, Leonardo Ph D. Massachusetts Institute of Technology. "Electron transport in ultrathin-body fully depleted n-MOSFETS fabricated on strained silicon directly on insulator with body thickness ranging from 22nm to 25 nm." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38671.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.<br>Includes bibliographical references (leaves 49-53).<br>The electron effective mobility in ultrathin-body (UTB) n-MOSFETs fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage measurements as well as cross section transmission electron microscopy. Devices with body thicknesses ranging from 2 nm to 25 nm are studied. Significant electron mobility enhancements ([approx] 1.8x) are observed in SSDOI compared to unstrained SOI for body thicknesses above 3.5 nm. The mobility exhibits a sharp drop as the body thickness is scaled below 3.5 nm.<br>by Leonardo Gomez.<br>S.M.
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Books on the topic "Fully Depleted Silicon-on-Insulator (FDSOI)"

1

Sakurai, Takayasu. Fully-depleted SOI CMOS circuits and technology for ultralow-power applications. Springer, 2011.

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Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/c2019-0-00393-7.

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Suh, Dongwook. Modeling of non-fully depleted silicon-on-insulator MOSFETS, and applications to high-performance/low-power ULSI design. 1995.

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Matsuzawa, Akira, Takayasu Sakurai, and Takakuni Douseki. Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications. Springer, 2008.

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Matsuzawa, Akira, Takayasu Sakurai, and Takakuni Douseki. Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications. Springer, 2006.

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Book chapters on the topic "Fully Depleted Silicon-on-Insulator (FDSOI)"

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Theodorou, Christoforos, and Gérard Ghibaudo. "Noise and Fluctuations in Fully Depleted Silicon-on-Insulator MOSFETs." In Noise in Nanoscale Semiconductor Devices. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37500-3_2.

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Ernst, T., A. Vandooren, S. Cristoloveanu, T. E. Rudenko, and J. P. Colinge. "Recombination Current in Fully-Depleted SOI DIODES: Compact Model and Lifetime Extraction." In Perspectives, Science and Technologies for Novel Silicon on Insulator Devices. Springer Netherlands, 2000. http://dx.doi.org/10.1007/978-94-011-4261-8_20.

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Hu, Chenming. "Fully-Depleted Silicon on Oxide Transistor and Compact Model." In Industry Standard FDSOI Compact Model BSIM-IMG for IC Design. Elsevier, 2019. http://dx.doi.org/10.1016/b978-0-08-102401-0.00001-7.

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"Index." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00021-5.

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Cristoloveanu, Sorin. "Band-modulation devices." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00014-8.

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Cristoloveanu, Sorin. "Electrostatic doping and related devices." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00013-6.

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Cristoloveanu, Sorin. "Characterization methods for FD-SOI MOSFET." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00012-4.

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Cristoloveanu, Sorin. "Coupling effects." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00007-0.

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"Front Matter." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00002-1.

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"FD-SOI teasers." In Fully Depleted Silicon-On-insulator. Elsevier, 2021. http://dx.doi.org/10.1016/b978-0-12-819643-4.00016-1.

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Conference papers on the topic "Fully Depleted Silicon-on-Insulator (FDSOI)"

1

Abdalla, Abdelgader M., and Jonathan Rodriguez. "A new table based modelling of 28nm fully depleted silicon-on insulator (FDSOI)." In 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2016. http://dx.doi.org/10.1109/smacd.2016.7520746.

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Schneider, L., F. Abbate, D. Le Cunff, E. Nolot, and A. Michallet. "Optical properties determination of Fully Depleted Silicon On Insulator (FDSOI) substrates by ellipsometry." In 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2015. http://dx.doi.org/10.1109/asmc.2015.7164469.

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Gatefait, M., B. Le-Gratiet, C. Prentice, and T. Hasan. "An evaluation of edge roll off on 28nm FDSOI (fully depleted silicon on insulator) product." In SPIE Advanced Lithography, edited by Martha I. Sanchez and Vladimir A. Ukraintsev. SPIE, 2016. http://dx.doi.org/10.1117/12.2218859.

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Abdalla, Abdelgader M., I. T. E. Elfergani, and Jonathan Rodriguez. "Modelling the temperature dependence of 28nm fully depleted silicon-on insulator (FDSOI) static characteristics based on parallel computing approach." In 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC). IEEE, 2016. http://dx.doi.org/10.1109/nmdc.2016.7777123.

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Schwarzenbach, W., N. Daval, S. Kerdiles, et al. "Strained silicon on insulator substrates for fully depleted application." In 2012 IEEE International Conference on IC Design & Technology (ICICDT). IEEE, 2012. http://dx.doi.org/10.1109/icicdt.2012.6232869.

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Mattamana, A., K. Groves, P. Orlando, et al. "X-band receiver module in fully depleted silicon on insulator technology." In 2012 IEEE International SOI Conference. IEEE, 2012. http://dx.doi.org/10.1109/soi.2012.6404387.

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Vanhoenacker-Janvier, D., R. Gillon, C. Raynaud, and F. Martin. "Fully-Depleted 0.25 Micron Silicon-on-Insulator MOSFET Transistors for Microwave Applications." In 29th European Microwave Conference, 1999. IEEE, 1999. http://dx.doi.org/10.1109/euma.1999.338398.

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Beigne, E., A. Valentian, B. Giraud, et al. "Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs." In Design Automation and Test in Europe. IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.135.

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Saligram, Rakshith, Abhilash P, and Vasundhara Patel K. S. "Realization of multi-valued logic combinational circuits on fully depleted silicon on insulator." In 2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS). IEEE, 2018. http://dx.doi.org/10.1109/icnews.2018.8904021.

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Umana-Membreno, G. A., S. J. Chang, M. Bawedin, J. Antoszewski, S. Cristoloveanu, and L. Faraone. "Sub-band modulated electronic transport in planar fully-depleted silicon-on-insulator MOSFETs." In 2014 Conference on Optoelectronic and Microelectronic Materials & Devices (COMMAD). IEEE, 2014. http://dx.doi.org/10.1109/commad.2014.7038715.

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