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Journal articles on the topic 'Fully Depleted Silicon-on-Insulator (FDSOI)'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Kambham, Ajay Kumar, Dan Flatoff, and Bianzhu Fu. "Application of Atom Probe on Fully Depleted Silicon-On-Insulator (FDSOI) Structures." Microscopy and Microanalysis 22, S3 (2016): 696–97. http://dx.doi.org/10.1017/s1431927616004335.

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2

Lin, Jyi-Tsong, Yi-Chuen Eng, and Po-Hsieh Lin. "A Novel Nanoscale FDSOI MOSFET with Block-Oxide." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/627873.

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We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI structure is in fact shown to behave similarly to an ultrathin body (UTB) SOI but without the associated disadvantages and technological challenges of the ultrathin film, because a thick Si body allows for reduced sensitivity to self-heating, thereby improving thermal stability.

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3

Wang, Hanbin, Jinshun Bi, Mengxin Liu, and Tingting Han. "Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure." Electronics 10, no. 13 (2021): 1585. http://dx.doi.org/10.3390/electronics10131585.

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This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

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Almeida, Luciano M., Katia R. A. Sasaki, M. Aoulaiche, Eddy Simoen, Cor Clayes, and João Antonio Martino. "One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect." Journal of Integrated Circuits and Systems 7, no. 2 (2012): 113–20. http://dx.doi.org/10.29292/jics.v7i2.363.

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This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.

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5

Litty, Antoine, Sylvie Ortolland, Dominique Golanski, Christian Dutto, Alexandres Dartigues, and Sorin Cristoloveanu. "Towards High-Voltage MOSFETs in Ultrathin FDSOI." International Journal of High Speed Electronics and Systems 25, no. 01n02 (2016): 1640005. http://dx.doi.org/10.1142/s012915641640005x.

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High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

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6

Xu, Jingyan, Yang Guo, Ruiqiang Song, Bin Liang, and Yaqing Chi. "Supply Voltage and Temperature Dependence of Single-Event Transient in 28-nm FDSOI MOSFETs." Symmetry 11, no. 6 (2019): 793. http://dx.doi.org/10.3390/sym11060793.

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Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.

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7

Olejarz, Piotr, Kyoungchul Park, Samuel MacNaughton, Mehmet R. Dokmeci, and Sameer Sonkusale. "0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process." Journal of Low Power Electronics and Applications 2, no. 2 (2012): 155–67. http://dx.doi.org/10.3390/jlpea2020155.

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8

Wei, Zhaopeng, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Jerome Prouvee, and Benjamin Blampey. "Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits." Active and Passive Electronic Components 2019 (July 4, 2019): 1–9. http://dx.doi.org/10.1155/2019/4578501.

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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9

Lederer, Maximilian, Thomas Kämpfe, Norman Vogel, et al. "Structural and Electrical Comparison of Si and Zr Doped Hafnium Oxide Thin Films and Integrated FeFETs Utilizing Transmission Kikuchi Diffraction." Nanomaterials 10, no. 2 (2020): 384. http://dx.doi.org/10.3390/nano10020384.

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The microstructure of ferroelectric hafnium oxide plays a vital role for its application, e.g., non-volatile memories. In this study, transmission Kikuchi diffraction and scanning transmission electron microscopy STEM techniques are used to compare the crystallographic phase and orientation of Si and Zr doped HfO2 thin films as well as integrated in a 22 nm fully-depleted silicon-on-insulator (FDSOI) ferroelectric field effect transistor (FeFET). Both HfO2 films showed a predominately orthorhombic phase in accordance with electrical measurements and X-ray diffraction XRD data. Furthermore, a stronger texture is found for the microstructure of the Si doped HfO2 (HSO) thin film, which is attributed to stress conditions inside the film stack during crystallization. For the HSO thin film fabricated in a metal-oxide-semiconductor (MOS) like structure, a different microstructure, with no apparent texture as well as a different fraction of orthorhombic phase is observed. The 22 nm FDSOI FeFET showed an orthorhombic phase for the HSO layer, as well as an out-of-plane texture of the [111]-axis, which is preferable for the application as non-volatile memory.

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10

Yan, Gangping, Jinshun Bi, Gaobo Xu, et al. "Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor." IEEE Access 8 (2020): 154898–905. http://dx.doi.org/10.1109/access.2020.3018714.

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11

Jacquemod, Gilles, Alexandre Fonseca, Emeric de Foucauld, Yves Leduc, and Philippe Lorenzini. "2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology." Frontiers of Materials Science 9, no. 2 (2015): 156–62. http://dx.doi.org/10.1007/s11706-015-0288-6.

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12

Zhang, Lujie, Jingyan Xu, Yaqing Chi, and Yang Guo. "The Effect of Energy Loss Straggling on SEUs Induced by Low-Energy Protons in 28 nm FDSOI SRAMs." Applied Sciences 9, no. 17 (2019): 3475. http://dx.doi.org/10.3390/app9173475.

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Sensitive volume thickness for silicon on insulator (SOI) devices has scaled to the point that energy loss straggling cannot be ignored within the development of the manufacturing process. In this study, irradiation experiments and Geant4 simulation were carried out to explore the influence of energy loss straggling on single event upsets (SEUs) caused by sub-8 MeV proton direct ionization. We took a 28 nm fully-depleted SOI static random-access memory (SRAM) as the research target. According to our results, the depositing energy spectrum formed by monoenergetic low-energy protons that penetrated through the sensitive volume of the target SRAM was extremely broadened. We concluded that the SEUs we observed in this article were attributed to energy loss straggling. Therefore, it is sensible to take the new mechanism into consideration when predicting proton-induced SEUs for modern nanometer SOI circuits, instead of the traditional linear energy transfer (LET) method.

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13

Klewer, Christian, Frank Kuechenmeister, Jens Paul, et al. "Package Qualification Envelope for 22FDX® Technology." International Symposium on Microelectronics 2019, no. 1 (2019): 000169–75. http://dx.doi.org/10.4071/2380-4505-2019.1.000169.

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Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.

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14

Dghais, Wael, Malek Souilem, Fakhreddine Zayer, and Abdelkader Chaari. "Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation." Mathematical Problems in Engineering 2018 (August 8, 2018): 1–9. http://dx.doi.org/10.1155/2018/1356538.

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This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.

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15

Han, Sangwoo, Sojin Jeong, Jaemin Shin, and Changhwan Shin. "Steep-Switching Fully Depleted Silicon-on-Insulator (FDSOI) Phase-Transition Field-Effect Transistor With Optimized HfO₂/Al₂O₃-Multilayer-Based Threshold Switching Device." IEEE Transactions on Electron Devices 68, no. 3 (2021): 1358–63. http://dx.doi.org/10.1109/ted.2021.3053237.

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16

Christmann, Jean-Frédéric, Florent Berthier, David Coriat, et al. "A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm." Journal of Low Power Electronics and Applications 9, no. 1 (2019): 8. http://dx.doi.org/10.3390/jlpea9010008.

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Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.

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17

Kumar, K. Senthil, Saptarsi Ghosh, Anup Sarkar, S. Bhattacharya, and Subir Kumar Sarkar. "Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance." Applied Mechanics and Materials 110-116 (October 2011): 5150–54. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5150.

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With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

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18

Zhao, Chao, and Jinjuan Xiang. "Atomic Layer Deposition (ALD) of Metal Gates for CMOS." Applied Sciences 9, no. 11 (2019): 2388. http://dx.doi.org/10.3390/app9112388.

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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19

Boutchacha, T., and G. Ghibaudo. "Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs." Active and Passive Electronic Components 2020 (December 2, 2020): 1–10. http://dx.doi.org/10.1155/2020/7989238.

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Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.

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20

Nocua, Alejandro, Arnaud Virazel, Alberto Bosio, Patrick Girard, and Cyril Chevalier. "HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740004. http://dx.doi.org/10.1142/s0218126617400047.

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High power consumption is a key factor hindering system-on-chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow when most of the optimization potential is possible. However, early accuracy cannot be ensured because of the lack of precise knowledge of the final circuit structure. Current SoC design paradigm relies on intellectual property (IP) core reuse since low-level information about circuit components and structure is available. Thus, power estimation accuracy at the system level can be improved by using this information and developing an estimation methodology that fits IP cores power modeling needs. The main contribution of this paper is the development and validation of a hybrid power estimation technique (HPET), in which information coming from different abstraction levels is used to assess the power consumption in a fast and accurate manner. HPET is based on an effective characterization methodology of the technology library and an efficient hybrid power modeling approach. Experimental results, derived using HPET, have been validated on different benchmark circuits synthesized using the 28[Formula: see text]nm “fully depleted silicon on insulator” (FDSOI) technology. Experimental results show that in average we can achieve up to 68[Formula: see text] improvement in power estimation run-time while having transistor-level accuracy. For both analyzed power types (instantaneous and average), HPET results are well correlated with respect to the ones computed in SPECTRE and Primetime-PX. This demonstrates that HPET is an effective technique to enhance power macro-modeling creation at high abstraction levels.

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21

Min Cao, T. Kamins, P. V. Voorde, C. Diaz та W. Greene. "0.18-μm fully-depleted silicon-on-insulator MOSFET's". IEEE Electron Device Letters 18, № 6 (1997): 251–53. http://dx.doi.org/10.1109/55.585344.

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22

MacElwee, T. W., I. D. Calder, R. A. Bruce, and F. R. Shepherd. "High-performance fully depleted silicon-on-insulator transistors." IEEE Transactions on Electron Devices 37, no. 6 (1990): 1444–51. http://dx.doi.org/10.1109/16.106239.

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23

Sugii, Nobuyuki. "Low-power-consumption fully depleted silicon-on-insulator technology." Microelectronic Engineering 132 (January 2015): 226–35. http://dx.doi.org/10.1016/j.mee.2014.08.004.

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24

Vandooren, Anne. "Physics and Integration of Fully-Depleted Silicon-On-Insulator Devices." ECS Transactions 6, no. 4 (2019): 15–26. http://dx.doi.org/10.1149/1.2728836.

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25

Kang, Soo Cheol, Donghwan Lim, Sung Kwan Lim, et al. "Unique reliability characteristics of fully depleted silicon-on-insulator tunneling FET." Japanese Journal of Applied Physics 57, no. 4S (2018): 04FB02. http://dx.doi.org/10.7567/jjap.57.04fb02.

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26

Álvarez, D., J. Hartwich, J. Kretz, M. Fouchier, and W. Vandervorst. "Scanning spreading resistance microscopy of fully depleted silicon-on-insulator devices." Microelectronic Engineering 67-68 (June 2003): 945–50. http://dx.doi.org/10.1016/s0167-9317(03)00158-8.

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27

Dezfulian, Kevin K., J. Peter Krusius, Michael O. Thompson, and Somit Talwar. "Laser-induced lateral epitaxy in fully depleted silicon-on-insulator junctions." Applied Physics Letters 81, no. 12 (2002): 2238–40. http://dx.doi.org/10.1063/1.1507359.

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Park, Hyungjin, Jean-Pierre Colinge, Sorin Cristoloveanu, and Maryline Bawedin. "Persistent Floating‐Body Effects in Fully Depleted Silicon‐on‐Insulator Transistors." physica status solidi (a) 217, no. 9 (2020): 1900948. http://dx.doi.org/10.1002/pssa.201900948.

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Kheirallah, Rida, Gilles Ducharme, and Nadine Azemard. "Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices." Journal of Low Power Electronics 12, no. 1 (2016): 58–63. http://dx.doi.org/10.1166/jolpe.2016.1420.

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Bindal, A., N. Rovedo, J. Restivo, C. Galli, and S. Ogura. "Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications." Thin Solid Films 232, no. 1 (1993): 105–9. http://dx.doi.org/10.1016/0040-6090(93)90770-p.

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Navarro, C., M. Bawedin, F. Andrieu, B. Sagnes, F. Martinez, and S. Cristoloveanu. "Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors." Journal of Applied Physics 118, no. 18 (2015): 184504. http://dx.doi.org/10.1063/1.4935453.

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Li, Yulong, Warren M. Porter, Chaitanya Kshirsagar, et al. "Fully-Depleted Silicon-on-Insulator Devices for Radiation Dosimetry in Cancer Therapy." IEEE Transactions on Nuclear Science 61, no. 6 (2014): 3443–50. http://dx.doi.org/10.1109/tns.2014.2365544.

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MANVENDRA, SINGH CHAUHAN, and KUMAR CHAUHAN RAJEEV. "PERFORMANCE ANALYSIS OF MODIFIED SOURCE JUNCTIONLESS FULLY DEPLETED SILICON ON INSULATOR MOSFET." i-manager’s Journal on Electronics Engineering 8, no. 2 (2018): 44. http://dx.doi.org/10.26634/jele.8.2.14140.

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34

Signamarcheix, T., F. Andrieu, B. Biasse, et al. "Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies." Solid-State Electronics 59, no. 1 (2011): 8–12. http://dx.doi.org/10.1016/j.sse.2011.01.013.

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35

Mazellier, Jean-Paul, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, and Philippe Bergonzo. "Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis." Diamond and Related Materials 17, no. 7-10 (2008): 1248–51. http://dx.doi.org/10.1016/j.diamond.2008.03.026.

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CRISTOLOVEANU, S., T. ERNST, D. MUNTEANU, and T. OUISSE. "ULTIMATE MOSFETs ON SOI: ULTRA THIN, SINGLE GATE, DOUBLE GATE, OR GROUND PLANE." International Journal of High Speed Electronics and Systems 10, no. 01 (2000): 217–30. http://dx.doi.org/10.1142/s012915640000026x.

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We tentatively present possible architectures of Silicon On Insulator (SOI) transistors for the final stages of the scaling of silicon microelectronics. The scaling trends for conventional partially depleted and fully depleted SOI MOSFETs are critically examined. A ground plane can considerably attenuate short-channel effects. The manufacturability of extremely thin MOSFETs is demonstrated. Based on quantum calculations, we discuss the merits of double-gate transistors with volume inversion.

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37

Vitale, Steven A., and Pascale M. Gouker. "Gadolinium oxide coated fully depleted silicon-on-insulator transistors for thermal neutron dosimetry." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 721 (September 2013): 45–49. http://dx.doi.org/10.1016/j.nima.2013.04.056.

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38

Yoon, Chankeun, and Changhwan Shin. "Time-resolved electrical characteristics of ferroelectric-gated fully depleted silicon on insulator devices." Solid-State Electronics 164 (February 2020): 107698. http://dx.doi.org/10.1016/j.sse.2019.107698.

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Sato, Yasuhiro, Takako Ishihara, Yuichi Kado, Kazuyoshi Nishimura, and Toshiaki Tsuchiya. "Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits." Japanese Journal of Applied Physics 43, no. 8A (2004): 5209–17. http://dx.doi.org/10.1143/jjap.43.5209.

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Sharma, Rajneesh, and Ashwani K. Rana. "Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET." International Journal of Electronics 104, no. 2 (2016): 286–96. http://dx.doi.org/10.1080/00207217.2016.1199052.

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Mchedlidze, Teimuraz, and Elke Erben. "Characterization of Ultrathin Fully Depleted Silicon‐on‐Insulator Devices Using Subthreshold Slope Method." physica status solidi (a) 217, no. 24 (2020): 2000625. http://dx.doi.org/10.1002/pssa.202000625.

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Tokunaga, K., and J. C. Sturm. "Substrate bias dependence of subthreshold slopes in fully depleted silicon-on-insulator MOSFET's." IEEE Transactions on Electron Devices 38, no. 8 (1991): 1803–7. http://dx.doi.org/10.1109/16.119018.

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Dreeskornfeld, L., J. Hartwich, J. Kretz, L. Risch, W. Roesner, and D. Schmitt-Landsiedel. "Nanoscale electron beam lithography and etching for fully depleted silicon-on-insulator devices." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 20, no. 6 (2002): 2777. http://dx.doi.org/10.1116/1.1518023.

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Ma, Ming-Wen, Tien-Sheng Chao, Kuo-Hsing Kao, Jyun-Siang Huang, and Tan-Fu Lei. "Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices." Japanese Journal of Applied Physics 45, no. 9A (2006): 6854–59. http://dx.doi.org/10.1143/jjap.45.6854.

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Toguchi, Shintaro, En Xia Zhang, Mariia Gorchichko, et al. "Total-Ionizing-Dose Effects on 3D Sequentially Integrated, Fully Depleted Silicon-on-Insulator MOSFETs." IEEE Electron Device Letters 41, no. 4 (2020): 637–40. http://dx.doi.org/10.1109/led.2020.2972439.

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Baudot, Sophie, Francois Andrieu, Olivier Weber, et al. "Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon–Germanium Source/Drain." IEEE Electron Device Letters 31, no. 10 (2010): 1074–76. http://dx.doi.org/10.1109/led.2010.2057500.

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Kim, Hyun Joo, Joo Hyung You, Kae Dal Kwack, and Tae Whan Kim. "Nanoscale Two-Bit/Cell NAND Silicon–Oxide–Nitride–Oxide–Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates." Japanese Journal of Applied Physics 49, no. 9 (2010): 094201. http://dx.doi.org/10.1143/jjap.49.094201.

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Pavanello, Marcelo Antonio, João Antonio Martino, and Denis Flandre. "Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects." Solid-State Electronics 44, no. 6 (2000): 917–22. http://dx.doi.org/10.1016/s0038-1101(00)00032-0.

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Shang, Huiling, Marvin H. White, and Dennis A. Adams. "Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology." Solid-State Electronics 46, no. 12 (2002): 2307–13. http://dx.doi.org/10.1016/s0038-1101(02)00235-6.

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Umana-Membreno, G. A., S. J. Chang, M. Bawedin, J. Antoszewski, S. Cristoloveanu, and L. Faraone. "High-resolution mobility spectrum analysis of magnetoresistance in fully-depleted silicon-on-insulator MOSFETs." Solid-State Electronics 113 (November 2015): 109–15. http://dx.doi.org/10.1016/j.sse.2015.05.022.

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