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Journal articles on the topic 'Gain and offset mismatches'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Zheng, Yanze, Naixin Zhou, Yijiu Zhao, and Sicheng Sun. "Time-interleaved system mismatch estimation based on correlation function and particle swarm optimization algorithm." Review of Scientific Instruments 93, no. 10 (2022): 104702. http://dx.doi.org/10.1063/5.0103225.

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The time-interleaved analog-to-digital converters (TIADCs) technique is an efficient solution to improve the sampling rate of the acquisition system with low-speed ADCs. However, channel mismatches such as gain mismatch, time skew mismatch, and offset mismatch may seriously degrade the performance of TIADC. Furthermore, for high-speed signal acquisition, the gain and time skew mismatches would vary with the signal frequency, and the traditional fixed model does not work any longer. In this paper, a series of sinusoidal signals are adopted to estimate the variable mismatches. First, an autocorr

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Thaar A.Kareem, Saif Benali, and Hatem Trabelsi. "Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes." International Journal of Interactive Mobile Technologies (iJIM) 17, no. 06 (2023): 180–96. http://dx.doi.org/10.3991/ijim.v17i06.38803.

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Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS cur

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3

Yang, Kuojun, Shulin Tian, Peng Ye, Peng Zhang, and Yuanjin Zheng. "A Statistic-Based Calibration Method for TIADC System." Mathematical Problems in Engineering 2015 (2015): 1–9. http://dx.doi.org/10.1155/2015/689869.

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Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product

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Li, Xin, Cheng Huang, Desheng Ding, and Jianhui Wu. "A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs." Journal of Circuits, Systems and Computers 29, no. 02 (2019): 2030002. http://dx.doi.org/10.1142/s0218126620300020.

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Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADC

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Qian, Lei, Xinpeng Xing, Haigang Feng, and Georges Gielen. "Digital Background Calibration Techniques for 2GS/s 12bit Time-Interleaved Pipelined ADC." Journal of Physics: Conference Series 2613, no. 1 (2023): 012020. http://dx.doi.org/10.1088/1742-6596/2613/1/012020.

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Abstract This paper presents digital background(BG) calibration techniques which are utilized to correct both inter-stage gain error (IGE) and inter-channel mismatches in a 12-bit 2GS/s 4-channel time-interleaved pipeline ADC. The inter-stage gain is mitigated by Least Mean Square (LMS) based calibration with a proposed Pseudo Noise (PN) codes injected into 1.5bit MDAC stages, which has neither input amplitude limitation nor comparator requirement. The inter-channel offset and gain mismatches are eliminated by Modified Moving Average (MMA) and LMS –based calibrations respectively. The inter-ch

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Pan, Huiqing, Shulin Tian, and Peng Ye. "An Adaptive Synthesis Calibration Method for Time-Interleaved Sampling Systems." Metrology and Measurement Systems 17, no. 3 (2010): 405–14. http://dx.doi.org/10.2478/v10178-010-0034-4.

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An Adaptive Synthesis Calibration Method for Time-Interleaved Sampling SystemsIn a parallel time-interleaved data sampling system, timing and amplitude mismatches of this structure degrade the performance of the whole ADC system. In this paper, an adaptive blind synthesis calibration algorithm is proposed, which could estimate the timing, gain and offset errors simultaneously, and calibrate automatically. With no need of an extra calibration signal and redesign, it could efficiently and dynamically track the changes of mismatches due to aging or temperature variation. A fractional delay filter

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Ta, Van-Thanh, Van-Phuc Hoang, Van-Phu Pham, and Cong-Kha Pham. "An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters." Electronics 9, no. 1 (2020): 73. http://dx.doi.org/10.3390/electronics9010073.

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The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases t

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Naga Chakravarthi Manepalli, Venkata, and Chandramohan Bhuma. "Optimization Algorithms based compensation of mismatches in Time interleaved Analog to Digital Converters." International journal of electrical and computer engineering systems 13, no. 3 (2022): 237–44. http://dx.doi.org/10.32985/ijeces.13.3.8.

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Time interleaved analog to digital converters (TIADCs) play a significant role in signal processing wherever higher sampling rates are required. However, TIADCs suffer from various mismatches like sampling time, dc offset, gain, bandwidth etc. This results in generation of erroneous signal. Numerous methods were proposed for estimation of these mismatches and for correction of the erroneous signal. Optimization algorithms like genetic algorithm (GA), differential evolution (DE) algorithm were also used for estimation of mismatches. An overview of these algorithms and their performance comparis

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Li, Yuehui, Cong Liu, Guangshan Niu, Xiangdong Luo, Haocheng Ma, and Yiqiang Zhao. "Error Detection and Correction of Mismatch Errors in M-Channel TIADCs Based on Genetic Algorithm Optimization." Electronics 11, no. 15 (2022): 2366. http://dx.doi.org/10.3390/electronics11152366.

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In order to achieve higher system performance, a digital calibration technique for the sub-channel mismatches of time-interleaved ADCs (TIADCs) is proposed in this paper. The sine-fit-based estimation algorithm is introduced to estimate the channel mismatches and a calibration algorithm is proposed to compensate for the mismatches. Subsequently, the genetic algorithm (GA) is firstly utilized to detect the mismatch errors of the outputs of sub-channels after frequency domain filtering. The detected offset error and gain error are then corrected by performing the calibration algorithm, and the t

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Jia, Hanbo, Xuan Guo, Danyu Wu, et al. "A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration." Electronics 9, no. 6 (2020): 910. http://dx.doi.org/10.3390/electronics9060910.

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This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed

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11

Ta, Van-Thanh, Van-Phuc Hoang, and Xuan Tran. "All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs." EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 6, no. 21 (2019): 160983. http://dx.doi.org/10.4108/eai.24-10-2019.160983.

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Zenebe, Mikias Belhu, Getachew Alemu, Valentijn De Smedt, and Paul Leroux. "Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency." Electronics 12, no. 13 (2023): 2775. http://dx.doi.org/10.3390/electronics12132775.

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Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with ad

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13

Guo, Lianping, Shulin Tian, and Zhigang Wang. "Estimation and Correction of Gain Mismatch and Timing Error in Time-Interleaved ADCs Based on DFT." Metrology and Measurement Systems 21, no. 3 (2014): 535–44. http://dx.doi.org/10.2478/mms-2014-0045.

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Abstract Time-interleaved analog-to-digital converter (ADC) architecture is crucial to increase the maximum sample rate. However, offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the performance of time-interleaved ADCs. This paper focuses on the gain mismatch and timing error. Techniques based on Discrete Fourier Transform (DFT) for estimating and correcting gain mismatch and timing error in an M-channel ADC are depicted. Numerical simulations are used to verify the proposed estimation and correction algorithm.

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14

Blackburn, Simon R. "Maximum Likelihood Decoding for Multilevel Channels With Gain and Offset Mismatch." IEEE Transactions on Information Theory 62, no. 3 (2016): 1144–49. http://dx.doi.org/10.1109/tit.2016.2521658.

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15

Weber, Jos H., and Kees A. Schouhamer Immink. "Maximum Likelihood Decoding for Gaussian Noise Channels With Gain or Offset Mismatch." IEEE Communications Letters 22, no. 6 (2018): 1128–31. http://dx.doi.org/10.1109/lcomm.2018.2809749.

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16

Jalili, Armin, Sayed Masoud Sayedi, and J. Jacob Wikner. "Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs." Microelectronics Journal 42, no. 1 (2011): 158–64. http://dx.doi.org/10.1016/j.mejo.2010.08.014.

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Hartanto, Ari Dwi, and Al Sutjijana. "Binary Cyclic Pearson Codes." Jurnal Matematika MANTIK 7, no. 1 (2021): 1–8. http://dx.doi.org/10.15642/mantik.2021.7.1.1-8.

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The phenomena of unknown gain or offset on communication systems and modern storages such as optical data storage and non-volatile memory (flash) becomes a serious problem. This problem can be handled by Pearson distance applied to the detector because it offers immunity to gain and offset mismatch. This distance can only be used for a specific set of codewords, called Pearson codes. An interesting example of Pearson code can be found in T-constrained code class. In this paper, we present binary 2-constrained codes with cyclic property. The construction of this code is adopted from cyclic code

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18

Ishrat, Zahan Mukti, Rahman Khan Ebadur, and Kumar Biswas Koushik. "1.8-V Low Power, High-Resolution, High-Speed Comparator with Low Offset Voltage Implemented in 45nm CMOS Technology." International Journal of Innovative Science and Research Technology 7, no. 12 (2022): 183–87. https://doi.org/10.5281/zenodo.7471024.

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This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed. The designed comparator is built on 45 𝑛𝑚 flip CMOS technology and runs 4.2 𝐺 samples per second at nominal voltage. It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC). The outlined design can operate on a nominal supply of 1.8 V. The comparator offset voltage was elevated because of this mismatch. To compensate for the offset voltage, we followed a decent approach to design the circuits. Therefore, the offset voltage is reduced to 250𝜇𝑉. The desi

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19

Laababid, Younes, Karim El Khadiri, and Ahmed Tahiri. "Biopotential multi-path current feedback instrumentation amplifier with automatic offset cancellation loop for resistive bridge microsensors." International Journal of Power Electronics and Drive Systems (IJPEDS) 14, no. 4 (2023): 2107. http://dx.doi.org/10.11591/ijpeds.v14.i4.pp2107-2118.

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<span lang="EN-US">This study introduces a refined current feedback instrumentation amplifier (CFIA) specifically designed for amplifying biopotential signals that originate from resistive-bridge sensors. The proposed architecture uniquely incorporates a multipath chopper-stabilized CFIA which has been developed to minimize the effects of bridge offsets, while maintaining low power usage, high input impedance, and reduced noise characteristics. The engineering blueprint employs a ripple reduction loop (RRL) to mitigate output ripple caused by chopper up-modulation. To speed up offset can

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Younes, Laababid, El Khadiri Karim, and Tahiri Ahmed. "Biopotential multi-path current feedback instrumentation amplifier with automatic offset cancellation loop for resistive bridge microsensors." Biopotential multi-path current feedback instrumentation amplifier with automatic offset cancellation loop for resistive bridge microsensors 14, no. 4 (2023): 2107–18. https://doi.org/10.11591/ijpeds.v14.i4.pp2107-2118.

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This study introduces a refined current feedback instrumentation amplifier (CFIA) specifically designed for amplifying biopotential signals that originate from resistive-bridge sensors. The proposed architecture uniquely incorporates a multipath chopper-stabilized CFIA which has been developed to minimize the effects of bridge offsets, while maintaining low power usage, high input impedance, and reduced noise characteristics. The engineering blueprint employs a ripple reduction loop (RRL) to mitigate output ripple caused by chopper up-modulation. To speed up offset cancellation and to limit th

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Immink, Kees A. Schouhamer, and Jos H. Weber. "Minimum Pearson Distance Detection for Multilevel Channels With Gain and/or Offset Mismatch." IEEE Transactions on Information Theory 60, no. 10 (2014): 5966–74. http://dx.doi.org/10.1109/tit.2014.2342744.

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22

U, Seng-Pan, R. P. Martins, and J. E. Franca. "Offset- and gain-compensated and mismatch-free SC delay circuit with flexible implementation." Electronics Letters 35, no. 3 (1999): 188. http://dx.doi.org/10.1049/el:19990170.

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23

Häring, L., and A. Czylwik. "Synchronization in MIMO OFDM systems." Advances in Radio Science 2 (May 27, 2005): 147–53. http://dx.doi.org/10.5194/ars-2-147-2004.

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Abstract. In this paper, an overview of carrier frequency offset (CFO) estimation algorithms for Orthogonal Frequency Division Multiplexing (OFDM) systems is presented. It is well-known that multicarrier systems suffer from their high sensitivity to mismatches of transmitter and receiver oscillator frequencies. The performance degrades since the CFO destroys the orthogonality of the subcarriers. Hence, extensive research has been done on the estimation and correction of the CFO in Single-Input Single-Output (SISO) systems. Mainly, the proposed algorithms can be categorized into data-aided and

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Ferragina, V., A. Fornasari, U. Gatti, P. Malcovati, and F. Maloberti. "Gain and Offset Mismatch Calibration in Time-Interleaved Multipath A/D Sigma–Delta Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 12 (2004): 2365–73. http://dx.doi.org/10.1109/tcsi.2004.838154.

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Han, Jing Lei, Wen Lian Zhang, and Zhi Biao Shao. "A Novel Pre-Amplifier for DTH in Folding and Interpolating ADC." Applied Mechanics and Materials 321-324 (June 2013): 367–71. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.367.

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A pre-amplifier for distributed track and hold (DTH) circuit in high speed and high resolution folding and interpolating analog-to-digital converter (ADC) is proposed. This scheme resolves several limitations of conventional differential difference pre-amplifier (DDPA) in low voltage supply, compared to the conventional DDPA, the proposed scheme increases the input range so that all DDPAs of DTH can operate effectively, improves the averaging effect of average network, saves the random offset voltage from device mismatch, decreases the gain error of DTH, reduces the output common-mode (CM) dev

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Huang, S., and B. C. Levy. "Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs." IEEE Transactions on Circuits and Systems I: Regular Papers 53, no. 6 (2006): 1278–88. http://dx.doi.org/10.1109/tcsi.2006.875180.

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Zenebe, Mikias Belhu, Getachew Alemu, Valentijn De Smedt, and Paul Leroux. "Frequency-Based Sensor Interface with Dynamic Offset Compensation." Electronics 12, no. 7 (2023): 1524. http://dx.doi.org/10.3390/electronics12071524.

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Sensor interfaces need to be robust and accurate for many applications. This is more challenging for sensor systems operating in radiation environments because the mismatch between components grows as a result of the absorbed total ionizing dose (TID). In frequency-based sensor interfaces, the frequency drift of the voltage-controlled oscillator (VCO) can create dynamic output offset, gain, and linearity errors unless a calibration algorithm is included. In this paper, a digital intensive dynamic offset cancelation technique is proposed for an open loop VCO-based sensor to digital converter, w

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Li, Jianwen, Xuan Guo, Jian Luan, et al. "A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology." Electronics 9, no. 2 (2020): 375. http://dx.doi.org/10.3390/electronics9020375.

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A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit

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Gao, Yu Han, Yong Lu Wang, Guang Bin Chen, et al. "An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication." Advanced Materials Research 756-759 (September 2013): 205–8. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.205.

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In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivale

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Sun, Hui Yong, and Peng Cao. "Researches on Channel Mismatch Effects in Time-Interleaved ADC System." Advanced Materials Research 655-657 (January 2013): 978–83. http://dx.doi.org/10.4028/www.scientific.net/amr.655-657.978.

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The Time-Interleaved ADC（TIADC) is an effective method for implement ultra high-speed data acquisition. However, the errors of channel mismatch are seriously degrade the signal-to-noise ratio of the system, such as Time-skew error, Gain error and Offset error. This paper have done some researches and analysis, and given the modeling of the three channels mismatch. What's more, it also given a detailed analysis of error and the method of measure it, derived the formula of signal to noise and distortion ratio(SINAD) and spurious free dynamic range(SFDR). All of them provide a reference for the t

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Apoorva, Reddy Proddutoori. "High Impact of Low Voltage Controlling SoC Power." European Journal of Advances in Engineering and Technology 7, no. 12 (2020): 89–92. https://doi.org/10.5281/zenodo.12771134.

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The scaling of CMOS technology significantly increases the mismatch and fluctuations of transistor threshold voltage, causing bias voltage in SoC designs. A large offset voltage increases clock line jitter and negatively affects dynamic power consumption during reading, detecting the correct speed and operating speed. All MOS transistors used in the low-order dropout (LDO) regulator are low voltage (LV) MOSFETs, saving the manufacturing cost of high voltage devices for the conventional design. Two low voltage transistors are cascaded in the power transmission, creating multiple voltage domains

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Hu, Min, and Pengxing Yi. "Digital Calibration for Gain, Time Skew, and Bandwidth Mismatch in Under-Sampling Time-Interleaved System." Applied Sciences 12, no. 21 (2022): 11029. http://dx.doi.org/10.3390/app122111029.

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This paper presents an all-digital background calibration method for gain, time skew, and bandwidth mismatch in M-channel under-sampling time-interleaved analog-to-digital converters (TI-ADCs) systems. Firstly, the characteristics of offset, gain, time skew, and bandwidth mismatch on the TI-ADCs system are analyzed. Secondly, a parameter vector is constructed to correct gain, time skew, and bandwidth mismatch. Then, the constructed parameter vector is calculated with the bandpass fractional delay filter and least squares (LS) algorithm. Based on the bandpass fractional delay filter, the propos

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Morsy, Ayman, Jonathan Vrijsen, Jan Coosemans, Tuur Bruneel, and Maarten Kuijk. "Noise Analysis for Correlation-Assisted Direct Time-of-Flight." Sensors 25, no. 3 (2025): 771. https://doi.org/10.3390/s25030771.

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The development of a correlation-assisted direct time-of-flight (CA-dToF) pixel provides a novel solution for time-of-flight applications that combines low power consumption, robust ambient shot noise suppression, and a compact design. However, the pixel’s implementation introduces systematic errors, affecting its performance. We investigate the pixel’s robustness against various noise sources, including timing jitter, kTC noise, switching noise, and photon shot noise. Additionally, we address limitations such as the SPAD deadtime, and source follower gain mismatch and offset, identifying thei

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Chen, Hongmei, Yongsheng Yin, Honghui Deng, and Fujiang Lin. "A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs." VLSI Design 2016 (October 9, 2016): 1–8. http://dx.doi.org/10.1155/2016/6475932.

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A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the output

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Ghosh, Shouharda, and Bibhu Datta Sahoo. "Closed-Form Expression for the Combined Effect of Offset, Gain, Timing, and Bandwidth Mismatch in Time-Interleaved ADCs Using Generalized Sampling." IEEE Transactions on Instrumentation and Measurement 70 (2021): 1–12. http://dx.doi.org/10.1109/tim.2021.3124042.

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Hou, Kaiyang, Dajun Sun, Tingting Teng, and Junjie Hu. "A coherent integration method of an active sonar for maneuvering turning target detection." Journal of the Acoustical Society of America 155, no. 5 (2024): 2973–89. http://dx.doi.org/10.1121/10.0025927.

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The detection probability of underwater weak targets using active sonar is low, and inter-pulse coherent integration can improve the signal-to-noise ratio of echoes. When a target executes a maneuvering turn, complex range and Doppler frequency migrations occur during the coherent integration time that decrease the coherent integration gain. Most existing integration methods simplify the target motion to a finite-order polynomial model but fail to integrate a maneuvering turning target (MTT) due to model mismatch. Hence, this study proposes an underwater MTT integration method based on the mod

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Zhao, Yongjie, Sida Li, and Zhiping Huang. "TI-ADC multi-channel mismatch estimation and calibration in ultra-high-speed optical signal acquisition system." Mathematical Biosciences and Engineering 18, no. 6 (2021): 9050–75. http://dx.doi.org/10.3934/mbe.2021446.

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<abstract> <p>This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implem

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Wu, Jin, Dan Yu Wu, Fan Jiang, et al. "An 8-Bit 1.72-Gsample/s Two Channel TimeInterleaved Analog-to-Digital Converter Based on PCB Circuit Board." Applied Mechanics and Materials 336-338 (July 2013): 1525–31. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1525.

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This paper reports an 8-bit 1.72-Gsample/s TimeInterleaved analog-to-digital converter (TIADC) based on PCB with Field Programmable Gate Array (FPGA) technique. The system integrates two independent designed 8-bit 0.9-Gsample/s ADC chips in parallel, commercial FPGA and multi phase clock distributor circuit. In order to increase the systems performance, online calibration method is proposed to calibrate the mismatching errors in TIADC. The utilization of the FPGA is proven to be effective in removing the offset & gain mismatch; the clock distributor circuit is used as the time delay for ea

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Pham, Xuan Thanh, Ngoc Tan Nguyen, Van Truong Nguyen, and Jong-Wook Lee. "A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing." Sensors 20, no. 7 (2020): 2059. http://dx.doi.org/10.3390/s20072059.

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To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first st

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INANLOU, REZA, and MOHAMMAD YAVARI. "A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450026. http://dx.doi.org/10.1142/s0218126614500261.

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In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digita

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Zhang, Xiaowei, Wei Fan, Jianxiong Xi, and Lenian He. "14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor." Journal of Sensors 2021 (February 22, 2021): 1–17. http://dx.doi.org/10.1155/2021/6651642.

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This paper proposes a 14-bit fully differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two-step scaled-reference voltages to realize 14-bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self-calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. Th

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Kalpana, G., Raja Krishnamoorthy, and P. T. Kalaivaani. "Design and implementation of low-power CMOS biosignal amplifier for active electrode in biomedical application using subthreshold biasing strategy." International Journal of Wavelets, Multiresolution and Information Processing 18, no. 01 (2019): 1941017. http://dx.doi.org/10.1142/s0219691319410170.

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Active Electrodes (AEs) are electrodes which have integrated bio-amplifier circuitry and are known to be less susceptible to motion artifacts and environmental interference. In this work, a low-power and high-input impedance amplifier for active electrode application is implemented based on subthreshold biasing strategies. In this proposed Application Specific Integrated Circuit (ASIC) device was versatile and numerical to achieve a high degree of programmability. It could be adapted to any other external part of one cochlear prosthesis, the sound analyzer that could be driven by a Digital Sig

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Ferlito, Umberto, Alfio Dario Grasso, Michele Vaiana, and Giuseppe Bruno. "An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement." Journal of Low Power Electronics and Applications 11, no. 2 (2021): 22. http://dx.doi.org/10.3390/jlpea11020022.

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Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mi

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Cornelissen, Andries Johannes, Nando Ferreira, Marilize Cornelle Burger, and Jacobus Daniel Jordaan. "Proximal femur anatomy-implant geometry discrepancies." SICOT-J 8 (2022): 5. http://dx.doi.org/10.1051/sicotj/2022004.

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Objectives: Due to ongoing concern about femur anatomy-implant mismatches, this cross-sectional study aimed to create a geometric femur profile and used it to identify and quantify possible mismatches between femur anatomy and cephalomedullary nail dimensions. The work further aimed to assess whether patient demographics affect anatomy-implant coherence. Methods: One hundred skeletally mature complete femur computer tomography (CT) scans were collected and exported to software enabling landmark placement and measures with multiplanar reconstruction techniques. Results: Clinically relevant anat

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Park, Pyoungwon, Dipankar Nag, Dan Lei Yan, and Muthukumaraswamy Annamalai Arasu. "Digital Compensation Method for the Path Delay Mismatches in GRO-TDC." Journal of Circuits, Systems and Computers 25, no. 01 (2015): 1640008. http://dx.doi.org/10.1142/s0218126616400089.

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The digital compensation method for path delay mismatches in the time-to-digital converter (TDC) based on gated-ring oscillator (GRO) is proposed and demonstrated. The output of the GRO is digitized by the combination of a counter and a phase-to-digital converter (PDC) producing an integer and a fractional digital value, respectively. Due to the delay mismatches between two paths, the integer and fractional digital values are not synchronized thereby causing calculation errors. In order to reduce the errors, a correction bit (CB) is generated and then the erroneous output is fixed by the addit

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Castillo, Danilo Aparecido Carnevale, João Soares Cavalcante, Bruno Cavalcante Sanches, Wilhelmus Adrianus Maria Van Noije, and Rodrigo Trevisoli Doria. "An Enhanced CMOS 65 Nm Front-End for Cervical Cancer Detection through Bioimpedance Spectroscopy." ECS Meeting Abstracts MA2025-01, no. 36 (2025): 1714. https://doi.org/10.1149/ma2025-01361714mtgabs.

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This work presents the design and validation of a front-end structure targeting the Electrical Bio-Impedance Spectroscopy (EBS) application for Cervical Cancer Detection (CCD). The EBS technique for cancer screening hinges on assessing an eventually anomalous demeanour in the Electrical Impedance of a specified tissue due to the existence of cancerous cells throughout a particular frequency spectrum. In specific, the tissue’s impedance primarily depends on its inner cellular structures within the interval from a few kHz to 1 MHz, historically denominated as the “βdispersion zone”. The forecite

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Chen, Yan, Yousheng Chen, Yan Guo, and Chunxia Li. "A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting." Electronics 8, no. 9 (2019): 986. http://dx.doi.org/10.3390/electronics8090986.

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A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show

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Petrullo, Lauren, Stan Boutin, Jeffrey E. Lane, Andrew G. McAdam, and Ben Dantzer. "Phenotype–environment mismatch errors enhance lifetime fitness in wild red squirrels." Science 379, no. 6629 (2023): 269–72. http://dx.doi.org/10.1126/science.abn0665.

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Mismatches between an organism’s phenotype and its environment can result in short-term fitness costs. Here, we show that some phenotype – environment mismatch errors can be explained by asymmetrical costs of different types of errors in wild red squirrels. Mothers that mistakenly increased reproductive effort when signals of an upcoming food pulse were absent were more likely to correctly increase effort when a food pulse did occur. However, mothers that failed to increase effort when cues of an upcoming food pulse were present suffered lifetime fitness costs that could only be offset through

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Kim, Seok-Kyoon. "Proportional-Type Output Voltage-Tracking Controller for Interleaved DC/DC Boost Converter with Performance Recovery Property." Mathematical Problems in Engineering 2018 (2018): 1–12. http://dx.doi.org/10.1155/2018/2536946.

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This paper proposes an offset-free proportional-type output voltage-tracking algorithm embedding the disturbance observers (DOBs) for the N-phase interleaved DC/DC boost converter through a systematical multivariable approach. The contributions of this article fall into two parts. The first one is to design the first-order nonlinear DOBs for exponentially estimating the disturbances caused by the model-plant mismatches. The second one is to prove that the proposed proportional-type controller equipped with the DOBs guarantees the performance recovery property as well as the offset-free propert

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Rahman, Dzul, Kamelia Quzwain, and Nadia Media Rizka. "Validasi Antena Offset Reflektor." Journal of Informatics and Communication Technology (JICT) 4, no. 2 (2023): 55–62. http://dx.doi.org/10.52661/j_ict.v4i2.135.

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Dalam sistem komunikasi seluler Fifth-Generation (5G) terdapat subjek teknik yang baru seperti millimeter wave, ukuran sel yang kecil, dan multibeam di stasiun pangkalan yang akan diperkenalkan terkait dengan teknologi gelombang radio. Antena offset reflektor dapat digunakan pada aplikasi millimeter wave karena mampu menghasilkan gain yang tinggi. Projek ini menjelaskan pembuatan antena offset dual-reflector dengan menggunakan teknik shaping. Model antena offset reflektor berhasil didesain dengan menggunakan pemograman MATLAB. Untuk memvalidasi program MATLAB tersebut, simulasi dengan mengguna

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