Journal articles: 'Gain-boosting of cascode amplifiers'

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Wang, Lin Feng, Qiao Meng, and Hao Zhi. "Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth." Applied Mechanics and Materials 614 (September 2014): 237–40. http://dx.doi.org/10.4028/www.scientific.net/amm.614.237.

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This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.

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Raman, J., P. Rombouts, and L. Weyten. "Folded-cascode amplifier with efficient feedforward gain-boosting." Electronics Letters 46, no. 21 (2010): 1425. http://dx.doi.org/10.1049/el.2010.2543.

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BEN-ESMAEL, M., F. J. LIDGEY, K. HAYATLEH, and B. L. HART. "GAIN-BANDWIDTH TRADE-OFF IN THE CMOS CASCODE AMPLIFIER." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350013. http://dx.doi.org/10.1142/s0218126613500138.

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The cascode amplifier has the potential of providing high gain and high bandwidth simultaneously. However, the design is not as intuitive as one might at first think. In this paper, we present a detailed analysis of the single cascode amplifiers. The relationship between gain and bandwidth is important. When used to achieve maximum bandwidth the voltage gain of the common-source stage is close to unity. However, when the cascode is designed to obtain a high voltage gain, then the gain-bandwidth trade-off, typical in the common source amplifier, reappears. This analysis is used to provide the basis for practical cascode amplifier design.

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Monsurrò, Pietro, Salvatore Pennisi, Giuseppe Scotti, and Alessandro Trifiletti. "0.9-V CMOS cascode amplifier with body-driven gain boosting." International Journal of Circuit Theory and Applications 37, no. 2 (March 2009): 193–202. http://dx.doi.org/10.1002/cta.539.

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Assaad, Rida, and Jose Silva-Martinez. "Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers." VLSI Design 2009 (July 28, 2009): 1–11. http://dx.doi.org/10.1155/2009/323595.

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Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

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Wang, Zhe Fei, Yi Jiang Cao, and Ju Meng Feng. "A Design of High Performance CMOS Folded Cascode Operational Amplifier." Advanced Materials Research 981 (July 2014): 31–35. http://dx.doi.org/10.4028/www.scientific.net/amr.981.31.

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This paper describes a kind of folded cascode amplifier, which not only has high gain, large output swing characteristics, and its outputs can be self-compensation, it has a strong suppression capability with voltage noise. Based on a 0.5μm CMOS process uses two operational amplifiers. Through software emulation corrected the error which was caused by theoretical calculation. Has good performance in gain, noise, swing, phase margin, common mode rejection ratio and other parameters.

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Akbari, Meysam, and Omid Hashemipour. "Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits." Journal of Circuits, Systems and Computers 25, no. 11 (August 14, 2016): 1650144. http://dx.doi.org/10.1142/s0218126616501449.

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In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

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He, Fei, Qian Xie, and Zheng Wang. "A study on gain boosting techniques of cascode amplifier at near-f frequencies based on gain plane approach." Microelectronics Journal 112 (June 2021): 105064. http://dx.doi.org/10.1016/j.mejo.2021.105064.

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Idros, Norhamizah, Zulfiqar Ali Abdul Aziz, and Jagadheswaran Rajendran. "A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier." Microelectronics International 37, no. 4 (September 11, 2020): 205–13. http://dx.doi.org/10.1108/mi-05-2020-0030.

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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Basu, Joydeep, and Pradip Mandal. "Switched-Capacitor Common-Mode Feedback-Based Fully Differential Operational Amplifiers and its Usage in Implementation of Integrators." Journal of Circuits, Systems and Computers 29, no. 14 (March 20, 2020): 2050223. http://dx.doi.org/10.1142/s0218126620502230.

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For stabilizing the common-mode output voltage of fully differential operational amplifiers, switched-capacitor (SC) type of common-mode feedback (CMFB) is a familiar technique. This is appropriate for implementing high-gain wide-swing low-power op-amps due to its benefits of minimum power consumption, superior linearity across a large amplifier output swing range, and improved feedback loop stability in comparison to continuous-time CMFB. However, the usage of SC-CMFB requires careful attention to some realistic aspects, details of many of which are available in literature. Nonetheless, its adverse effect on the op-amp’s differential-mode gain has not been investigated much. The explanation for this effect is the SC-CMFB-induced equivalent resistive loading, and this is particularly significant in amplifiers like folded cascode which are intended to provide a high gain. This issue of drop in op-amp dc gain because of SC-CMFB, and the consequence on the realization of continuous-time and discrete-time forms of integrators utilizing such amplifiers is the topic of discussion in this paper. Relevant analytical derivations and circuit simulations at the transistor level are provided. A couple of design guidelines and circuit topologies for minimizing the loading-induced gain reduction are also presented.

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Lee, Samuel B. S., Hang Liu, Kiat Seng Yeo, Jer-Ming Chen, and Xiaopeng Yu. "Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS." Electronics 9, no. 7 (June 27, 2020): 1058. http://dx.doi.org/10.3390/electronics9071058.

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This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

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Sahu, Rashmi, Maitraiyee Konar, and Sudip Kundu. "Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers." Micro and Nanosystems 12, no. 3 (December 1, 2020): 168–74. http://dx.doi.org/10.2174/1876402912666200123153318.

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Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

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Malz, Stefan, Bernd Heinemann, Rudolf Lachner, and Ullrich R. Pfeiffer. "J-band amplifier design using gain-enhanced cascodes in 0.13 μm SiGe." International Journal of Microwave and Wireless Technologies 7, no. 3-4 (May 26, 2015): 339–47. http://dx.doi.org/10.1017/s175907871500080x.

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This paper presents two J-band amplifiers in different 0.13 μm SiGe technologies: a small signal amplifier (SSA) in a technology in which never before gain has been shown over 200 GHz; and a low noise amplifier (LNA) design for 230 GHz applications in an advanced SiGe HBT technology with higher fT/fmax, demonstrating the combination of high gain, low noise, and low power in a single amplifier. Both circuits consist of a four-stage pseudo-differential cascode topology. By employing series–series feedback at the single-stage level the small-signal gain is increased, enabling circuit operation at high-frequencies and with improved efficiency, while maintaining unconditional stability. The SSA was fabricated in a SiGe BiCMOS technology by Infineon with fT/fmax values of 250/360 GHz. It has measured 19.5 dB gain at 212 GHz with a 3 dB bandwidth of 21 GHz. It draws 65 mA from a 3.3 V supply. On the other hand, a LNA was designed in a SiGe BiCMOS technology by IHP with fT/fmaxof 300/450 GHz. The LNA has measured 22.5 dB gain at 233 GHz with a 3 dB bandwidth of 10 GHz and a simulated noise figure of 12.5 dB. The LNA draws only 17 mA from a 4 V supply. The design methodology, which led to these record results, is described in detail with the LNA as an example.

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Shivan, T., E. Kaule, M. Hossain, R. Doerner, T. Johansen, D. Stoppel, S. Boppel, W. Heinrich, V. Krozer, and M. Rudolph. "Design and modeling of an ultra-wideband low-noise distributed amplifier in InP DHBT technology." International Journal of Microwave and Wireless Technologies 11, no. 7 (May 3, 2019): 635–44. http://dx.doi.org/10.1017/s1759078719000515.

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AbstractThis paper reports on an ultra-wideband low-noise distributed amplifier (LNDA) in a transferred-substrate InP double heterojunction bipolar transistor (DHBT) technology which exhibits a uniform low-noise characteristic over a large frequency range. To obtain very high bandwidth, a distributed architecture has been chosen with cascode unit gain cells. Each unit cell consists of two cascode-connected transistors with 500 nm emitter length and ft/fmax of ~360/492 GHz, respectively. Due to optimum line-impedance matching, low common-base transistor capacitance, and low collector-current operation, the circuit exhibits a low-noise figure (NF) over a broad frequency range. A 3-dB bandwidth from 40 to 185 GHz is measured, with an NF of 8 dB within the frequency range between 75 and 105 GHz. Moreover, this circuit demonstrates the widest 3-dB bandwidth operation among all reported single-stage amplifiers with a cascode configuration. Additionally, this work has proposed that the noise sources of the InP DHBTs are largely uncorrelated. As a result, a reliable prediction can be done for the NF of ultra-wideband circuits beyond the frequency range of the measurement equipment.

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Centurelli, Francesco, Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti, and Alessandro Trifiletti. "A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate." Electronics 10, no. 14 (July 9, 2021): 1638. http://dx.doi.org/10.3390/electronics10141638.

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A novel architecture and design approach which make it possible to boost the bandwidth and slew-rate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

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Lahiji, Rosa R., Linda P. B. Katehi, and Saeed Mohammadi. "A wideband CMOS distributed amplifier with slow-wave shielded transmission lines." International Journal of Microwave and Wireless Technologies 3, no. 1 (November 15, 2010): 59–66. http://dx.doi.org/10.1017/s1759078710000772.

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A four-stage distributed amplifier utilizing low-loss slow-wave shielded (SWS) transmission lines is implemented in a standard 0.13 μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The amplifier when biased in its high current operating mode of IDtotal = 46 mA (at Vdd = 2.2 V, Pdiss = 101 mW) provides a forward transmission gain of 11.3 ± 1.5 dB with a 3-dB bandwidth of 17 GHz and a gain-bandwidth product of 74 GHz. The noise figure (NF) under the same bias condition is better than 8.5 dB up to 10 GHz. The measured output-referred 1-dB compression point is higher than +2 dBm. The amplifier is also measured under low-bias condition of IDtotal = 18 mA (at Vdd = 1.15 V, Pdiss = 20.7 mW). It provides a transmission gain of 6.6 ± 1 dB, a 3-dB bandwidth of 14.8 GHz, a gain-bandwidth product of 35.5 GHz, and a NF of better than 8.6 dB up to 10 GHz. Despite using a simple four-stage cascode design, this distributed amplifier achieves very high-gain-bandwidth product at a relatively low DC power compared to the state of the art CMOS distributed amplifiers reported in the literature. This is due to the incorporation of low-loss SWS coplanar waveguide (CPW) transmission lines with a loss factor of nearly 50% of that of standard transmission lines on CMOS-grade Si substrate.

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Fu, Ximing, Kamal El-Sankary, and Yadong Yin. "A High Bandwidth-Power Efficiency, Low THD2,3 Driver Amplifier with Dual-Loop Active Frequency Compensation for High-Speed Applications." Electronics 10, no. 18 (September 20, 2021): 2311. http://dx.doi.org/10.3390/electronics10182311.

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This paper presents a driver amplifier with high bandwidth-power efficiency, high capacitor-driving capacity, and low total harmonic distortion (THD). One complementary differential pair composed of self-cascode transistors is incorporated to obtain a full input voltage swing. Flipped voltage follower (FVF) buffers are applied as second stage to drive the last class-AB output stage. Moreover, a dual-loop active-feedback frequency compensation (DLAFC) is presented, which can stabilize the proposed multistage amplifier and keep the dominant pole on high frequency to obtain high-frequency total harmonic distortion (THD) suppression. To achieve a low-frequency phase margin protection (PMP), one left half-plane (LHP) zero is introduced to compensate for the nondominant pole caused by the load capacitor. Meanwhile, two high-frequency LHP zeros are injected to achieve high-frequency phase margin boosting (PMB) and reduce the amplifier’s settling time and integration area. This proposed amplifier is implemented in a standard DBH 0.18 μm 5 V CMOS process, and it achieves over 115-dB DC gain, 150–300 MHz GBW under 0–100 p load capacitors, ultra-high THD2,3 suppression ranges from 100 kHz to 10 MHz under 1–2 V output swing, and over 250 V/μs average slew rate, by only dissipating 12.5 mW at 5 V power supply.

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ZHAO, HONGLIANG, YIQIANG ZHAO, YIWEI SONG, JUN LIAO, and JUNFENG GENG. "A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA." Journal of Circuits, Systems and Computers 22, no. 10 (December 2013): 1340033. http://dx.doi.org/10.1142/s0218126613400331.

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A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

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Tessmann, Axel, Volker Hurm, Arnulf Leuther, Hermann Massler, Rainer Weber, Michael Kuri, Markus Riessle, et al. "243 GHz low-noise amplifier MMICs and modules based on metamorphic HEMT technology." International Journal of Microwave and Wireless Technologies 6, no. 3-4 (February 25, 2014): 215–23. http://dx.doi.org/10.1017/s1759078714000166.

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Two compact H-band (220–325 GHz) low-noise millimeter-wave monolithic integrated circuit (MMIC) amplifiers have been developed, based on a grounded coplanar waveguide (GCPW) technology utilizing 50 and 35 nm metamorphic high electron mobility transistors (mHEMTs). For low-loss packaging of the circuits, a set of waveguide-to-microstrip transitions has been realized on 50-μm-thick GaAs substrates demonstrating an insertion loss of <0.5 dB at 243 GHz. By applying the 50 nm gate-length process, a four-stage cascode amplifier module achieved a small-signal gain of 30.6 dB at 243 GHz and more than 28 dB in the bandwidth from 218 to 280 GHz. A second amplifier module, based on the 35-nm mHEMT technology, demonstrated a considerably improved gain of 34.6 dB at 243 GHz and more than 32 dB between 210 and 280 GHz. At the operating frequency, the two broadband low-noise amplifier modules achieved a room temperature noise figure of 5.6 dB (50 nm) and 5.0 dB (35 nm), respectively.

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Ellinger, F., U. Jorges, U. Mayer, and R. Eickhoff. "Analysis and Compensation of Phase Variations Versus Gain in Amplifiers Verified by SiGe HBT Cascode RFIC." IEEE Transactions on Microwave Theory and Techniques 57, no. 8 (August 2009): 1885–94. http://dx.doi.org/10.1109/tmtt.2009.2025415.

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Cheng, Qi, Weimin Li, Xian Tang, and Jianping Guo. "Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques." Electronics 8, no. 5 (May 23, 2019): 572. http://dx.doi.org/10.3390/electronics8050572.

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This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.

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Nguyen, Huy Hoang, Duy Manh Luong, and Gia Duong Bach. "A Novel Independently Biased 3-Stack GaN HEMT Configuration for Efficient Design of Microwave Amplifiers." Applied Sciences 9, no. 7 (April 11, 2019): 1510. http://dx.doi.org/10.3390/app9071510.

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The power amplifier (PA) and low-noise amplifier (LNA) are the most critical components of transceiver systems including radar, mobile communications, satellite communications, etc. While the PA is the key component of the transmitter (TX), the LNA is the key component of the receiver (RX) of the transceiver system. It is pointed out that traditional design approaches for both the LNA and PA face challenging drawbacks. When designing an LNA, the power gain and noise figure of the LNA are difficult to improve simultaneously. For PA design, it indicates that efficiency and linearity of the PA are also hard to improve simultaneously. This study aims to surmount this by proposing a novel independently biased 3-stack GaN high-electron-mobility transistor (HEMT) configuration for efficient design of both PA and LNA for next generation wireless communication systems. By employing an independently biased technique, the proposed configuration can offer superior performance at both small-signal (SS) for LNA design and large-signal (LS) for PA design compared with other typical circuit configurations. Simulation results show that by utilizing an adaptive bias control of each transistor of the proposed configuration, both power gain and noise figure can be improved simultaneously for the LNA design. Moreover, efficiency and linearity can be also improved at the same time for the PA design. Compared results with other typical configurations including a single-stage, conventional cascode, independently biased cascode, and conventional 3-stack reveals that the proposed configuration exhibits superior advantages at both SS and LS operation.

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Al-Bayati, Essra E., and R. S. Fyath. "Design and Performance Investigation of a New Distributed Amplifier Architecture for 40 and 100 Gb/s Optical Receivers." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 14, no. 5 (February 3, 2015): 5661–86. http://dx.doi.org/10.24297/ijct.v14i5.5274.

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The design of distributed amplifiers (DAs) is one of the challenging aspects in emerging ultra high bit rate optical communication systems. This is especially important when implementation in submicron silicon complementary metal oxide semiconductor (CMOS) process is considered. This work presents a novel design scheme for DAs suitable for frontend amplification in 40 and 100 Gb/s optical receivers. The goal is to achieve high flat gain and low noise figure (NF) over the ultra wideband operating bandwidth (BW). The design scheme combines shifted second tire (SST) matrix configuration with cascode amplification cell configuration and uses m-derived technique. Performance investigation of the proposed DA architecture is carried out and the results are compared with that of other DA architectures reported in the literature. The investigation covers the gain and NF spectra when the DAs are implemented in 180, 130, 90, 65 and 45 CMOS standards.The simulation results reveal that the proposed DA architecture offers the highest gain with highest degree of flatness and low NF when compared with other DA configurations. Gain-BW products of 42772 and 21137 GHz are achieved when the amplifier is designed for 40 and 100 Gb/s operation, respectively, using 45 nm CMOS standard. Thesimulation is performed using AWR Microwave Office (version 10).

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FATHIANPOUR, A., and S. SEYEDTABAII. "EVOLUTIONARY SEARCH FOR OPTIMIZED LNA COMPONENTS GEOMETRY." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450011. http://dx.doi.org/10.1142/s021812661450011x.

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In this paper, an optimized design procedure based on genetic algorithm (GA) for automatic synthesis of dual-band concurrent fully integrated low-noise amplifiers (LNA) targeted to 802.16d @ 3.5 GHz and 802.11b, g @ 2.4 GHz standards is discussed. The algorithm delivers the circuit elements geometry, rather than their values, and bias levels to secure the best level of LNA gain, input matching, output matching and power consumption. Working on the components geometry level aims at considering the elements parasitic effects. The basic cascode and a current reuse folded cascode LNA's are tried. GA as an optimization engine is programmed in MATLAB and performance evaluation in 0.18 μm RF CMOS TSMC technology is ceded to HSPICE. Results indicate that the automated scheme well computes the desired circuit in an acceptable time span; otherwise, it may be explored by either tremendous manual trial and error or astronomical cycles of an exhaustive search. This is not accomplished without imposing certain approximate search space constraints.

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Petricli, Ibrahim, Hadi Lotfi, and Andrea Mazzanti. "Analysis and Design of D-Band Cascode SiGe BiCMOS Amplifiers With Gain-Bandwidth Product Enhanced by Load Reflection." IEEE Transactions on Microwave Theory and Techniques 69, no. 9 (September 2021): 4059–68. http://dx.doi.org/10.1109/tmtt.2021.3094468.

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Castagnola, Juan L., Fortunato C. Dualibe, Agustín M. Laprovitta, and Hugo García-Vázquez. "A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio." Electronics 9, no. 5 (May 11, 2020): 785. http://dx.doi.org/10.3390/electronics9050785.

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This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

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Weng, Ow Tze, Suhaila Isaak, and Yusmeeraz Yusof. "Low Power CMOS Electrocardiogram Amplifier Design for Wearable Cardiac Screening." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 3 (June 1, 2018): 1830. http://dx.doi.org/10.11591/ijece.v8i3.pp1830-1836.

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The trend of health care screening devices in the world is increasingly towards the favor of portability and wearability. This is because these wearable screening devices are not restricting the patient’s freedom and daily activities. While the demand of low power and low cost biomedical system on chip is increasing in exponential way, the front-end electrocardiogram (ECG) amplifiers are still suffering from flicker noise for low frequency cardiac signal acquisition, 50Hz power line electromagnetic interference, and the large unstable input offsets due to the electrode-skin interface is not attached properly. In this paper, a CMOS based ECG amplifier that suitable for low power wearable cardiac screening is proposed. The amplifier adopts the highly stable folded cascode topology and later being implemented into RC feedback circuit for low frequency DC offset cancellation. By using 0.13µm CMOS technology from Silterra, the simulation results show that this front-end circuit can achieve a very low input referred noise of 1pV/Hz1/2 and high common mode rejection ratio of 174.05dB. It also gives voltage gain of 75.45dB with good power supply rejection ratio of 92.12dB. The total power consumption is only 3µW and thus suitable to be implemented with further signal processing and classification back end for low power wearable biomedical device.<br /><br />

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Liu, Min, Panpan Xu, Jincan Zhang, Bo Liu, and Liwen Zhang. "A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications." Circuit World 46, no. 4 (April 2, 2020): 243–48. http://dx.doi.org/10.1108/cw-05-2019-0046.

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Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

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ALLSTOT, DAVID J., SANKARAN ANIRUDDHAN, MIN CHU, JEYANANDH PARAMESH, and SUDIP SHEKHAR. "RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 377–428. http://dx.doi.org/10.1142/s0129156405003247.

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Several state-of-the-art wireless receiver architectures are presented including the traditional super-heterodyne, the image-reject heterodyne, the direct-conversion, and the very-low intermediate frequency (VLIF). The case studies are followed by a detailed view of receiver building blocks: low-noise amplifiers (LNA), mixers, and voltage-controlled oscillators (VCO). Two popular topologies currently exist for LNAs: the common-gate configuration, which offers low power consumption with superior stability, robustness and linearity performance, and its common-source counterpart, which provides comparatively higher gain and lower noise figure. Aside from the traditional passive and active Gilbert mixers, the even-harmonic and masking-quadrature mixers are developed to combat second-order non-linearity and improve image-rejection, respectively. For quadrature carrier generation, the degeneration-injected QVCO is superior to the cascode-injected QVCO both in terms of phase noise and tuning range. The Colpitts QVCO is attractive as a low-noise alternative as it does not disturb the output voltage as much as its traditional LC counterpart and thus offers lower phase noise.

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Ismail, Khadijah, P. Susthitha Menon, Sahbudin Shaari, Abang Annuar Ehsan, Hesham Bakarman, Norhana Arsad, and Ahmad Ashrif A. Bakar. "Gain performance of cascaded and hybrid semiconductor optical amplifier in CWDM system." Journal of Nonlinear Optical Physics & Materials 23, no. 01 (March 2014): 1450007. http://dx.doi.org/10.1142/s0218863514500076.

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The incorporation of cascaded and hybrid-type optical amplifiers into the optical fiber link is advantageous for the purpose of achieving wide gain bandwidth of multi-wavelength coarse wavelength division multiplexing (CWDM) systems. Different amplifiers whose operating gain region differ from each other are connected in cascade, thus providing better gain performance as the overall gain is combined and flattened over a larger spectrum. In this paper, the effect of the crossover of the uniform gain of the semiconductor optical amplifier (SOA) and the nonuniform gain of erbium-doped fiber amplifier (EDFA) is analyzed using an in-line cascaded SOA-SOA and an in-line hybrid SOA-EDFA configuration in the amplification of an 8-channels CWDM system obtained from the simulation using Optisystem software. It was observed that the cascaded SOA-SOA produces higher gain of 25 dB and wider gain bandwidth of 60 nm compared to the hybrid SOA-EDFA configuration with maximum gain of only 24 dB and 40 nm bandwidth. In addition, better bit-error-rate (BER) performance which is within the typical values in optical fiber communication is also achieved from the cascaded SOA topology. Wider gain bandwidth obtained with the SOA-SOA configuration would permit the transmission of video application at 1551 nm in the proposed Ethernet CWDM system transmitted at 100 Mb/s data rates.

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Lee, Ji-Young, and Tae-Yeoul Yun. "High-gain mixer using cascode current bleeding andgm-boosting techniques." Microwave and Optical Technology Letters 59, no. 1 (November 24, 2016): 1–6. http://dx.doi.org/10.1002/mop.30215.

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Nguyen, Van-Viet, Hyohyun Nam, Bok-Hyung Lee, Muk-Kyo Lee, Sun-Youl Choi, Jeong-Moon Song, and Jung-Dong Park. "A 2-13 GHz Bi-directional Gain Amplifier with Asymmetric Unit-cell using Cascade Gain Boosting." Journal of the Institute of Electronics and Information Engineers 55, no. 12 (December 31, 2018): 65–71. http://dx.doi.org/10.5573/ieie.2018.55.12.65.

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Lee, Min Chin, Zth Ru Yang, and Zth Jing Hu. "Implementation of Rail-to-Rail Operational Amplifier for Biomedical Applications." Applied Mechanics and Materials 130-134 (October 2011): 434–37. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.434.

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This paper proposes gain boosting architecture of a rail-to-rail folded cascaded operational amplifier with CMFB scheme that employing fully differential pair amplifier for applications to biomedical signal process. The proposed rail-to-rail folded cascaded single stage OPA is design and implemented using the TSMC 0.35μm CMOS 2P4M process. Based on simulated and measured results , the chip size is with power dissipation about 1.6mW, input common mode votage range from 0V to 3.3 V, maximum DC gain 82 dB, 114 dB CMRR and 86 dB PSRR.

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Song, Ming Xin, Yue Li, and Meng Meng Xu. "Design of High Gain CMOS Folded Cascode Operational Amplifier." Applied Mechanics and Materials 389 (August 2013): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.389.573.

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A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

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Chaudhry, Q., R. Alidio, G. Sakamoto, and T. Cisco. "A SiGe MMIC variable gain cascode amplifier." IEEE Microwave and Wireless Components Letters 12, no. 11 (November 2002): 424–25. http://dx.doi.org/10.1109/lmwc.2002.805533.

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Asiyabi, Tayebeh, and Jafar Torfifard. "Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 379–87. http://dx.doi.org/10.1166/jolpe.2019.1623.

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In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simultaneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and largesignal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65° phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 μW from 1.8 V.

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Majidi-Ahy, R., C. Nishimoto, M. Riaziat, M. Glenn, S. Silverman, S. L. Weng, Y. C. Pao, G. Zdasiuk, S. Bandy, and Z. Tan. "100-GHz high-gain InP MMIC cascode amplifier." IEEE Journal of Solid-State Circuits 26, no. 10 (1991): 1370–78. http://dx.doi.org/10.1109/4.90088.

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Ibrahim, Abu Bakar, Che Zalina Zulkifli, Shamsul Arrieya Ariffin, and Nurul Husna Kahar. "High frequency of low noise amplifier architecture for WiMAX application: A review." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (June 1, 2021): 2153. http://dx.doi.org/10.11591/ijece.v11i3.pp2153-2164.

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The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure.

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Kaur, Gaganpreet, Sanjay Sharma, and Gurmeet Kaur. "Novel Raman Parametric Hybrid L-Band Amplifier with Four-Wave Mixing Suppressed Pump for Terabits Dense Wavelength Division Multiplexed Systems." Advances in Optical Technologies 2016 (February 15, 2016): 1–8. http://dx.doi.org/10.1155/2016/6148974.

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We demonstrate improved performance of parametric amplifier cascaded with Raman amplifier for gain of 54.79 dB. We report amplification of L-band using 100 × 10 Gbps Dense Wavelength Division Multiplexed (DWDM) system with 25 GHz channel spacing. The gain achieved is the highest reported so far with gain flatness of 3.38 dB without using any gain flattening technique. Hybrid modulated parametric pump is used for suppressing four-wave mixing (FWM) around pump region, resulting in improvement of gain flatness by 2.42 dB. The peak to peak variation of gain is achieved less than 1.6 dB. DWDM system with 16-channel, 25 GHz spaced system has been analyzed thoroughly with hybrid modulated parametric pump amplified Raman-FOPA amplifier for gain flatness and improved performance in terms of BER and Q-factor.

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Saxena, Nikhil, Pankaj Agarwal, and Sonal Soni. "Design and Analysis of Cascode Amplifier with Improved Gain." Journal of Computational and Theoretical Nanoscience 14, no. 11 (November 1, 2017): 5654–56. http://dx.doi.org/10.1166/jctn.2017.7027.

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Cellucci, Danilo, Francesco Centurelli, Valerio Di Stefano, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, and Alessandro Trifiletti. "0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias." International Journal of Circuit Theory and Applications 48, no. 1 (September 13, 2019): 15–27. http://dx.doi.org/10.1002/cta.2703.

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Aghaee, Toktam, Sadegh Biabanifard, and Abbas Golmakani. "Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input path." Analog Integrated Circuits and Signal Processing 90, no. 1 (October 14, 2016): 237–46. http://dx.doi.org/10.1007/s10470-016-0874-2.

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Mallick, Bandana, Bibhu Prasad, and Dr Krishna Chandra Patra. "Design of a Hybrid Optical amplifier for 64 DWDM Channels network by using EDFA and Raman Amplifier." International Journal of Electrical and Electronics Research 5, no. 4 (December 31, 2017): 18–23. http://dx.doi.org/10.37391/ijeer.050401.

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In this paper a hybrid amplifier EDFA-RAMAN DWDM transmission system is proposed and demonstrated. A new hybrid two-stage optical fiber amplifier for dense wavelength division multiplexing (DWDM) network is observed. The hybrid amplifier is cascaded erbium- doped fiber amplifiers (EDFA) & Raman amplifier which provide a nearly flat gain over 80 nm. The hybrid amplifier has been modeled using an Optic-System version 14 on a DWDM transmission. In this paper we compare Q-factor at different input power i.e. at 0db and at 10 db. Here two different types of apodized function (Uniform & Gaussian) are selected as fiber Bragg grating parameters and system performance is analyzed. Performance of the system is analyzed by using BER analyzer.

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Juang, C., S. F. Shiue, S. Y. Tsai, and J. N. Yang. "Transimpedance amplifiers using three cascade variable inverter gain stages." Analog Integrated Circuits and Signal Processing 49, no. 3 (September 11, 2006): 299–302. http://dx.doi.org/10.1007/s10470-006-9706-0.

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Liang, J. Y., and C. S. Aitchison. "Gain performance of cascade of single stage distributed amplifiers." Electronics Letters 31, no. 15 (July 20, 1995): 1260–61. http://dx.doi.org/10.1049/el:19950828.

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Rashtian, Hooman, and Omeed Momeni. "Gain Boosting in Distributed Amplifiers for Close-to-fmax Operation in Silicon." IEEE Transactions on Microwave Theory and Techniques 67, no. 3 (March 2019): 1039–49. http://dx.doi.org/10.1109/tmtt.2019.2894671.

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Zhang, Jing Zhi. "A 520MHz Wideband Variable Gain Amplifier." Applied Mechanics and Materials 556-562 (May 2014): 1564–67. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1564.

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The design and realization of a wideband variable gain amplifier for RF system is presented. The cascade of LNA and controllable attenuation makes the design have a 0-90dB gain adjustment range. Special care is devoted to the solution of typical problems encountered in the design of the amplifier, such as signal shielding and power supply decoupling. The amplifier uses passive amplitude-frequency equalization, 0.1-460MHz band variation is less than 1dB, the 3dB bandwidth is up to 520MHz. The noise characteristic is low, the total input referred noise is less than 15.5nV⁄√¯Hz.

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GOLDSTEIN, EVAN L., and LARS ESKILDSEN. "ERBIUM-DOPED FIBER AMPLIFIERS FOR MULTIWAVELENGTH LIGHTWAVE NETWORKS: IMPACT OF THE NON-FLAT GAIN SPECTRUM." International Journal of High Speed Electronics and Systems 07, no. 01 (March 1996): 37–54. http://dx.doi.org/10.1142/s0129156496000037.

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The effort to build amplified multiwavelength lightwave networks that are large and reconfigurable has raised a host of hard technological challenges, ranging from device-level difficulties to transmission engineering to network-management concerns. Not least of these are the challenges posed by the spectral gain nonuniformities, and the associated multiwavelength noise performance, of such a network's cascaded optical amplifiers. This paper catalogs the research challenges posed by multiwavelength amplification in networks, summarizes the theory underlying them, and describes approaches that are emerging to lessen their ill effects.

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Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

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Lee, Changhyun, and Changkun Park. "2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain." Scientific World Journal 2014 (2014): 1–5. http://dx.doi.org/10.1155/2014/967181.

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We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is1.4×0.6 mm2.

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Journal articles on the topic 'Gain-boosting of cascode amplifiers'

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