Dissertations / Theses on the topic 'GaN MMIC Power Amplifiers'

With the growth of smart phones, the demand for more broadband, data centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4th generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use non-constant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10mm x 11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high effi-ciencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

In this research, an innovative phased array antenna module is proposed to implement a high-power, high-efficient and compact C-band radio transmitter. The module configuration, which can be integrated into front-end circuits, was designed as planar layers stacked up together to form a metallic cube. The layers were fabricated by using a Computer Numerical Control (CNC) milling machine and screwed together. The antenna parts and the amplifier units were designed at two opposite sides of the cube to spread the dissipated heat produced by the amplifiers and act as a heat sink. Merging the antenna parts with the amplifier circuits offers additional advantages such as decreasing the total power loss, mass, and volume of the transmitter modules by removing the extra power divider and combiner networks and connectors between them as well as reducing the total signal path. To achieve both a maximum possible radiation efficiency and high directivity, the aperture waveguide antenna was selected as the array element. Four antenna elements have been located in a cavity to be excited equally and the cavity is excited through a slot on its underside so a compact subarray is formed. Antenna measurements demonstrated a 15.5 dBi gain and 20 dB return loss at 10 % fractional bandwidth centered around 5.8 GHz and with more than 98% radiation efficiency. The total dimensions of the subarray are approximately 8*12*4 cm3. The outcoming signal from the amplifiers is transferred into the slot exciting the subarray through a microstrip-to-waveguide transition (MWT). A novel and robust MWT structure was designed for the presented application. The MWT was also integrated with a microstrip coupler to monitor the power from the amplifier output. The measured insertion loss of the MWT along with the microstrip coupler was less than 0.25 dB along with more than 20 dB return loss within the same bandwidth of the subarray. The microstrip coupler shows 38 dB of coupling and more than 48 dB of isolation with negligible effects on the amplifier output signal and the insertion/return loss of the MWT. The amplifier subcomponents consist of power combiners/dividers (PCDs), high power amplifiers (HPAs) and bias circuitry. A Monolithic Microwave Integrated Circuit (MMIC) three-stage HPA was designed in a commercially available 0.15 um AlGaN/GaN HEMT technology provided by National Research Council Canada (NRC) and occupies an area of 4.7*3.7 mm2. To stabilize the HPA, a novel inductive degeneration technique was successfully used. To the best of the author’s knowledge, this is the first time this technique has been used to stabilize HPAs. Careful considerations on input/output impedances of all HEMTs were taken into account to prevent parametric oscillations. Other instability sources, i.e. odd-mode, even-mode, and low frequency (bias circuit) oscillations were also prevented by designing the required stabilization circuits. The electromagnetic simulation of the HPA shows 35 W (45.5 dBm) of saturated output power, 26 dB large signal gain and 29% power added efficiency within the same operating bandwidth as the subarray. The output distortion is less than 27 dB, indicating that the HPA is highly linear. The PCD was designed by utilizing a novel, enhanced configuration of a Gysel structure implemented on Rogers RT-Duroid5880. The insertion loss of the Gysel is less than 0.2 dB while return loss and isolation are greater than 20 dB over the entire bandwidth. The same subarray area (8*12 cm2) has been used for the amplifier circuits and up to eight HPAs can be included in each module. All the above parts of the transmitter module were fabricated and measured, except the MMIC-HPA.

Ces travaux de thèse se concentrent sur la conception d'amplificateur de puissance MMIC large-bande haut rendement en technologie GaN pour des applications militaires de type radar et guerre électronique. Les objectifs principaux sont de proposer des structures innovantes de combinaison de puissance notamment pour réduire la taille des amplificateurs actuels tout en essayant d'améliorer leur rendement dans le même temps. Pour cela, une partie importante de ces travaux consiste au développement de combineurs de puissance ultra compactes et faibles pertes. Une fois ces combineurs réalisés et mesurés, ils sont intégrés dans des amplificateurs de puissance afin de prouver leur fonctionnalité et les avantages qu'ils apportent. Différents types d'amplificateur tant au niveau de l'architecture que desperformances sont réalisés au cours de ces travaux<br>This work focus on the design of wideband and high efficiency GaN MMIC high power amplifiers for military applications such as radar and electronic warfare. The main objectives consist in finding innovative power combining structures in order to decrease the overall size of amplifiers and increasing their efficiency at the same time. For these matters, an important part of this work consisted in the design and realization of ultra compact and low loss power combiners. Once the combiners realized and measured, they are integrated into power amplifiers to prove their functionality and the advantages they bring. Several kind of amplifiers have been realized whether regrind their architecture or their performances

Ce travail répond à un besoin industriel accru en termes d’amplification des signaux sur porteuses à enveloppes variables utilisés par les systèmes de télécommunications actuels. Ces signaux disposent d’un fort PAPR et d’une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. La raison pour laquelle les industriels télécoms requièrent alors des amplificateurs de très fortes puissances de sortie, robustes, fiables et ayant une dépense énergétique optimale le long de la dynamique d’enveloppe associée à un niveau de linéarité acceptable. Ce document expose les résultats d’étude et de réalisation de deux Amplificateurs de Puissance Doherty (APD) à haut rendement encapsulés en boîtiers plastiques QFN. Le premier est un amplificateur Doherty symétrique classique (APD-SE) et le second est un amplificateur à deux entrées RF (APD-DE). Ces démonstrateurs fonctionnant en bande C sont fondés sur l’utilisation de la technologie Quasi-MMIC associant des barrettes de puissance à base des transistors HEMTs AlGaN/GaN sur SiC à des circuits d’adaptation en technologie ULRC. L’approche Quasi-MMIC associée à la solution d’encapsulation plastique QFN permettant une meilleure gestion des comportements thermiques offre des performances électriques similaires à celles de la technologie MMIC avec des coûts et des cycles de fabrication très attractifs. Durant ces travaux, une nouvelle méthode d’évaluation des transistors dédiés à la conception d’amplificateurs Doherty a été développée et mise en oeuvre. L’utilisation intensive des simulations électromagnétiques 2.5D et 3D a permis de bien prendre en compte les effets de couplages entre les différents circuits dans l’environnement du boîtier QFN. Les résultats des tests des amplificateurs réalisés fonctionnant sur une bande de 1GHz ont permis de valider la méthode de conception et ont montré que les concepts avancés associés à l’approche Quasi-MMIC ainsi qu’à des technologies d’encapsulation plastique, peuvent générer des fonctions micro-ondes innovantes. Les caractérisations de l’APD-DE ont relevé l’intérêt inhérent à la préformation des signaux d’excitation et des points de polarisation de chaque étage de l’amplificateur<br>This work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier

Ces travaux de thèse s’intègrent dans le cadre du processus d’amélioration continue de l’efficacité et de la linéarité des amplificateurs de puissance en présence des signaux sur porteuses modulées utilisés par les systèmes de télécommunications modernes.Ces signaux présentent un PAPR élevé et une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. De ce fait, les amplificateurs de puissance conventionnel (classe AB à polarisation fixe) sont souvent surdimensionnés pour répondre aux besoins des industriels télécoms. La technique de suivi d’enveloppe a été utilisée pour augmenter la PAE le long de l’OBO (10 dB pour LTE) tout en gardant un gain en puissance constant associé à une bonne linéarité en termes de conversion d’AM/AM. Une méthode de conception d’amplificateur de puissance en technologie MMIC fondé sur l’utilisation des HEMTs GaN a été développée et utilisée pour concevoir un AP délivrant une puissance de sortie de 4W et fonctionnant en bande K [17-20GHz]. L’AP réalisé a été ensuite couplé à un modulateur numérique de polarisation de drain. L’ensemble AP et modulateur de polarisation constituant un système de suivi d’enveloppe appelé APSE a été caractérisé en termes d’efficacité et de linéarité en présence de signaux modulés. L’APSE montre des performances très intéressantes comparées à celles obtenue avec un AP à polarisation fixe. En effet à un OBO de l’ordre de 7dB, dans la bande [17-20GHz], la PAE est améliorée de [10-7.5 points]. La PAE moyenne le long de l’OBO varie entre 32 et 36% sur la bande considérée et elle est associée à une EVM variant entre 5 à 1.6% avec une DPD quasi-statique appliquée au signal en bande de base. Les caractérisations de l’APSE ont démontré l’intérêt de l’utilisation des amplificateurs de puissance à suivi d’enveloppe dans les systèmes de télécommunications modernes<br>This thesis work is part of the process of continuous improvement of the efficiency and linearity of power amplifiers in presence of signals on modulated carriers used in modern telecommunications systems. These signals have a high PAPR and a statistical envelope distribution centered below the envelope peak value. As a result, conventional power amplifiers (Class AB fixed bias) are often oversized to meet the needs of the telecom industry. The envelope tracking technique has been used to increase the PAE along the OBO (10 dB for LTE) while maintaining a constant power gain associated to a good linearity in terms of AM/AM conversion. A power amplifier design method in MMIC technology based on the use of GaN HEMTs has been developed and is used to design an APdelivering an output power of 4W and operating in K-band [17-20GHz]. The realized APwas then coupled to a digital drain bias modulator. The APand bias modulator assembly constituting an envelope tracking system called APSE was characterized in terms of efficiency and linearity in presence of modulated signals. The APSE shows very interesting performances compared to those obtained with a fixed bias AP. Indeed, at an OBO of about 7dB, in the [17-20GHz] band, the PAE is improved by [10-7.5]. The average PAE along the OBO varies between 32 and 36% over the considered band and it is associated to an EVM varying between 5 and 1.6% with a quasi-static DPD applied to the baseband signal.The characterizations of APSE have demonstrated the interest of the use of envelope tracking power amplifiers in modern telecommunications systems

Mestrado em Engenharia Electrónica e Telecomunicações<br>The satellite communications have become a valid alternative to conventional communications, through fiber or copper, in situations of catastrophe or even as complement to improve the quality of the services provided at a worldwide scale. Recently, radio frequency engineers have worked towards a reliable solution to replace the travelling wave tube amplifiers on board of the satellite communications. Despite the travelling wave tube amplifiers reveal a good performance, its weight, size and cost are a serious technical problem to the main satellite manufacturers. However, this scenario tends to change due to the exploitation of the Gallium Nitride technology in high power, efficiency and frequency applications. The objective of this work involves an implementation of two power amplifiers in class B, resorting to a Gallium Nitride transistors and using different types of planar transmission lines, for a 5.8GHz frequency which is often used in uplink transmissions for C-band or even in recent applications of wireless power transmission. The best results were obtained for the microstrip lines power amplifier, achieving 34.1dBm of output power, 62.35% of drain efficiency at saturation and a small-gain of 17dB.<br>As comunicações via satélite têm-se tornado uma alternativa válida às vias de comunicações convencionais, como a fibra e o cobre, em situações de catástrofe ou até como complemento para melhorar a qualidade de serviços disponibilizados à escala global. Recentemente, os engenheiros de rádio frequência têm trabalhado para encontrar uma solução definitiva e fiável para a substituição dos amplificadores a válvulas nos satélites de comunicações. Apesar destes amplificadores apresentarem uma performance de destaque, o seu tamanho, peso, consumo e custo são sérios problemas para as empresas especializadas na sua construção. Contudo, o panorama tende a mudar devido à exploração da tecnologia de Nitreto de Gálio em aplicações de alta potência, frequência e eficiência. O objetivo desta trabalho passa pela implementação de dois amplificadores de potência em classe B, recorrendo a transístores de Nitreto de Gálio e usando diferentes linhas de transmissão planares, para a frequência de 5.8GHz que é frequentemente usada em transmissões uplink na banda C, ou mesmo nas recentes aplicações de transferência de energia sem fios. Os melhores resultados foram obtidos pela implementação em linhas microstrip, atingindo os 34.1dBm de potência de saída, 62.35% de eficiência na saturação e um ganho máximo de 17dB.

Thesis (Ph. D.)--University of California, San Diego, 2006.<br>Title from first page of PDF file (viewed December 13, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.

Dans la course aux développements des technologies, une révolution a été induite par l'apparition des technologies Nitrures depuis deux décennies. Ces technologies à grande bande interdite proposent en effet une combinaison unique tendant à améliorer les performances en puissance, en intégration et en bilan énergétique pour des applications hautes fréquences (bande L à bande Ka en production industrielle). Ces technologies mobilisent fortement les milieux académiques et industriels afin de proposer des améliorations notamment sur les aspects de fiabilité. Les larges efforts consentis par des consortiums industriels et académiques ont permis de mieux identifier, comprendre et maîtriser certains aspects majeurs limitant la fiabilité des composants, et ainsi favoriser la qualification de certaines filières. Cependant, la corrélation et l'analyse physique fine des mécanismes de dégradation suscite encore de nombreux questionnements, et il est indispensable de renforcer ces études par une approche d'analyse multi-outils. Nous proposons dans ce travail de thèse une stratégie d'analyse selon deux aspects majeurs. Le premier concerne la mise en œuvre d'un banc de stress qui autorise le suivi de nombreux marqueurs électriques statiques et dynamiques, sans modifier les conditions de connectiques des dispositifs sous test. Le second consiste à mettre en œuvre un modèle physique TCAD le plus représentatif de la technologie étudiée afin de calibrer le composant à différentes périodes du stress.Le premier chapitre est consacré à la présentation des principaux tests de fiabilité des HEMTs GaN, et des défauts électriques et/ou structuraux recensés dans la littérature ; il y est ainsi fait état de techniques dites non-invasives (c.-à-d. respectant l'intégrité fonctionnelle du composant sous test), et de techniques destructives (c.-à-d. n'autorisant pas de reprise de mesure). Le second chapitre présente le banc de stress à haute fréquence et thermique développé pour les besoins de cette étude ; l'adjonction d'un analyseur de réseau vectoriel commutant sur les quatre voies de tests permet de disposer de données dynamiques fréquentielles, afin d'interpréter les variations du modèle électrique petit-signal des modules sous test à différentes périodes du stress. [...]<br>In the race to technologies development, disruptive wide bandgap GaN devices propose challenging performances for high power and high frequency applications. These technologies strongly mobilize academic and industrial partners in order to improve both the performances and the reliability aspects. Extensive efforts have made it possible to better identify, understand and control first order degradation mechanisms limiting the lifetime of the devices; however, the correlation (and fine physical analysis) of different degradation mechanisms still raises many questions, and it is essential to strengthen these studies by mean of multi-tool analysis approach. In this thesis, we propose a twofold analysis strategy. The first aspect concerns the implementation of a stress bench that allows the monitoring of numerous static and dynamic electrical markers, without removing the devices under test from their environment (in order to have a consistent data set during the period of the strain application). The second aspect consists in implementing a physical TCAD model of the technology under study, in order to calibrate the component before stress, and to tune the model at different periods of stress (still considering stress-dependent parameters potentially affecting the device). The first chapter is devoted to the presentation of the main reliability tests of GaN HEMTs, and of the electrical and/or structural defects identified in the literature; it thus refers to so-called non-invasive techniques (i.e. respecting the functional integrity of the component under test), and destructive techniques (i.e. not allowing additive electrical measurement). The second chapter presents the high frequency and thermal stress bench dedicated to this study; the addition of a vector network analyzer switching between the four test channels provides dynamic frequency data, in order to interpret the variations of the small signal electrical model of the devices under test at different stress periods.[...]

Power amplifiers (PAs) are one of the most crucial elements in wireless standards becasue they are the most power hungry subsystems. These elements have to face an important issue, which is the power efficiency, a fact related with the output back-off (OBO). But the OBO depends on the kind of modulated signal, in proportion to the modulated signal peak-to-average power ratio (PAPR). The higuer is the data rate, the higer is the OBO, and consequently the lower is the efficiency. A low efficiency of PAs causes the waste of energy as heat. Furthermore, the trade-off between linearity and efficiency in PAs is another major issue. To cope with the undesired circumstances producing efficiency degradation, the Doherty power amplifier (DPA) is one of the useful techniques which provide high efficiency for high PAPR of modern communication signals. Nevertheless, the limited bandwidth (BW) of this kind of PAs (about 10% of fractional bandwidth) and its importance (in modern wireless systems such as LTE, WiMAX, Wi-Fi and satellite systems) have encouraged the researchers to improve this drawback in recent years. Some typical BW limiting factors effect on the performance of DPAs: i) quarter-wave length transformers, ii) phase compensation networks in/output matching circuits, iii) offset lines and device non-idealities; The quarter-wave length transformers performs as an inverter impedance in the load modulation technique of DPAs. The future objective in designing DPAs is to decrease the impact of these issues. In this context, this PhD-thesis is focused on improving fractional bandwidth of DPAs using the new methods that are related to impedance transformers instead of impedance inverters in the load modulation technique. This study is twofold. First, it is presented a novel DPA where a wideband GaN DPA in the 2.5 GHz band with an asymmetrical Wilkinson splitter. The impedance transformer of the proposed architecture is based on a matching network including a tapered line with multi-section transformer in the main stage. The BW of this DPA has ranged from 1.8 to 2.7 GHz. Plus, the obtained power efficiency (drain) is higher than 33% in the whole BW at both maximum and OBO power levels. Second, based on the benefits of the Klopfenstein taper, a promising DPA design is proposed where a Klopfenstein taper replaces the tapered line. In fact, this substitution results on reducing the reflection coefficient of the transformer. From a practical prototype realization of this novel Doherty-like PA in the 2.25 GHz band, this modification has demonstrated that the resulting DPA BW is increased in comparison to the conventional topology while keeping the efficiency figures. Moreover, this study also shows that the Klopfenstein taper based design allows an easy tuning of the group delay through the output reactance of the taper, resulting in a more straightforward adjustments than other recently published designs where the quarter-wave transformer is replaced by multi-section transmission lines (hybrid or similar). Experimental results have shown 43-54% of drain efficiency at 42 dBm output power, in the range of 1.7 to 2.75 GHz. Concretely, the results presented in this novel Doherty-like PA implies an specific load modulation technique that uses the mixed Klopfenstein tapered line together with a multi-section transformer in order to obtain high bandwidth with the usual efficiency in DPAs.<br>Los amplificadores de potencia (PAs) son uno de los elementos más importantes para los transmisores inalámbricos desde el punto de vista del consumo energético. Un aspecto muy importante es su eficiencia energética, un concepto relacionado con el back-off de salida (OBO), que a su vez viene condicionadpo por el PAPR de la señal modulada a amplificar. Una baja eficiencia de los PA hace que la pérdida de energía se manifieste en forma de calor. De hecho, esta cuestión conduce al incremento de los costes y tamaño, esto último por los radiadores. Además, el compromiso entre la linealidad y la eficiencia en los PA es otro problema importante. Para hacer frente a las circunstancias que producen la degradación de la eficiencia, el amplificador de potencia tipo Doherty (DPA) es una de las técnicas más útiles que proporcionan una buena eficiencia incluso para los altos PAPR comunes en señales de comunicación modernos. Sin embargo, el limitado ancho de banda (BW) de este tipo de PA (alrededor del 10% del ancho de banda fraccional) y su importancia (en los sistemas inalámbricos modernos, tales como LTE, WiMAX, Wi-Fi y sistemas de satélites) han animado a los investigadores para mejorar este inconveniente en los últimos años. Algunos aspectos típicos que limitan el BW en los DPA son: i) transformadores de longitud de cuarto de onda, ii) redes de compensación de fase y circuitos de adaptación de salida, iii) compensación de las líneas y los dispositivos no ideales. Los transformadores de cuarto de onda actuan como un inversor de impedancia en la técnica de modulación de carga de la DPA "("load modulation"). Concretamente, el objetivo futuro de diseño de DPA es disminuir el impacto de estos problemas. En este contexto, esta tesis doctoral se centra en mejorar el ancho de banda fraccional de DPA utilizando los nuevos métodos que están relacionados con el uso de transformadores de impedancias en vez de inversores en el subcircuito de modulación de carga. Este estudio tiene dos niveles. En primer lugar, se presenta una novedosa estructura del DPA de banda ancha usándose dispositivos de GaN en la banda de 2,5 GHz con un divisor Wilkinson asimétrico. El transformador de impedancias de la arquitectura propuesta se basa en una red de adaptación, incluyendo una línea cónica con múltiples secciones del transformador en la etapa principal. El BW de este DPA ha sido de 1,8 a 2,7 GHz. Además, se obtiene una eficiencia de drenador de más del 33% en todo el BW, tanto a nivel de potencia máxima como a nivel del OBO. En segundo lugar, aprovechando los beneficios de un adaptador de Klopfenstein, se propone un nuevo diseño del DPA. Con la sustitución de la lina conica por el Klopfenstein se reduce el coeficiente de reflexión de transformador de impedancias. Sobre un prototipo práctico de esta nueva estructura del Doherty, en la banda de 2,25 GHz, se ha demostrado que el BW resultante se incrementa en comparación con la topología convencional mientras se mantienen las cifras de eficiencia. Por otra parte, en este estudio se demuestra que el diseño basado en el Klopfenstein permite una afinación fácil del retardo de grupo a través de la reactancia de salida del taper, lo que resulta en un ajuste más sencillo que otros diseños publicados recientemente en el que el transformador de cuarto de onda se sustituye por multi-líneas de transmisión de la sección (híbridos o similar). Los resultados experimentales han mostrado un 43-54% de eficiencia de drenador sobre 42 dBm de potencia de salida, en el intervalo de 1,7 a 2,75 GHz. Concretamente, los resultados presentados en esta nueva estructura tipo-Doherty implican una técnica de modulación de carga que utiliza una combinación de un Klopfenstein junto con un transformador de múltiples secciones con el fin de obtener un alto ancho de banda con la eficiencia habitual en DPAs.<br>Els amplificadors de potència (PA) són un dels elements més importants per els sistemes ràdio ja que sone ls principals consumidors d'energía. Un aspecte molt important és l'eficiència de l'amplificador, aspecte relacionat amb el back-off de sortida (OBO) que a la seva vegada ve condicionat pel PAPR del senyal modulat. Una baixa eficiència dels PA fa que la pèrdua d'energia en manifesti en forma de calor. De fet, aquesta qüestió porta a l'increment dels costos i grandària, degut als dissipadors de calor. A més, el compromís entre la linealitat i l'eficiència en els PA es un altre problema important. Per fer front a les circumstàncies que porten a la degradació de l'eficiència, l'amplificador de potència Doherty (DPA) és una de les tècniques més útils i que proporcionen una bona eficiència per als alts PAPR comuns en senyals de comunicació moderns. No obstant això, l'ample de banda limitat (BW) d'aquest tipus de PA (al voltant del 10% de l'ample de banda fraccional) i la seva importància (en els sistemes moderns, com ara LTE, WiMAX, Wi-Fi i sistemes de satèl·lits) han animat els investigadors per millorar aquest inconvenient en els últims anys. Alguns aspectes tipicament limitadors del BW en els DPA son: i) transformadors de longitud d'quart d'ona, ii) xarxes de compensació de fase en circuits / adaptacions de sortida, iii) compensació de les línies i els dispositius no ideals. Els transformadors de quart d'ona s'utilitzen com a inversors d'impedàncies en la tècnica de modulació de càrrega del DPA ("load modulation"). Concretament, l'objectiu futur de disseny d'DPA és disminuir l'impacte d'aquests problemes. En aquest context, aquesta tesi doctoral es centra en millorar l'ample de banda fraccional dels DPA utilitzant nous mètodes que estan relacionats amb l'ús de transformadors d'impedàncies, en comptes d'inversors, en el subcircuit de modulació de càrrega. Aquest treball té dos nivells. En primer lloc, es presenta un DPA novedós que fa servir dispositus GaN DPA a la banda de 2,5 GHz amb un divisor Wilkinson asimètric. El transformador d'impedàncies de l'arquitectura proposada es basa en una xarxa d'adaptació, incloent una línia cònica amb múltiples seccions del transformador en l'etapa principal. El BW d'aquest DPA ha mostrat ser d'1,8 a a 2,7 GHz. A més, s'obté una eficiència de drenador de més del 33% en tot el BW, tant a nivell de potència màxima com de OBO. En segon lloc, sobre la base dels beneficis del adaptador de Klopfenstein, un proposa un nou disseny on un Klopfenstein substitueix la anterior línia cònica. Aquesta substitució repercuteix en la reducció del coeficient de reflexió de transformador d'impedàncies.Des d'una realització pràctica (prototipus) d'aquest nou amplificador tipus Doherty a la banda de 2,25 GHz, s'ha demostrat que el BW resultant s'incrementa en comparació amb la topologia convencional mentre es mantenen les xifres d'eficiència. D'altra banda, en aquest estudi es demostra que el disseny basat en el Klopfenstein permet una afinació fàcil del retard de grup a través de la reactància de sortida de la forma cònica, el que resulta en un ajust més senzill que altres dissenys publicats recentment en què el transformador de quart d'ona es substitueix per multi-línies de transmissió de la secció (híbrids o similar). Els resultats experimentals han mostrat un 43-54% d'eficiència de drenador en 42 dBm de potència de sortida, en l'interval de 1,7-2,75 GHz. Concretament, els resultats presentats en aquest nou amplificador tipus Doherty impliquen una tècnica de modulació de càrrega específic que utilitza una combinació del Klopfenstein juntament amb un transformador de múltiples seccions per tal d'obtenir un alt ample de banda amb la usual eficiència en DPAs.

Cette thèse démontre la faisabilité de l'utilisation de la technologie Nitrure de Gallium (GaN) dans les systèmes RF / micro-ondes reconfigurables. Les principales caractéristiques de ce type de technologie des semi-conducteurs se résident dans ses capacités de supporter des puissances élevées avec un rendement aussi élevé. En outre, la technologie GaN est un candidat très prometteur pour la réalisation des applications haute puissance/haute fréquence. Le travail de cette thèse est divisé en deux parties principales. La première est consacrée au développement, à l’analyse et à la caractérisation en DC et en RF jusqu'à 20 GHz des circuits actifs réalisés à base de la technologie GaN, tels que les diodes varicap et les commutateurs. Les diodes varicap fabriquées ont été modélisées en petit et grand signal par des équations analytiques contenant des coefficients empiriques ainsi un modèle en circuit a été développé, tandis aux commutateurs, un modèle de circuit en petit signal a été proposé. Ces composants actifs ont été réalisés en utilisant les processus GaN HEMTs de fabrication offerts par le Conseil National de Recherches du Canada (CNRC). La deuxième partie aborde les aspects de l'intégration de ces dispositif actifs GaN et de la conception des circuits reconfigurables proposés, tels que déphaseur reconfigurable, -3dB 90° coupleur hybride reconfigurable, oscillateur accordable en fréquence, commutation de faisceau et accordabilité en fréquence d’un réseau d'antennes patch tout en utilisant ces diodes varicap et commutateur GaN développées au fil de cette thèse. A travers cette thèse, l'utilisation de la technologie GaN pour la conception des designs RF reconfigurables en fréquence pour les applications fonctionnant au-dessous de 10 GHz a été démontrée<br>This thesis demonstrates the feasibility of using the Gallium Nitride (GaN) technology in reconfigurable RF/microwave systems. The main features of this type of semiconductor technology being its high power with high efficiency. In addition, GaN technology is a very promising candidate for realizing high power/high frequency applications. The thesis work is divided in two main parts. The first one is devoted to active GaN devices, such as varactor diodes and switches, development, analyze and characterization via DC and RF up to 20 GHz. The fabricated varactor were modeled by analytic equations containing empirical coefficients and also a physic circuit model was developed, while for the switches only a small signal physic circuit model was proposed. These GaN devices was manufactured by using the Canadian National Research Council (NRC) GaN HEMTs processes. The second part addresses the integration and design aspects of the reconfigurable proposed circuits, such as tunable phase shifter, reconfigurable 3-dB 90° hybrid coupler, tunable frequency oscillator, beam switching antenna array and matching reconfigurable patch antenna based on these developed GaN varactors and switches devices. The use of GaN on highly efficient reconfigurable designs for broadband RF/microwave applications operating below 10 GHz was demonstrated

The incorporation of Gallium Nitride (GaN) Power Amplifiers (PAs) into future high power aperture radar systems is certain; however, the introduction of this technology into multifunction radar systems will present new challenges to radar engineers. This dissertation describes a broad investigation into amplitude and phase transients produced by GaN PAs when they are excited with multifunction radar waveforms. These transients are the result of self-heating electrothermal memory effects and are manifested as interpulse instabilities that can negatively impact the coherent processing of multiple pulses. A behavioral model based on a Foster network topology has been developed to replicate the measured amplitude and phase transients accurately. This model has been used to develop a digital predistortion technique that successfully mitigates the impact of the transients. The Moving Target Indicator (MTI) Improvement Factor and the Root Mean Square (RMS) Pulse-to-Pulse Stability are used as metrics to assess the impact of the transients on radar system performance and to test the effectiveness of a novel digital predistortion concept.<br>Ph. D.

yes<br>This work integrates a harmonic tuning mechanism in synergy with the GaN HEMT transistor for 5G mobile transceiver applications. Following a theoretical study on the operational behavior of the Class-F power amplifier (PA), a complete amplifier design procedure is described that includes the proposed Harmonic Control Circuits for the second and third harmonics and optimum loading conditions for phase shifting of the drain current and voltage waveforms. The performance improvement provided by the Class-F configuration is validated by comparing the experimental and simulated results. The designed 10W Class-F PA prototype provides a measured peak drain efficiency of 64.7% at 1dB compression point of the PA at 3.6GHz frequency.

Les systèmes radar nécessitent d’être de plus en plus performants et doivent émettre des impulsions les plus identiques possibles. Un critère permet de quantifier la bonne régularité des impulsions radar au cours du temps : la stabilité pulse à pulse. L’amplificateur de puissance est un élément essentiel du système radar. Dans ce sens, ce travail présente une analyse du critère de stabilité pulse à pulse dans le cas d’un amplificateur HEMT GaN. Les formules mathématiques permettant d’extraire la valeur de la stabilité pulse à pulse des mesures temporelles d’enveloppe sont présentées. La conception et la réalisation d’un amplificateur de puissance RF connectorisé 50 Ω sont décrites. Divers cas de rafales radar ont été étudiés au travers des mesures temporelles d’enveloppe pour en quantifier l’impact sur les valeurs de stabilité pulse à pulse. Un banc de mesure hétérodyne de la stabilité pulse à pulse a été spécialement développé pendant ces travaux de thèse. Finalement, ces résultats de stabilité pulse à pulse ont été utilisés pour optimiser le modèle électrique non linéaire du transistor HEMT GaN afin de prendre en compte lors des simulations temporelles d’enveloppe les effets de la thermique et des pièges<br>Radar-oriented applications require stringent performances. Among them, emitting pulse train with uniform envelope characteristics in term of amplitude and phase. The criterion to quantify the self-consistency of radar signals over the pulse train is the pulse to pulse stability. The power amplifier is the most critical element in the RF radar chain because it has a strong impact on the overall pulse to pulse stability performances. In this context, this work is focused on the study of the impact of a HEMT GaN power amplifier on the pulse to pulse stability. Mathematical approach is presented to derive the pulse to pulse stability from time domain envelope measurements. Design and implementation of a 50Ω matched RF power amplifier are presented. Different radar bursts scenario are investigated and their impact on the pulse to pulse stability are quantified through extensive time domain envelope measurements. For that purpose, a dedicated experimental heterodyne time domain envelope test bench has been developed. These pulse to pulse stability measurements are finally used to optimize and fully validate a nonlinear electrical model of a HEMT GaN, allowing to quantify the relative impact of thermal and trapping effects during circuit envelope simulation in radar-oriented applications

In this thesis, novel designs for adaptive power amplifiers, capable of maintaining excellent performance at dissimilar signal parameters, are presented. These designs result in electronically reconfigurable, single-ended and Doherty power amplifiers (DPA) that efficiently sustain functionality at different driving signal levels, highly varying time domain characteristics and wide-spread frequency bands. The foregoing three contexts represent those dictated by the diverse standards of modern communication systems. Firstly, two prototypes for a harmonically-tuned reconfigurable matching network using discrete radio frequency (RF) microelectromechanical systems (MEMS) switches and semiconductor varactors will be introduced. Following that is an explanation of how the varactor-based matching network was used to develop a high performance reconfigurable Class F-1 power amplifier. Afterwards, a systematic design procedure for realizing an electronically reconfigurable DPA capable of operating at arbitrary centre frequencies, average power levels and back-off efficiency enhancement power ranges is presented. Complete sets of closed-form equations are outlined which were used to build tunable matching networks that compensate for the deviation of the Doherty distributed elements under the desired deployment scenarios. Off-the-shelf RF MEMS switches are used to realize the reconfigurability of the adaptive Doherty amplifiers. Finally, based on the derived closed-form equations, a tri-band, monolithically integrated DPA was realized using the Canadian Photonics Fabrication Centre (CPFC??) GaN500 monolithic microwave integrated circuit (MMIC) process. Successful integration of high power, high performance RF MEMS switches within the MMIC process paved the way for the realization of the frequency-agile, integrated version of the adaptive Doherty amplifier.

碩士<br>國立交通大學<br>電信工程系所<br>92<br>This thesis is divided into two parts. The first part describes the analysis and design of a Ka-Band power amplifier applied to the automotive collision avoidance radar system. In order to acquire the adequate linearity and efficiency of the system requirements, the architecture with two stages is adopted to design the power amplifier. The first stage utilizes class-A type to supply sufficient power gain. The second stage improves RF-to-DC signal ratio by class-AB type. By this way, the linearity of this circuit can also be improved. The semiconductor material of PHEMT is adequate to design the RF circuits with the characteristics of high power level and high operating frequency because it possesses the higher breakdown voltage and the lower doping channel. So as to operate the circuits at Ka-band, we select the semiconductor process of WIN 0.15-um GaAs PHEMT to design the circuits. At the central frequency of 32.4GHz, the measured results reveal that the fabricated power amplifier has the P-1dB of 2dBm、Pout of 12.4dBm, and PAE of 19.7% at P-1dB point. The second section of this thesis proposes and demonstrates a novel architecture of 2.4GHz bi-directional amplifier. The approach improves effectively the isolation and noise figure of the circuit to ameliorate the quality of output signal. The framework includes two reflection-type amplifiers and a 90 degree branch-line circuit. The designed process must pay attention to the oscillation condition because its principles are similar to that of an oscillator. Meanwhile, the ability of bi-direction could be realized in accordance with the characteristic of branch-line circuit. The bi-directional amplifier with this architecture can obtain the gain which is same as that of a reflection-type amplifier. Also, a variable capacitance is arranged to steady the condition of oscillation and adjust the gain according to the circuit’s requires. And the conventional branch-line circuit must be realized by means of transmission lines with the quarter wavelength. This length is 16.7mm at the operating frequency of 2.4GHz. This approach is inappropriate for CMOS IC. Therefore, this 90 degree branch-line circuit is realized on a FR4 board and utilizes a new method to reduce the area. So, this IC only embraces these two critical reflection-type amplifiers. And the expected specifications of this reflection-type amplifier are as follows: power gain 13.6dBm, P1dB -5dBm，the noise figure 14.3dB. Furthermore, the return loss S11 of this bi-directional amplifier is below -10dB across overall utilized bandwidth. The gain can alter from 7.5dB to 16dB and the noise figure varies from 4.1 to 5.4.

碩士<br>元智大學<br>電機工程學系乙組<br>107<br>This research presented an X-band GaN high microwave power amplifiers (PAs), including 10 GHz PA and 12 GHz PA by using WIN 0.25 um GaN process. GaN technology provides more output power and high efficiency than silicon process, but this technology is expensive; designer must overcome the problem of heat dissipation under high power situation. In design, there are more considerations in high frequency and high power. The circuit design is limited by the circuit model in source grounding configuration, so this research has adopted a two-stage CS amplifier method. The first stage plays the role as the gain enhancement function. The second stage provides higher output power capability. Input, inter-stage, and output matching circuits are implemented by transmission lines and capacitors, because the transmission line can withstand high DC currents and high RF signal powers. Besides, the size of the required transmission line can be reduced in high frequency operations. Therefore, it is desirable to complete a high frequency, high output power PA by this method.

abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.<br>Dissertation/Thesis<br>Doctoral Dissertation Electrical Engineering 2018

abstract: This work implements three switched mode power amplifier topologies namely inverse class-D (CMCD), push-pull class-E and inverse push-pull class-E, in a GaN-on-Si process for medium power level (5-10W) femto/pico-cells base-station applications. The presented power amplifiers address practical implementation design constraints and explore the fundamental performance limitations of switched-mode power amplifiers for cellular band. The designs are analyzed and compared with respect to non-idealities like finite on-resistance, finite-Q of inductors, bond-wire effects, input signal duty cycle, and supply and component variations. These architectures are designed for non-constant envelope inputs in the form of digitally modulated signals such as RFPWM, which undergo duty cycle variation. After comparing the three topologies, this work concludes that the inverse push-pull class-E power amplifier shows lower efficiency degradation at reduced duty cycles. For GaN based discrete power amplifiers which have less drain capacitance compared to GaAs or CMOS and where the switch loss is dominated by wire-bonds, an inverse push-pull class-E gives highest output power at highest efficiency. Push-pull class-E can give efficiencies comparable to inverse push-pull class-E in presence of bondwires on tuning the Zero-Voltage Switching (ZVS) network components but at a lower output power. Current-Mode Class-D (CMCD) is affected most by the presence of bondwires and gives least output power and efficiency compared to other two topologies. For systems dominated by drain capacitance loss or which has no bondwires, the CMCD and push-pull class-E gives better output power than inverse push-pull class-E. However, CMCD is more suitable for high breakdown voltage process.<br>Dissertation/Thesis<br>Masters Thesis Electrical Engineering 2015

碩士<br>國立中央大學<br>電機工程學系<br>106<br>The thesis developed five power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WINTM 0.25-µm GaN for both X-band and Ka-band operations. The best transistor size and biasing current density of the used transistors were chosen by simulating in different processes. The wideband matching was realized by the magnetically coupling transformer and the enhanced efficiency was realized by using Doherty architecture. Finally, the circuit performance was verified by the measuring small and large signal parameters, such as S-parameters, output power, linearity and modulated signals, etc., The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for X-band operation. This two-stage power amplifier adopted the unilateralization technique which was constructed by a class A amplifier in parallel with class B one to increase the overall output 1-dB compression power (OP1dB) and power added efficiency (PAE). The wide operating bandwidth was achieved by using magnetically coupling Balun for the output matching and T-type matching for the inter-stage matching. The measurement results showed a small signal gain of 20.1 dB, the saturated output power (Psat) and OP1dB are 20.1 dBm and 18.4 dBm, respectively. The peak output power and PAE are improved by the amount of 3.8 dB and 3.4%, respectively, while adopted this composited power amplifier architecture. The chip area is 1.78 (1.95×1.13) mm2. The second and third chips were fabricated in tsmcTM 90-nm CMOS technology for Ka-band operation. Two amplifiers were realized by using unilateralization technique in common-source topology. The input and output matching design followed the previous work and the inter-stage matching was realizes by magnetic transformer. The third power amplifier applied a pre-matching design to minimize the chip size and increase the operating bandwidth. These power amplifiers displayed the gains of 17.43 dB and 14.5dB, respectively. The saturated output powers were measured to 14.73 dBm and 18.4 dBm. The OP1dB were 10.7dBm and 14.5 dBm, respectively. The chip areas are 0.73 (1.41×0.405) mm2 and 0.67 (1.01×0.67) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The last power amplifier also was fabricated in WINTM 0.25-µm GaN technology. A Doherty power amplifier (DPA) adopted a T-type network for the output matching to reduce the chip size and a Lange-coupler for the input matching. The DPA achieved a peak gain of 11.8 dB, a saturation output power of 35.9 dBm, a PAE at 6-dB power back-off of 39.9% and a peak PAE 41.5%. The chip area is 3.03 (1.73×1.75) mm2.

碩士<br>國立交通大學<br>電信工程研究所<br>107<br>This thesis consists of two parts, the first part is GaN Power Amplifiers on Si-Substrate Using Load-Pull Design, and the second part is Flip-Chip SiGe HBT Power Amplifiers Using the GIPD Parallel- Series-Combining Transformer. In the first part, we use load-pull method design two stage GaN power amplifier on Si-Substrate. And we also use mismatch power penalty to check whether the first stage would pull all of the power of the second stage. We implemented some power amplifiers with critical bands under 6 GHz. In the second part, we use flip-chip technique instead of bondwires to design SiGe HBT power amplifiers with GIPD parallel-series- combining transformer in order to reduce uncertainty. We use bondwires and flip-chip to implement two kinds of SiGe HBT power amplifier using the GIPD parallel-series- combining transformer.

Emerging wireless standards are designed to be spectrally efficient to address the high cost of licensing wireless spectra. Unfortunately, the resulting signals have a high peak-to-average ratio that reduces the base station power amplifier efficiency at the back-off power level. The wasted energy is converted to heat that degrades the device reliability and increases the base-station’s carbon footprint and cooling requirements. In addition, these new standards place stringent re- quirements on the amplifier output power, linearity, efficiency, and bandwidth. To improve the back-off efficiency, a Doherty amplifier, which uses two device in parallel for back-off efficiency enhancement, is deployed in a typical base station. Unfortunately, the conventional Doherty amplifier is narrowband and thus cannot satisfy the bandwidth requirement of the modern base station that needs to support multiple standards and backward compatibility. In this thesis, we begin by studying the class F/F−1 high efficiency mode of operation. To this end, we designed a narrowband, harmonically-tuned 3.3 GHz, 10 W GaN high efficiency amplifier. Next, we investigate how to simultaneously achieve high efficiency and broad bandwidth by harnessing the simplified real frequency technique for the broadband matching network design. A 2 to 3 GHz, 45 W GaN amplifier and a 650 to 1050 MHz, 45 W LDMOS amplifier were designed. Finally, we analyze the conventional Doherty amplifier to determine the cause of its narrow bandwidth. We find that the narrow bandwidth can be attributed to the band-limited quarter-wave transformer as well as the widely adopted traditional design technique. As an original contribution to knowledge, we propose a novel Doherty amplifier configuration with intrinsically broadband characteristics by analyzing the load modulation concept and the conventional Doherty amplifier. The proposed amplifier uses asymmetrical drain voltage biases and symmetrical devices and it does not require a complex mixed-signal setup. To demonstrate the proposed concept in practice, we designed a 700 to 1000 MHz, 90 W GaN broadband Doherty amplifier. Moreover, to show that the proposed concept is applicable to high power designs, we designed a 200 W GaN broadband Doherty amplifier in the same band. In addition, to show that the technique is independent of the device technology, we designed a 700 to 900 MHz, 60 W LDMOS broadband Doherty amplifier. Using digital pre-distortion, the three prototypes were shown to be highly linearizable when driven with wideband 20 MHz LTE and WCDMA modulated signals and achieved excellent back-off efficiency. Lastly, using the insights from the previous analyses, we propose a novel mixed-technology Doherty amplifier with an extended and reconfigurable back-off level as well as an improved power utilization factor. The reconfigurability of the proposed amplifier makes it possible to customize the back-off level to achieve the highest average efficiency for a given modulated signal without redesigning the matching networks. A 790 to 960 MHz, 180 W LDMOS/GaN Doherty amplifier demonstrated the extended bandwidth and reconfigurability of the back-off level. The proposed amplifier addresses the shortcomings of the conventional Doherty amplifier and satisfies the many requirements of a modern base station power amplifier.

碩士<br>國立中央大學<br>電機工程學系<br>105<br>The thesis developed three power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WIN 0.25-µm GaN for both C/X-band and Ku-band operations. Firstly, the transistor characteristics of different processes were simulated to choose best transistor size and current density. The broadband matching performance was realized by using transformer and Guanella-type transmission-line transformers. Finally, the design concepts were verified by measuring various circuit performances, such as s parameters, output power, linearity and digital modulation characteristics. The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for C/X-band operation. The two-stage power amplifier adopted cascade topology. The broadband performance was achieved by using transmission-line transformer for output matching and magnetic transformer for both input and inter-stage matching networks. The measurement results of the first PA shows a small signal gain of 25.23 dB, the saturated output power (Psat) and the maximum power added efficiency (PAEMAX) are 24.34 dBm and 28.2%, respectively. The performances of the output 1-dB gain compression point (OP1dB) of 20.64 dBm. The chip area is 1.78(1.968×0.904) mm2. The second circuit was fabricated in tsmcTM 90-nm CMOS technology for C/X-band operation. The circuit design flow follows the previous PA design which uses both transmission-line transformer and magnetic transformers to achieve broadband and low lossmatching. The wideband PA exhibits a peak gain of 29.1 dB, and 3-dB bandwidths from 5.1-11.2 GHz. The measured saturation output power, OP1dB, and maximum PAE are 22.02 dBm, 19.64 dBm, and 23.92%, respectively. The chip size is 1.32 (1.522×0.866) mm2. The third chip presents a Ku-band monolithic microwave integrated circuit (MMIC) power amplifier in WIN 0.25-µm GaN technology. The broadband performance was achieved by using transmission-line transformer for both input and output matching networks. The amplifier achieves a 3-dB bandwidth from 13 to 18.2 GHz with small signal gain of 14.71 dB. Continuous wave measurements demonstrate a maximum saturated output power of 32.26 dBm and OP1dB of 27.6 dBm, respectively. The chip size is 3.13 (2.16 × 1.448) mm2.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as the most compelling technology for the transmission of highpower radio-frequency (RF) signals for cellular mobile communications and radar applications. However, despite their remarkable power capabilities, the deployment of GaN HEMT-based RF power amplifiers (PAs) in the mobile communications infrastructure is often ruled out in favor of alternative siliconbased technologies. One of the main reasons for this is the pervasiveness of nonlinear long-term memory effects in GaN HEMT technology caused by thermal and charge-trapping phenomena. While these effects can be compensated for using sophisticated digital predistortion algorithms, their implementation and model-extraction complexity—as well as the power necessary for their real-time execution—make them unsuitable for modern small cells and large-scale multiple-input multiple-output transceivers, where the power necessary for the linearization of each amplification element is of great concern. In order to address these issues and further the deployment of high-powerdensity high-efficiency GaN HEMT-based RF PAs in next-generation communications and radar applications, in this thesis we propose novel methods for the characterization, modeling, and compensation of long-term memory effects in GaN HEMT-based RF PAs. More specifically, we propose a method for the characterization of the dynamic self-biasing behavior of GaN HEMTbased RF PAs; multiple behavioral models of charge trapping and their implementation as analog electronic circuits for the accurate real-time prediction of the dynamic variation of the threshold voltage of GaN HEMTs; a method for the compensation of the pulse-to-pulse instability of GaN HEMT-based RF PAs for radar applications; and a hybrid analog/digital scheme for the linearization of GaN HEMT-based RF PAs for next-generation communications applications.<br>Os transístores de alta mobilidade eletrónica de nitreto de gálio (GaN HEMTs) são considerados a tecnologia mais atrativa para a transmissão de sinais de radiofrequência de alta potência para comunicações móveis celulares e aplicações de radar. No entanto, apesar das suas notáveis capacidades de transmissão de potência, a utilização de amplificadores de potência (PAs) baseados em GaN HEMTs é frequentemente desconsiderada em favor de tecnologias alternativas baseadas em transístores de silício. Uma das principais razões disto acontecer é a existência pervasiva na tecnologia GaN HEMT de efeitos de memória lenta causados por fenómenos térmicos e de captura eletrónica. Apesar destes efeitos poderem ser compensados através de algoritmos sofisticados de predistorção digital, estes algoritmos não são adequados para transmissores modernos de células pequenas e interfaces massivas de múltipla entrada e múltipla saída devido à sua complexidade de implementação e extração de modelo, assim como a elevada potência necessária para a sua execução em tempo real. De forma a promover a utilização de PAs de alta densidade de potência e elevada eficiência baseados em GaN HEMTs em aplicações de comunicação e radar de nova geração, nesta tese propomos novos métodos de caracterização, modelação, e compensação de efeitos de memória lenta em PAs baseados em GaN HEMTs. Mais especificamente, nesta tese propomos um método de caracterização do comportamento dinâmico de autopolarização de PAs baseados em GaN HEMTs; vários modelos comportamentais de fenómenos de captura eletrónica e a sua implementação como circuitos eletrónicos analógicos para a previsão em tempo real da variação dinâmica da tensão de limiar de condução de GaN HEMTs; um método de compensação da instabilidade entre pulsos de PAs baseados em GaN HEMTs para aplicações de radar; e um esquema híbrido analógico/digital de linearização de PAs baseados em GaN HEMTs para comunicações de nova geração.<br>Programa Doutoral em Telecomunicações

碩士<br>國立中央大學<br>電機工程學系<br>107<br>This thesis consists of five chapters. The thesis developed a Ku-band wideband power amplifier and a K-band on-off keying (OOK) transmitter for wireless sensor network (WSN) applications in tsmcTM 0.18-µm CMOS process and 90-nm CMOS process, respectively. The author also developed two watt-level power amplifiers for X-band military marine radar in WINTM 0.25-µm GaN process. Chapter 2 presents a Ku-band neutralized Darlington cascode power amplifier by using transformer-coupled matching in 0.18-µm CMOS. To solve the bottleneck of the 0.18-μm CMOS process in millimeter wave, such as lossy substrate, poor capability of transconductance (gm) and low breakdown voltage. Darlington pair with cascode topology was adopted as power cell to enhance the current cut-off frequency (fT), maximum oscillation frequency (fmax) and maximum available gain (MAG) of the transistors for being capable of operating at Ku-band to Ka-band. This design also used the cross-coupled capacitors to improve gain and bandwidth. The measurement results showed that the amplifier achieved a peak gain of 14 dB, a saturated output power (P_sat) and output power of 1-dB gain compression point (OP_1dB) of 22.2 dBm and 18.8 dBm, respectively. The peak power added efficiency (PAE_max) is 15.8%. The 3-dB bandwidth is from 11.3 to 17.3 GHz. The chip area is 0.7 (1.46×0.48) mm2. Chapter 3 proposes a high energy-efficiency K-band OOK transmitter in 90-nm CMOS process. This chapter improves the drawback that conventional transmitter cannot apply the proper modulation signal at buffer stage. The modified transmitter consists of a wideband voltage control oscillator (VCO), a high isolation and high data rate switch-type modulator and a medium power amplifier. The measurement results showed that the OOK transmitter achieves a frequency tuning range from 22.7 to 25.4 GHz, a minimum phase noise of -101.6 dBc/Hz at 1-MHz offset and a maximum output power of 5.3 dBm. The total power consumption is 23 mW. When the data rate is 2.4 Gbps, the energy efficiency is 9.6 pJ/bit. The chip area is 0.36 (0.9×0.4) mm2. Chapter 4 proposes two types of watt-level power amplifier that applied to X-band military marine radar. The chapter 4-3 presents a power amplifier using two-stage configuration to achieve a linear gain of above 20 dB. In order to achieve 10 W output power and having excellent power per area ratio (PPAR), an ultra-compact layout of four-way power combining structure has been developed. The measurement results showed that the power amplifier achieves a peak power gain of 20.6 dB, a saturated output power (P_sat) and output power of 1-dB gain compression point (OP_1dB) of 41.73 dBm (14.9 W) and 30.9 dBm, respectively. The peak power added efficiency (PAE_max) is 37%. The PPAR and power density are 4.29 W/mm2 and 4.66 W/mm, respectively. The chip area is 3.49 (2.1×1.66) mm2. The chapter 4-4 presents a high efficient power amplifier using two-stage configuration to achieve a linear gain of 20 dB. A compact harmonic tuning network was adopted to improve the linearity and efficiency. Also satisfy the stringent adjacent channel leakage ratio (ACLR) requirements. The designed power amplifier achieves a peak power gain of 19.8 dB, a saturated output power (P_sat) and output power of 1-dB gain compression point (OP_1dB) of 38.4 dBm (7 W) and 36.9 dBm, respectively. The peak power added efficiency (PAE_max) is 45.4%. The PPAR and power density are 2.77 W/mm2 and 4.36 W/mm, respectively. The chip area is 2.52 (2.63×0.96) mm2.

abstract: The drive towards device scaling and large output power in millimeter and sub-millimeter wave power amplifiers results in a highly non-linear, out-of-equilibrium charge transport regime. Particle-based Full Band Monte Carlo device simulators allow an accurate description of this carrier dynamics at the nanoscale. This work initially compares GaN high electron mobility transistors (HEMTs) based on the established Ga-face technology and the emerging N-face technology, through a modeling approach that allows a fair comparison, indicating that the N-face devices exhibit improved performance with respect to Ga-face ones due to the natural back-barrier confinement that mitigates short-channel-effects. An investigation is then carried out on the minimum aspect ratio (i.e. gate length to gate-to-channel-distance ratio) that limits short channel effects in ultra-scaled GaN and InP HEMTs, indicating that this value in GaN devices is 15 while in InP devices is 7.5. This difference is believed to be related to the different dielectric properties of the two materials, and the corresponding different electric field distributions. The dielectric effects of the passivation layer in millimeter-wave, high-power GaN HEMTs are also investigated, finding that the effective gate length is increased by fringing capacitances, enhanced by the dielectrics in regions adjacent to the gate for layers thicker than 5 nm, strongly affecting the frequency performance of deep sub-micron devices. Lastly, efficient Full Band Monte Carlo particle-based device simulations of the large-signal performance of mm-wave transistor power amplifiers with high-Q matching networks are reported for the first time. In particular, a CellularMonte Carlo (CMC) code is self-consistently coupled with a Harmonic Balance (HB) frequency domain circuit solver. Due to the iterative nature of the HB algorithm, this simulation approach is possible only due to the computational efficiency of the CMC, which uses pre-computed scattering tables. On the other hand, HB allows the direct simulation of the steady-state behavior of circuits with long transient time. This work provides an accurate and efficient tool for the device early-stage design, which allows a computerbased performance evaluation in lieu of the extremely time-consuming and expensive iterations of prototyping and experimental large-signal characterization.<br>Dissertation/Thesis<br>Ph.D. Electrical Engineering 2011

碩士<br>國立交通大學<br>電信工程研究所<br>104<br>This thesis consists of two parts, including power amplifiers with Parallel, Series, Parallel-Series power combining transformers and a 5-GHz GaN low noise amplifier. In the first part, fully-Integrated high linearity power amplifiers implemented with TSMC 0.18-m SiGe BiCMOS technology are presented. The improvement of output power and linearity is achieved using parallel, series, parallel-series power combining transformers to combine the power of multiple power cells. Furthermore, a 5-GHz high/low mode power amplifier with parallel power combining transformer not only improves output power and linearity but also enhances efficiency. The second part introduces GaN technology and a 5-GHz GaN low noise amplifier with GaN technology is demonstrated with low noise figure.

The conventional Doherty architecture is commonly used in wireless transmitters for its ability to boost the average efficiency of a traditional single-ended class B amplifier. It consists of two parallel single-ended amplifying branches (named carrier and peaking amplifiers) which are linked, at the output, through a /4 combiner. This output combiner commonly has a significant impact on the overall bandwidth, as it is usually built from a transmission line structure with tuned dimensions. Other non-conventional combining structures could be designed, targeting a wider bandwidth, contributing to an overall increase of the Doherty amplifier’s bandwidth. Being this an high relevance research topic for the development of high efficient and broadband amplifiers, it is highly desirable to have a laboratory setup that implements a Doherty power amplifier to which distinct output combiner structures can be connected and tested. In that sense, the design of two single-ended amplifiers (the carrier and the peaking) was performed in a circuit simulator (ADS, from Keysight) together with the input power divider that compose the Doherty architecture. The Doherty amplifier main board was designed to incorporate the carrier and peaking amplifiers, and also the power splitter at the input, and it was prepared so that it could be connected to any desired combiner to be tested. A traditional Doherty power combiner was designed and both boards (Doherty amplifier and the combiner) were produced, connected and tested in the RF laboratory. The measured amplifier presented the typical caractheristics of a Doherty amplifier with nearly 75% of drain efficiency at full-power, and nearly 50% at the output back-off level. In addition, a second combiner unit was designed with two purposes. The first was to demonstrate the operation of the designed Doherty amplifier with a distinct output combiner, showing that, as intended in this work, it is suited to test multiple combiner structures. The second objective was to serve as preliminary test to evaluate the possibility of merging the output combiner with the antenna element. Taking advantage of the electromagnetic coupling between antennas, this second combiner structure uses two antenna elements that were tuned to simultaneously behave as output combiner of the Doherty amplifier and a radiating element.<br>A arquitetura Doherty convencional é tipicamente utilizada em transmissores sem fios pela sua capacidade de aumentar a eficiência média de um tradicional amplificador em classe B. O amplificador Doherty consiste em dois amplificadores em paralelo (chamados de amplificadores carrier e peaking) que são ligados, na saída, através de um combinador de /4. Este combinador de saída geralmente tem um impacto significativo na largura de banda do amplificador, pois é tipicamente construído a partir de uma estrutura de linhas de transmissão com dimensões ajustadas para uma frequência. Outras estruturas de combinadores não convencionais podem ser projetadas, visando uma largura de banda maior, contribuindo para um aumento geral da largura de banda do amplificador Doherty. Sendo este um tópico de investigação de elevada relevância para o desenvolvimento de amplificadores de alta eficiência e largura de banda, seria interessante ter um setup de laboratório que implemente um amplificador de potência Doherty para o qual estruturas combinadoras distintas possam ser ligadas à saída do amplificador e testadas. Nesse sentido, o projeto de dois amplificadores (carrier e peaking) foi realizado num simulador de circuitos (ADS, da Keysight) junto com o divisor de potência de entrada que compõe a arquitetura Doherty. A placa principal do amplificador Doherty foi projetada para incorporar os amplificadores carrier e peaking, e também o divisor de potência na entrada, e foi preparada de modo que pudesse ser ligada a qualquer combinador desejado a ser testado. Um combinador de potência Doherty tradicional foi projetado e ambas as placas (amplificador Doherty e o combinador) foram produzidas, soldadas e testadas no laboratório de RF. O amplificador medido apresentou as características típicas de um amplificador Doherty com aproximadamente 75% de eficiência de dreno na potência máxima e aproximadamente 50% no ponto de output back-off. Além disso, foi projetado um segundo combinador com dois objetivos. O primeiro foi demonstrar o funcionamento do amplificador Doherty projetado com um combinador de saída distinto, mostrando que, como pretendido neste trabalho, o amplificador desenhado é adequado para testar múltiplas estruturas combinadoras. O segundo objetivo foi servir como teste preliminar para avaliar a possibilidade de fundir o combinador de saída com a antena. Aproveitando o acoplamento eletromagnético entre antenas, esta segunda estrutura combinadora utiliza duas antenas que foram projetadas para se comportarem simultaneamente como combinador de saída do amplificador Doherty e como elemento radiante.<br>Mestrado em Engenharia Eletrónica e Telecomunicações

碩士<br>國立中央大學<br>電機工程學系<br>105<br>In this paper, we present each block diagrams of front-end communication, including two versions of power amplifiers (PAs), a low noise amplifier (LNA) and a diode mixer in detail. To make our design goals achievable, we must consult load-pull, maximum available gain, and I-V curve and so on simulations carefully. There are mainly two parts of this paper, including receiver and transmitter of front-end communication system. First, we present LNA and the diode mixer is design, which are important block diagrams of receiver. These two circuits are designed in operating frequency between 25 GHz and 40 GHz with center frequency at 38 GHz. They are design in process of WIN ED-Mode 0.15 μm. The performance of LNA achieve up to 30-dB gain with about 140-mW DC power consumption. On the other hand, the diode mixer shows up to -6- dB conversion gain (or conversion loss) with 10 dBm local oscillator (LO) driving power. Note that there is no DC power consumption in the diode mixer because it is completely work as a passive mixer. Next, we set a goal to design a power amplifier with 1-W saturation output power. We design two amplifiers in WIN GaN process, including Ku- and Ka- band PA. The Ka-band power amplifier suffer from heat issue and fail to work. That is the reason why we design Ku-band version PA. The Ku-band successfully work as a 15-dB gain and nearly 29-dBm saturation output power from 10 GHz to 15 GHz. Finally, we try to design a W-band PA in 40 nm CMOS process. We set a goal to achieve the center operating frequency at 94 GHz. It is the parasitic issue that makes a W-band PA suffer from high loss in matching network and passive component in the circuit. As a result, we fail to make this PA work due to misestimation of in-band bypass capacitor EM simulation. In Chapter 4, we will present how to debug and make the PA work. Overall, we have consulted block diagrams in front-end communication system except for TX/RX switch and antenna design. Besides, a low noise down converter haven been taped out. It would be measured and make a front-end communication closer to be complete. In the future, the whole system should be integrated with antenna by TX/RX switch.