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Journal articles on the topic 'Gate-all-around FET'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Xie, Chengzhen, Yuxin Zhang, Kexin Zhang, and Leon Zi-Run Guo. "Introduction of Gate-All-Around FET (GAAFET)." Applied and Computational Engineering 28, no. 1 (2023): 164–75. http://dx.doi.org/10.54254/2755-2721/28/20230354.

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The Gate-All-Around Field-Effect Transistor (GAAFET) represents a significant advancement in integrated circuits technology, offering enhanced functionality compared to its predecessor, the Fin Field-Effect Transistor (FinFET). This paper provides a comprehensive overview of GAAEFT, its historical developments, current state, and recent developments. The introduction section mentioned the importance of changing from FinFET to GAAFET structures. The historical developments section traces the evolution of GAAFET technology, highlighting key milestones and breakthroughs. The current state section

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2

S., Ahmad Saidulu, Vineeth R.Sai, Y.Tanmayee, and B.Meenakshi. "Performance Measures of Different Gate Oxide Materials in Gate All Around Fet." International Journal of Recent Technology and Engineering (IJRTE) 9, no. 2 (2020): 23–25. https://doi.org/10.35940/ijrte.A2626.079220.

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The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipat

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3

Wu, Jiaxian, Huidi Qi, and Quancheng Zhao. "Self-Heating Effect of Gate-All-Around FETs: A Review." Applied and Computational Engineering 168, no. 1 (2025): None. https://doi.org/10.54254/2755-2721/2025.24442.

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As MOSFETs evolve into gate-all-around field effect transistor (GAAFET), the impact affecting the performance of MOSFET becomes more significant: the temperature rise caused by self-heating effect (SHE). This review paper presents the development process of field effect transistors (FET), from Planar FET to GAAFET, including their SHE. It introduces the formation mechanism of SHE, and compares the temperature distribution of different FETs under the influence of SHE and the performance of various FET structures in terms of heat conduction and dissipation. Three harmful factors for FET caused b

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4

Singh, Sarabdeep, Leo Raj Solay, Sunny Anand, Naveen Kumar, Ravi Ranjan, and Amandeep Singh. "Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier." Micromachines 14, no. 7 (2023): 1357. http://dx.doi.org/10.3390/mi14071357.

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This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA struc

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5

Madan, Jaya, and Rishu Chaujar. "Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET." IEEE Transactions on Nanotechnology 17, no. 1 (2018): 41–48. http://dx.doi.org/10.1109/tnano.2017.2650209.

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6

Wang, Miaomiao. "A Review of Reliability in Gate-All-Around Nanosheet Devices." Micromachines 15, no. 2 (2024): 269. http://dx.doi.org/10.3390/mi15020269.

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The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), a

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7

Guan, Yunhe, Zunchao Li, Wenhao Zhang, Yefei Zhang, and Feng Liang. "An Analytical Model of Gate-All-Around Heterojunction Tunneling FET." IEEE Transactions on Electron Devices 65, no. 2 (2018): 776–82. http://dx.doi.org/10.1109/ted.2017.2783911.

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8

Chen, Xiangchen, and Cher Ming Tan. "Modeling and analysis of gate-all-around silicon nanowire FET." Microelectronics Reliability 54, no. 6-7 (2014): 1103–8. http://dx.doi.org/10.1016/j.microrel.2013.12.009.

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9

Kim, Soohyun, Jungchun Kim, Doyoung Jang, et al. "Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET." Applied Sciences 10, no. 8 (2020): 2979. http://dx.doi.org/10.3390/app10082979.

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The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (VTH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μeff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak Ninv (= 5 × 1012 cm2/V∙s), both GAA NW-FET and FinF

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10

Jung, Hakkee. "Analytical subthreshold swing model of junctionless elliptic gate-all-around (GAA) FET." AIMS Electronics and Electrical Engineering 8, no. 2 (2024): 211–16. http://dx.doi.org/10.3934/electreng.2024009.

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<abstract> <p>An analytical subthreshold swing (SS) model has been presented to determine the SS of an elliptic junctionless gate-all-around field-effect transistor (GAA FET). The analysis of a GAA FET with an elliptic cross-section is essential because it is difficult to manufacture a GAA FET with an accurate circular cross-section during the process. The SS values obtained using the proposed SS model were compared with 2D simulation values and other papers to confirm good agreement. Using this analytical SS model, SS was analyzed according to the eccentricity of the elliptic cros

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11

Yujia Zhai, Leo Mathew, Rajesh Rao, et al. "High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High- $\kappa $ /Metal Gate." IEEE Transactions on Electron Devices 61, no. 11 (2014): 3896–900. http://dx.doi.org/10.1109/ted.2014.2353658.

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12

Espineira, G., D. Nagy, G. Indalecio, A. J. Garcia-Loureiro, K. Kalna, and N. Seoane. "Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET." IEEE Electron Device Letters 40, no. 4 (2019): 510–13. http://dx.doi.org/10.1109/led.2019.2900494.

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13

Chowdhury, Md. Iqbal Bahar. "Germanium-Silicon Based Hetero Junction Cylindrical Gate All Around Field Effect Transistor for Improved Performance." International Journal of Engineering Technology, Management and Applied Sciences 5, no. 9 (2017): 1–6. https://doi.org/10.5281/zenodo.15320002.

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Performance analysis of a hetero junction cylindrical gate all around field effect transistor (HJ-CGAA FET) is reported in this paper where source-drain material is germanium (Ge) and silicon (Si) is used as channel material. We also replaced the traditional silicon-di-oxide(SiO2) layer with silicon nitride (Si3N4). The simulation results indicate that this hetero junction structure is able to provide an improved performance over a conventional cylindrical gate all around FET. An optimized DIBL of 75.5167 mV/V and SS of 68.2 mV/dec is achieved for 10nm technology node from TCAD simulation. Oth

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14

Li, Cong, Feichen Liu, Ru Han, and Yiqi Zhuang. "A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application." IEEE Access 9 (2021): 63602–10. http://dx.doi.org/10.1109/access.2021.3074906.

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15

Nagy, Daniel, Guillermo Indalecio, Antonio J. Garcia-Loureiro, Muhammad A. Elmessary, Karol Kalna, and Natalia Seoane. "FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability." IEEE Journal of the Electron Devices Society 6 (2018): 332–40. http://dx.doi.org/10.1109/jeds.2018.2804383.

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16

Nagy, Daniel, Guillermo Indalecio, Antonio J. Garcia-Loureiro, Muhammad A. Elmessary, Karol Kalna, and Natalia Seoane. "Metal Grain Granularity Study on a Gate-All-Around Nanowire FET." IEEE Transactions on Electron Devices 64, no. 12 (2017): 5263–69. http://dx.doi.org/10.1109/ted.2017.2764544.

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17

Baek, Rock-Hyun, Chang-Ki Baek, Sang-Hyun Lee, et al. "$C$–$V$ Characteristics in Undoped Gate-All-Around Nanowire FET Array." IEEE Electron Device Letters 32, no. 2 (2011): 116–18. http://dx.doi.org/10.1109/led.2010.2092409.

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18

Mukesh, Sagarika, and Jingyun Zhang. "A Review of the Gate-All-Around Nanosheet FET Process Opportunities." Electronics 11, no. 21 (2022): 3589. http://dx.doi.org/10.3390/electronics11213589.

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In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed.

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19

Abbasnezhad, Reza, Hassan Rasooli Saghai, Reza Hosseini, Aliasghar Sedghi, and Ali Vahedi. "Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors." Journal of Electrical Engineering 74, no. 6 (2023): 503–12. http://dx.doi.org/10.2478/jee-2023-0058.

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Abstract In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (C gg), transconductance g m, and cut-off freque

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20

Madan, Jaya, R. S. Gupta, and Rishu Chaujar. "Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications." Microsystem Technologies 23, no. 9 (2016): 4081–90. http://dx.doi.org/10.1007/s00542-016-3143-5.

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21

Singh, Sarabdeep, and Ashish Raman. "A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects." Journal of Computational Electronics 17, no. 3 (2018): 967–76. http://dx.doi.org/10.1007/s10825-018-1166-0.

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22

Kim, Yeji, Yoongeun Seon, Soowon Kim, et al. "Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance." Electronics 10, no. 10 (2021): 1177. http://dx.doi.org/10.3390/electronics10101177.

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Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking

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23

Lin, Jinhan. "Advancement and Challenges of Field Effect Transistors based on Multi-gate Transistor." Journal of Physics: Conference Series 2370, no. 1 (2022): 012004. http://dx.doi.org/10.1088/1742-6596/2370/1/012004.

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The advancement and challenges of field effect transistors are based on multi-gate transistors from the perspective of structure and material. Multi-gate field-effect transistors (Multi-gate FET) have steeper sub-threshold slopes, which can reduce the short channel effect and improve mobility and drive current. A fin field-effect transistor (FinFET) and gate-all-around field-effect transistor (GAAFET) are attractive multi-gate structures most compatible with today’s standard machining technologies. As the future moves towards smaller processes, FinFET and GAAFET processes limit the spacing bet

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24

Luo, Wei, Chaofei Zha, Xia Zhang, Xin Yan, and Xiaomin Ren. "Synaptic devices based on gate-all-around InAs nanowire field effect transistor." Journal of Physics: Conference Series 2370, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2370/1/012015.

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In this paper, we proposed a gate-all-around InAs nanowire field effect transistor (GAA InAs NW FET) that can simulate synaptic behaviors such as short-term potentiation (STP) and long-term potentiation (LTP). The native oxide layer (In2O3) on the surface of InAs NW serves as a charge trapping layer for storing information. The transition from short-term potentiation (STP) to long-term potentiation (LTP) can be achieved by properly adjusting the gate voltage. Due to enhanced gate controllability, the GAA InAs NW FETs are expected to be widely used and promising in neuromorphic systems and netw

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25

Dutta, Umesh, M. K. Soni, and Manisha Pattanaik. "Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications." International Journal of Engineering & Technology 7, no. 4 (2018): 2263. http://dx.doi.org/10.14419/ijet.v7i4.12352.

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This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold sw

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26

Rana, Vaibhav, Gufran Ahmad, Akhil K. Ramesh, Samaresh Das, and Pushpapraj Singh. "Diameter-Dependent Piezoresistive Sensing Performance of Junctionless Gate-All-Around Nanowire FET." IEEE Transactions on Electron Devices 67, no. 7 (2020): 2884–89. http://dx.doi.org/10.1109/ted.2020.2991140.

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27

Goh, Kian-Hui, Sachin Yadav, Kain Lu Low, Gengchiau Liang, Xiao Gong, and Yee-Chia Yeo. "Gate-All-Around In0.53Ga0.47As Junctionless Nanowire FET With Tapered Source/Drain Structure." IEEE Transactions on Electron Devices 63, no. 3 (2016): 1027–33. http://dx.doi.org/10.1109/ted.2016.2526778.

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28

Ajay, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Model of GaSb-InAs p-i-n Gate All Around BioTunnel FET." IEEE Sensors Journal 19, no. 7 (2019): 2605–12. http://dx.doi.org/10.1109/jsen.2018.2887277.

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29

Dasgupta, Avirup, and Chenming Hu. "Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity." IEEE Electron Device Letters 41, no. 12 (2020): 1750–53. http://dx.doi.org/10.1109/led.2020.3032390.

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30

Madan, Jaya, Rahul Pandey, and Rishu Chaujar. "Conducting Polymer Based Gas Sensor Using PNIN- Gate All Around - Tunnel FET." Silicon 12, no. 12 (2020): 2947–55. http://dx.doi.org/10.1007/s12633-020-00394-5.

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31

Hakkee Jung. "Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric." International Journal of Engineering and Technology Innovation 14, no. 2 (2024): 189–200. http://dx.doi.org/10.46604/ijeti.2023.12887.

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This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gate-all-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metal-insulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an

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32

Won, Hyeonjae, and Myounggon Kang. "Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET." Applied Sciences 11, no. 3 (2021): 894. http://dx.doi.org/10.3390/app11030894.

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In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to the structural aspect through comparison of the two devices. Similar to n-type devices, p-type NW-FETs are less affected than FinFETs by the TID effect. For the inverter TID circuit simulation, both n- and p-types of FinFET and NW-FET were analyzed regarding the TID effect. The inverter operation considering the TID effect was verified using the Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. In addition, an inverter

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33

Singh, Sarabdeep, and Ashish Raman. "Gate-All-Around Charge Plasma-Based Dual Material Gate-Stack Nanowire FET for Enhanced Analog Performance." IEEE Transactions on Electron Devices 65, no. 7 (2018): 3026–32. http://dx.doi.org/10.1109/ted.2018.2816898.

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34

Madan, Jaya, and Rishu Chaujar. "Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability." IEEE Transactions on Device and Materials Reliability 16, no. 2 (2016): 227–34. http://dx.doi.org/10.1109/tdmr.2016.2564448.

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35

Lee, Jongwon, and Myounggon Kang. "TID Circuit Simulation in Nanowire FETs and Nanosheet FETs." Electronics 10, no. 8 (2021): 956. http://dx.doi.org/10.3390/electronics10080956.

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In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit opera

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36

Faiza, Merad, and Guen-Bouazza Ahlam. "DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4043–52. https://doi.org/10.11591/ijece.v10i4.pp4043-4052.

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum tr

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37

Mazumder, Abdullah Al Mamun, Kamal Hosen, Md Sherajul Islam, and Jeongwon Park. "Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET." IEEE Access 10 (2022): 30323–34. http://dx.doi.org/10.1109/access.2022.3159809.

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38

Kim, Shinkeun, Youngsoo Seo, Jangkyu Lee, Myounggon Kang, and Hyungcheol Shin. "GIDL analysis of the process variation effect in gate-all-around nanowire FET." Solid-State Electronics 140 (February 2018): 59–63. http://dx.doi.org/10.1016/j.sse.2017.10.017.

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39

Srivastava, Pooja, Aditi Upadhyaya, Shekhar Yadav, and C. M. S. Negi. "Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications." Semiconductor Science and Information Devices 5, no. 2 (2024): 1–10. http://dx.doi.org/10.30564/ssid.v5i2.6075.

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The advent of device miniaturization techniques and the evolution of very deep submicron technology have led to the increased prominence of short channel effects (SCEs) in conventional transistors (CTs). Now, in the era of nanoengineering and nano-wires, current research is centered around a novel device known as the Junctionless Field Effect Transistor (JLFET), which incorporates gate-all-around engineering applications. Given the challenges associated with scaling transistor sizes, such as creating high-quality junctions and changing doping concentrations (~1019 cm–3) over a 10 nm distance,

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40

Narula, Mandeep Singh, Archana Pandey, and Ajay Kumar. "Gate Electrode Work Function Engineered Nanowire FET with High Performance and Improved Process Sensitivity." March 2024 6, no. 1 (2024): 66–76. http://dx.doi.org/10.36548/jei.2024.1.006.

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MOSFETs have been used in integrated circuits for a long time. These were replaced by FinFET’s in 2011. But for short-channel devices, FinFET’s have low performance due to various effects like velocity saturation, hot carrier effect, drain-induced barrier lowering, channel length modulation, fringing field effect, sub-threshold conduction, threshold voltage roll-off, etc. Gate All Around FET (GAA FET) is the best device that will replace the FinFET’s. Therefore, during the fabrication process, it is crucial to investigate the effects of process variations caused by changes in device dimensions

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41

Batakala, Jeevan Rao. "Studying the Performance of Underlap GAA-FET." International Journal for Research in Applied Science and Engineering Technology 11, no. 9 (2023): 611–17. http://dx.doi.org/10.22214/ijraset.2023.55697.

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Abstract: This paper investigates the performance of underlap Gate-All-Around Field Effect Transistor (GAA FET) of 22nm gate length and evaluates the short channel performance of the device. Underlap GAA FET structure can be utilized to increase the drive current of the nanowire devices. In this work, underlap rectangular GAA FET is designed by extension of underlap regions on source/drain of GAA FET to increase the performance. This underlap device is increasing the capacitances by adding the fringing capacitances to parasitic capacitances which increases the fringing field from gate electrod

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42

Jung, Hakkee. "Analytical model of subthreshold swing in junctionless gate-all-around (GAA) FET with ferroelectric." AIMS Electronics and Electrical Engineering 7, no. 4 (2023): 322–36. http://dx.doi.org/10.3934/electreng.2023017.

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<abstract><p>An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in $15 \leqslant {P_r} \leqslant 30\,\mu C/c{m^2}$ and $0.8 \leqslant {E_c} \leqslant 1.5\,MV/cm$, which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from

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43

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this r

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44

Choi, Yejoo, Yuri Hong, and Changhwan Shin. "Device design guideline for junctionless gate-all-around nanowire negative-capacitance FET with HfO2-based ferroelectric gate stack." Semiconductor Science and Technology 35, no. 1 (2019): 015011. http://dx.doi.org/10.1088/1361-6641/ab5775.

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45

Alam, Md Rakibul, Tyafur Rahman Pathan, and Hamidur Rahman. "Drain Current Model of Graphene Channel G 4 -FET and Gate-All-Around MOSFET." IJIREEICE 6, no. 10 (2018): 1–8. http://dx.doi.org/10.17148/ijireeice.2018.6101.

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46

Dash, S., and G. P. Mishra. "An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET)." Advances in Natural Sciences: Nanoscience and Nanotechnology 7, no. 2 (2016): 025012. http://dx.doi.org/10.1088/2043-6262/7/2/025012.

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Im, Ki-Sik, Chul-Ho Won, Sindhuri Vodapally, et al. "Fabrication of normally-off GaN nanowire gate-all-around FET with top-down approach." Applied Physics Letters 109, no. 14 (2016): 143106. http://dx.doi.org/10.1063/1.4964268.

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Madan, Jaya, and Rishu Chaujar. "Palladium Gate All Around - Hetero Dielectric -Tunnel FET based highly sensitive Hydrogen Gas Sensor." Superlattices and Microstructures 100 (December 2016): 401–8. http://dx.doi.org/10.1016/j.spmi.2016.09.050.

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Yuhara, Daisuke, Kei Ikeda, Masayoshi Mikami, et al. "Reaction Mechanism Analysis of Si Selective Etching for Gate-All-Around Transistors by Molecular Simulations." Solid State Phenomena 346 (August 14, 2023): 74–79. http://dx.doi.org/10.4028/p-l5ef0w.

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Abstract:

The selective etching of Si in multi-stacked Si and SiGe structures is a key process to fabricate the next-generation of FET, Gate-all-around FET. In this study, we investigated the mechanism of wet chemical etching process at the molecular level for two common ionic solutions, potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). One of the important factors in the etching process is the reaction rate between the water and Si surface. Therefore, the water dynamics in i) bulk system and ii) Si wall confined system were mainly analyzed using molecular dynamics simulations. As a fe

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Dasgupta, Avirup, and Chenming Hu. "BSIM-CMG Compact Model for IC CAD: from FinFET to Gate-All-Around FET Technology." Journal of Microelectronic Manufacturing 3, no. 4 (2020): 1–8. http://dx.doi.org/10.33079/jomm.20030402.

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