Relevant bibliographies by topics / Gate-All-Around (GAA) Transistor

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Gate-All-Around (GAA) Transistor'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Gate-All-Around (GAA) Transistor"

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Im, Ki-Sik, Mallem Siva Pratap Reddy, Jinseok Choi, et al. "Characteristics of GaN-Based Nanowire Gate-All-Around (GAA) Transistors." Journal of Nanoscience and Nanotechnology 20, no. 7 (2020): 4282–86. http://dx.doi.org/10.1166/jnn.2020.17784.

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We investigate the DC, C–V, and pulse performances in GaN-based nanowire gate-all-around (GAA) transistors with two kinds of geometry: one is AlGaN/GaN heterostructure with two dimensional electron gas (2DEG) channel and the other is only GaN layer without 2DEG channel. From I–V and C–V curves, the fabricated GaN nanowire GAA transistor with AlGaN layer clearly exhibits normally-on operation with negative threshold voltage (Vth) due to the existence of 2DEG channel on the trapezoidal shaped GaN nanowire. On the other hand, the GaN nanowire GAA transistor without AlGaN layer presents a positive
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HOSSEINI, REZA, MORTEZA FATHIPOUR, and RAHIM FAEZ. "PERFORMANCE EVALUATION OF SOURCE HETEROJUNCTION STRAINED CHANNEL GATE ALL AROUND NANOWIRE TRANSISTOR." Modern Physics Letters B 26, no. 12 (2012): 1250076. http://dx.doi.org/10.1142/s0217984912500765.

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A Gate All Around Nanowire Transistor (GAA NWT) which employs source heterojunction and strained channel is proposed which improves device characteristics. A quantum mechanical transport approach based on nonequilibrium Green's function (NEGF) method in the frame work of effective mass theory is employed in this analysis. We evaluate the variation of the threshold voltage, the subthreshold slope, ON and OFF state currents when channel length decreases. It is shown that the source heterojunction strained channel GAA NWT gives high performance transistors values of the scaled transconductance an
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Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physic
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Han, Ke, Shanglin Long, Zhongliang Deng, Yannan Zhang, and Jiawei Li. "A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications." Micromachines 11, no. 2 (2020): 164. http://dx.doi.org/10.3390/mi11020164.

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This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelli
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Singh, Sarabdeep, Leo Raj Solay, Sunny Anand, Naveen Kumar, Ravi Ranjan, and Amandeep Singh. "Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier." Micromachines 14, no. 7 (2023): 1357. http://dx.doi.org/10.3390/mi14071357.

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This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA struc
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Gu, Jie, Qingzhu Zhang, Zhenhua Wu, et al. "Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs." Nanomaterials 11, no. 2 (2021): 309. http://dx.doi.org/10.3390/nano11020309.

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A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band stru
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Luo, Wei, Chaofei Zha, Xia Zhang, Xin Yan, and Xiaomin Ren. "Synaptic devices based on gate-all-around InAs nanowire field effect transistor." Journal of Physics: Conference Series 2370, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2370/1/012015.

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In this paper, we proposed a gate-all-around InAs nanowire field effect transistor (GAA InAs NW FET) that can simulate synaptic behaviors such as short-term potentiation (STP) and long-term potentiation (LTP). The native oxide layer (In2O3) on the surface of InAs NW serves as a charge trapping layer for storing information. The transition from short-term potentiation (STP) to long-term potentiation (LTP) can be achieved by properly adjusting the gate voltage. Due to enhanced gate controllability, the GAA InAs NW FETs are expected to be widely used and promising in neuromorphic systems and netw
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Vimala, Palanichamy, and N. R. Nithin Kumar. "Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET." Journal of Nano Research 59 (August 2019): 137–48. http://dx.doi.org/10.4028/www.scientific.net/jnanor.59.137.

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The paper proposes analytical model for Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA-MOSFET) for germanium channel including quantum mechanical effects. It is achieved by solving coupled Schrodinger-Poisson’s equation using variational approach. The proposed model takes quantum confinement effects to obtain charge centroid and inversion charge model. By using these models the quantum version of inversion layer capacitance, inversion charge distribution function and Drain current expressions are modelled and the performance evaluation of the developed model is compared
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Zhang, Yannan, Ke Han, and and Jiawei Li. "A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator." Micromachines 11, no. 2 (2020): 223. http://dx.doi.org/10.3390/mi11020223.

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Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low
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Abdul-Kadir, Firas Natheer, Yasir Hashim, Muhammad Nazmus Shakib, and Faris Hassan Taha. "Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 780. http://dx.doi.org/10.11591/ijece.v11i1.pp780-787.

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3n
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Dissertations / Theses on the topic "Gate-All-Around (GAA) Transistor"

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Harrison, Samuel. "Dispositifs GAA [Gate-All-Around] en technologie SON [Silicon-On-Nothing] : conception, caractérisation et modélisation en vue de l'intégration dans les noeuds CMOS avancés." Aix-Marseille 1, 2005. http://www.theses.fr/2005AIX11021.

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Depuis près de quarante ans, la densité d'intégration des transistors est doublée tous les deux ans environ, en suivant un rythme infernal dicté par la fameuse " loi de Moore ". Pourtant, cette dernière est aujourd'hui remise en question. En effet, pour la première fois, le transistor MOS " historique " est sur le point de buter sur des barrières physiques, électriques et technologiques quasi-insurmontables. La réduction des dimensions caractéristiques principales du MOS (mais aussi des tensions d'alimentation) s'accompagne de l'apparition d'un grand nombre d'effets parasites (effets canaux co
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Ray, Biswajit. "Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective." Thesis, 2008. https://etd.iisc.ac.in/handle/2005/741.

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Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the
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Ray, Biswajit. "Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective." Thesis, 2008. http://hdl.handle.net/2005/741.

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Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the
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Lin, Chia-Min, and 林家名. "A Study of the Crystallization Methods on Gate-All-Around (GAA) Poly-Si Nanowire Thin-Film-Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/46138675336333852345.

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碩士<br>逢甲大學<br>產業研發碩士班<br>97<br>Poly-Si thin film transistors (TFTs) have been widely used as switching elements in active-matrix displays. For applications on system-on-panel (SOP) and three-dimension integrated circuits (3-D ICs), further improvement of device performance are required. The mobility is one of the most important electrical characteristic in poly-Si TFTs, which is profoundly dependent on the grain sizes within channel region. The use of excimer laser crystallization is the main approach to enlarge the grain size, but its size of grain growth is still limited. Other than crystall
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Book chapters on the topic "Gate-All-Around (GAA) Transistor"

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Julien, Levisse Alexandre Sébastien, Xifan Tang, and Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices." In Emerging Computing: From Devices to Systems. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.

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AbstractSince the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (Faynot et al. 2010) transistors have therefore been proposed. All these solutions enabled Moore’s law scaling to continue. However, when approaching sub-10nm technology nodes, the story starts again. Again, process costs and electrical issues reduce the profitability of such solutions, and new technologies such as Gate-All-Around (GAA) (Sacchetto et al. 2009) transistors are seen as future FinFET replacement candidates.
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Verma, Yogesh Kumar, Varun Mishra, Rohit Gurjar, Rajeev Kumar Chauhan, and Santosh Kumar Gupta. "Simulation-Based Analysis of AlGaN/GaN Gate All Around Field Effect Transistor (AlGaN/GaN GAA-FET)." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0312-0_21.

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Chatterjee, Neel, and Sujata Pandey. "Multiphysics Analysis of Heat Transfer in Gate All Around (GAA) Silicon Nanowire Transistor: Material Perspective." In Springer Proceedings in Physics. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29096-6_6.

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Srivastava, Shobhit, and Abhishek Acharya. "Challenges and future scope of gate-all-around (GAA) transistors." In Device Circuit Co-Design Issues in FETs. CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-11.

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Kumar, Raj, Shashi Bala, and Arvind Kumar. "Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors." In Advances in Computer and Electrical Engineering. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch003.

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To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.
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Conference papers on the topic "Gate-All-Around (GAA) Transistor"

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Narang, Rakhi, Manoj Saxena, R. S. Gupta, and Mridula Gupta. "An analytical modeling approach for a gate all around (GAA) tunnel field effect transistor (TFET)." In 16th International Workshop on Physics of Semiconductor Devices, edited by Monica Katiyar, B. Mazhari, and Y. N. Mohapatra. SPIE, 2012. http://dx.doi.org/10.1117/12.925534.

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Lee, Ryoongbin, Suhyeon Kim, Sangwan Kim, et al. "Simulation study on influence of interface trap position in Sii-xGex Gate-All-Around (GAA) field-effect transistor." In 2018 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2018. http://dx.doi.org/10.23919/elinfocom.2018.8330548.

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Seo, Jae Hwa, Young Jun Yoon, Hwan Gi Lee, and In Man Kang. "Design optimization InGaAs/GaAsSb-based heterojunction Gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET)." In 2018 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2018. http://dx.doi.org/10.23919/elinfocom.2018.8330638.

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Ou, Jiaojiao, Ru Huang, Yuchao Liu, Runsheng Wang, and Yangyuan Wang. "Performance investigation of SRAM cells based on gate-all-around (GAA) Si nanowire transistor for ultra-low voltage applications." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6466743.

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Kumar, Parveen, and Balwinder Raj. "Design and Simulation of Silicon Nanowire Tunnel Field Effect Transistor." In International Conference on Women Researchers in Electronics and Computing. AIJR Publisher, 2021. http://dx.doi.org/10.21467/proceedings.114.62.

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This paper analyses the different parameters of tunnel field-effect transistor (TFET) based on silicon Nanowire in vertical nature by using a Gaussian doping profile. The device has been designed using an n-channel P+-I-N+ structure for tunneling junction of TFET with gate-all-around (GAA) Nanowire structure. The gate length has been taken as 100 nm using silicon Nanowire to obtain the various parameters such as ON-current (ION), OFF-current (IOFF), current ratio, and Subthreshold slope (SS) by applying different values of work function at the gate, the radius of Nanowire and oxide thickness o
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Seo, Jae Hwa, Young Jun Yoon, Ra Hee Kwon, Young In Jang, and In Man Kang. "Design optimization of Si/Ge-based heterojunction arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) which applicable for future mobile communication systems." In 2016 International Conference on Information Networking (ICOIN). IEEE, 2016. http://dx.doi.org/10.1109/icoin.2016.7427155.

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Li, J., S. Mochizuki, E. Stuckert, et al. "Precession Electron Diffraction (PED) Strain Characterization in Stacked Nanosheet FET Structure." In ISTFA 2022. ASM International, 2022. http://dx.doi.org/10.31399/asm.cp.istfa2022p0074.

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Abstract Non-planar semiconductor devices, such as vertical fin-based field-effect transistor (FinFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area. However, as circuits are scaled to smaller dimensions, it has become increasingly difficult to improve the performance of FinFET devices. Stacked nanosheet FETs have been developed to further enable larger effective conduction width in a given small layout area while enabling gate length scaling. Nanosheet (NS) FET devices ha
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Chatterjee, Neel, and Sujata Pandey. "Modelling and simulation of Si and InAs gate all around (GAA) nanowire transistors." In 2015 Annual IEEE India Conference (INDICON). IEEE, 2015. http://dx.doi.org/10.1109/indicon.2015.7443527.

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Wang, Luhao, Tiansong Cui, Shahin Nazarian, Yanzhi Wang, and Massoud Pedram. "Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors." In 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905480.

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Ahn, Min-Ju, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto. "Superior subthreshold slope of gate-all-around (GAA) p-type poly-Si junctionless nanowire transistors with highly suppressed grain boundary defects." In 2020 IEEE Silicon Nanoelectronics Workshop (SNW). IEEE, 2020. http://dx.doi.org/10.1109/snw50361.2020.9131416.

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