Journal articles: 'Gate-All-Around (GAA) Transistor'

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Im, Ki-Sik, Mallem Siva Pratap Reddy, Jinseok Choi, Youngmin Hwang, Jea-Seung Roh, Sung Jin An, and Jung-Hee Lee. "Characteristics of GaN-Based Nanowire Gate-All-Around (GAA) Transistors." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4282–86. http://dx.doi.org/10.1166/jnn.2020.17784.

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We investigate the DC, C–V, and pulse performances in GaN-based nanowire gate-all-around (GAA) transistors with two kinds of geometry: one is AlGaN/GaN heterostructure with two dimensional electron gas (2DEG) channel and the other is only GaN layer without 2DEG channel. From I–V and C–V curves, the fabricated GaN nanowire GAA transistor with AlGaN layer clearly exhibits normally-on operation with negative threshold voltage (Vth) due to the existence of 2DEG channel on the trapezoidal shaped GaN nanowire. On the other hand, the GaN nanowire GAA transistor without AlGaN layer presents a positive Vth (normally-off operation) due to the absent of 2DEG channel on the triangle shaped GaN nanowire. However, both devices show the similar temperaturedependent I–V characteristics due to the combination of bulk channel and surface channel in GaN nanowire GAA channel are mostly contributed, rather than the 2DEG channel. GaN-based nanowire GAA transistors demonstrate to almost negligible current collapse phenomenon due to the perfect GAA gate structure in GaN nanowire. The proposed GaN-based nanowire GAA transistors are very promising candidate for both high power device and nano-electronics application.

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HOSSEINI, REZA, MORTEZA FATHIPOUR, and RAHIM FAEZ. "PERFORMANCE EVALUATION OF SOURCE HETEROJUNCTION STRAINED CHANNEL GATE ALL AROUND NANOWIRE TRANSISTOR." Modern Physics Letters B 26, no. 12 (April 26, 2012): 1250076. http://dx.doi.org/10.1142/s0217984912500765.

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A Gate All Around Nanowire Transistor (GAA NWT) which employs source heterojunction and strained channel is proposed which improves device characteristics. A quantum mechanical transport approach based on nonequilibrium Green's function (NEGF) method in the frame work of effective mass theory is employed in this analysis. We evaluate the variation of the threshold voltage, the subthreshold slope, ON and OFF state currents when channel length decreases. It is shown that the source heterojunction strained channel GAA NWT gives high performance transistors values of the scaled transconductance and ON current that are greater than conventional silicon GAA NWT. Furthermore, comparison of switching delay τd and unity current gain frequency fT of the devices shows that the performance of source heterojunction strained channel GAA NWT is better than the conventional silicon GAA NWT.

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Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (September 4, 2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.

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Han, Ke, Shanglin Long, Zhongliang Deng, Yannan Zhang, and Jiawei Li. "A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications." Micromachines 11, no. 2 (February 3, 2020): 164. http://dx.doi.org/10.3390/mi11020164.

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This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

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Singh, Sarabdeep, Leo Raj Solay, Sunny Anand, Naveen Kumar, Ravi Ranjan, and Amandeep Singh. "Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier." Micromachines 14, no. 7 (June 30, 2023): 1357. http://dx.doi.org/10.3390/mi14071357.

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This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications.

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Gu, Jie, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, et al. "Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs." Nanomaterials 11, no. 2 (January 26, 2021): 309. http://dx.doi.org/10.3390/nano11020309.

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A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

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Luo, Wei, Chaofei Zha, Xia Zhang, Xin Yan, and Xiaomin Ren. "Synaptic devices based on gate-all-around InAs nanowire field effect transistor." Journal of Physics: Conference Series 2370, no. 1 (November 1, 2022): 012015. http://dx.doi.org/10.1088/1742-6596/2370/1/012015.

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In this paper, we proposed a gate-all-around InAs nanowire field effect transistor (GAA InAs NW FET) that can simulate synaptic behaviors such as short-term potentiation (STP) and long-term potentiation (LTP). The native oxide layer (In2O3) on the surface of InAs NW serves as a charge trapping layer for storing information. The transition from short-term potentiation (STP) to long-term potentiation (LTP) can be achieved by properly adjusting the gate voltage. Due to enhanced gate controllability, the GAA InAs NW FETs are expected to be widely used and promising in neuromorphic systems and networks.

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Vimala, Palanichamy, and N. R. Nithin Kumar. "Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET." Journal of Nano Research 59 (August 2019): 137–48. http://dx.doi.org/10.4028/www.scientific.net/jnanor.59.137.

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The paper proposes analytical model for Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA-MOSFET) for germanium channel including quantum mechanical effects. It is achieved by solving coupled Schrodinger-Poisson’s equation using variational approach. The proposed model takes quantum confinement effects to obtain charge centroid and inversion charge model. By using these models the quantum version of inversion layer capacitance, inversion charge distribution function and Drain current expressions are modelled and the performance evaluation of the developed model is compared with Silicon channel GAA-MOSFET. Analytically modelled expressions are verified by comparing the model with simulation results.

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Zhang, Yannan, Ke Han, and and Jiawei Li. "A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator." Micromachines 11, no. 2 (February 21, 2020): 223. http://dx.doi.org/10.3390/mi11020223.

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Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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Abdul-Kadir, Firas Natheer, Yasir Hashim, Muhammad Nazmus Shakib, and Faris Hassan Taha. "Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 780. http://dx.doi.org/10.11591/ijece.v11i1.pp780-787.

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.

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Vimala, P., and N. R. Nithin Kumar. "Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor." Journal of Nano Research 64 (November 2020): 115–22. http://dx.doi.org/10.4028/www.scientific.net/jnanor.64.115.

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The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

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Kang, Seok Jung, Jeong-Uk Park, Kyung Jin Rim, Yoon Kim, Jang Hyun Kim, Garam Kim, and Sangwan Kim. "Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4409–13. http://dx.doi.org/10.1166/jnn.2020.17792.

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In this manuscript, channel area fluctuation (CAF) effects on turn-on voltage (Von) and subthreshold swing (SS) in gate-all-around (GAA) nanowire (NW) tunnel field-effect transistor (TFET) with multi-bridge-channel (MBC) have been investigated for the first time. These variations occur because oblique etching slope makes various elliptical-shaped channels in MBC-TFET. Since TFET is promising candidates to succeed metal-oxide-semiconductor FETs (MOSFET), these variation effects have been compared to MOSFET. Furthermore, Ge homojunction TFET, one of the solutions to increase on-state current in TFET and improve SS also has been simulated using technology computer-aided design (TCAD) simulation. The results would be worth reference for future study about GAA NW TFETs.

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Pananakakis, Georges, Gérard Ghibaudo, and Sorin Cristoloveanu. "Nanodevices Tend to Be Round." Micromachines 12, no. 3 (March 20, 2021): 330. http://dx.doi.org/10.3390/mi12030330.

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Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by smaller size, lower doping, and higher gate voltage. After defining the geometrical criterion for square-to-circle shift, simulation results are used to document the main consequences. This transition occurs naturally in nanowires thinner than 50 nm. The results are rather universal, and supportive evidence is gathered from inversion-mode Gate-All-Around (GAA) MOSFETs as well as from thermal diffusion process.

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Kim, Yeji, Yoongeun Seon, Soowon Kim, Jongmin Kim, Saemin Bae, Inkyung Yang, Changhyun Yoo, Junghoon Ham, Jungmin Hong, and Jongwook Jeon. "Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance." Electronics 10, no. 10 (May 14, 2021): 1177. http://dx.doi.org/10.3390/electronics10101177.

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Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness (tfe), intermediate insulator thickness (tox), silicon channel radius (R), and interface trap densities (Net).

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Pandian, M. Karthigai, N. B. Balamurugan, and A. Pricilla. "Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/153157.

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An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.

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Simoen, Eddy, Carlos H. S. Coelho, Vanessa C. P. da Silva, João A. Martino, Paula Ghedini Der Agopian, Alberto Oliveira, Bogdan Cretu, and Anabela Veloso. "Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications." Journal of Integrated Circuits and Systems 17, no. 2 (September 17, 2022): 1–9. http://dx.doi.org/10.29292/jics.v17i2.617.

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In this review paper, the performance characteristics of Gate-All-Around (GAA) double nanosheet (NS) MOSFETs are described over a broad temperature range, from 78 K to 473 K (200 oC). Emphasis is on the analog operation, showing good potential. Besides the transistor length, the impact of the metal gate Effective Work Function and the vertical distance between the nanosheets has been studied. Among others, a clear Zero Temperature Coefficient (ZTC) gate voltage has been observed that can be modeled by considering the shift with temperature of the threshold voltage and the maximum transconductance. A trade-off has been noticed between the transistor efficiency and the unit gain frequency, whereby the optimal operation point occurs in strong inversion regime. The feasibility of designing simple analog circuits has also been demonstrated. Finally, a detailed investigation of the low-frequency noise behavior yields good values for the flicker noise Power Spectral Density in comparison with other technology nodes.

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Yang, Jingwen, Ziqiang Huang, Dawei Wang, Tao Liu, Xin Sun, Lewen Qian, Zhecheng Pan, et al. "A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors." Micromachines 14, no. 6 (May 24, 2023): 1107. http://dx.doi.org/10.3390/mi14061107.

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In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

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Bayani, Amir Hossein, Daryoosh Dideban, Mojtaba Akbarzadeh, and Negin Moezi. "Benchmarking Performance of a Gate-All-Around Germanium Nanotube Field Effect Transistor (GAA-GeNTFET) against GAA-CNTFET." ECS Journal of Solid State Science and Technology 6, no. 4 (2017): M24—M28. http://dx.doi.org/10.1149/2.0211704jss.

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Lee, Jongwon, and Myounggon Kang. "TID Circuit Simulation in Nanowire FETs and Nanosheet FETs." Electronics 10, no. 8 (April 16, 2021): 956. http://dx.doi.org/10.3390/electronics10080956.

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In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET.

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Ma, Yue, Jinshun Bi, Sandip Majumdar, Safdar Mehmood, Lanlong Ji, Yichao Sun, Chenrui Zhang, et al. "The influences of radiation effects on DC/RF performances of L _g = 22 nm gate-all-around nanosheet field-effect transistor." Semiconductor Science and Technology 37, no. 3 (January 24, 2022): 035010. http://dx.doi.org/10.1088/1361-6641/ac4af5.

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Abstract In this paper, we carried out detailed technology computer aided design simulations to investigate the radiation effects, e.g. total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of seven-layer stacked GAA nanosheet FET with L g = 22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ∼3 mA μm−1 and 47 mV V−1, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the fin FET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

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Merad, Faiza, and Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

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Liu, Enxu, Junjie Li, Na Zhou, Rui Chen, Hua Shao, Jianfeng Gao, Qingzhu Zhang, et al. "Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process." Nanomaterials 13, no. 14 (July 21, 2023): 2127. http://dx.doi.org/10.3390/nano13142127.

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Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures.

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Tiwari, Sanjana, Arya Dutt, Mayuresh Joshi, Prakhar Nigam, Ankur Beohar, and Ribu Mathew. "In-silico Investigation of Cyl. Gate all Around (GAA) Tunnel Field Effect Transistor (TFET) Biosensor." IOP Conference Series: Materials Science and Engineering 1166, no. 1 (July 1, 2021): 012045. http://dx.doi.org/10.1088/1757-899x/1166/1/012045.

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Mochizuki, Shogo, Juntao Li, Erin Stuckert, Huimei Zhou, and Nicolas Loubet. "Compressive Strained Si_1-XGe_x Channel for High Performance Gate-All-Around Nanosheet Transistors." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1192. http://dx.doi.org/10.1149/ma2022-02321192mtgabs.

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As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing. To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa. Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel. The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1

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Yoon, Young Jun, Jae Sang Lee, Dong-Seok Kim, Sang Ho Lee, and In Man Kang. "One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure." Electronics 9, no. 12 (December 13, 2020): 2134. http://dx.doi.org/10.3390/electronics9122134.

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This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 108 and a long retention time above 10 ms.

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Dutta, Umesh, M. K. Soni, and Manisha Pattanaik. "Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications." International Journal of Engineering & Technology 7, no. 4 (September 17, 2018): 2263. http://dx.doi.org/10.14419/ijet.v7i4.12352.

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This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average sub-threshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

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Seo, Jae Hwa, Young Jun Yoon, Young-Woo Jo, Dong-Hyeok Son, Seongjae Cho, Hyuck-In Kwon, Jung-Hee Lee, and In Man Kang. "Design Optimization of InAs-Based Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (TFET)." Journal of Nanoscience and Nanotechnology 16, no. 10 (October 1, 2016): 10199–203. http://dx.doi.org/10.1166/jnn.2016.13127.

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Seo, Jae Hwa, Young Jun Yoon, Jung-Hee Lee, and In Man Kang. "Design Optimization and Analysis of InGaAs-Based Gate-All-Around (GAA) Junctionless Field-Effect Transistor (JLFET)." Journal of Nanoscience and Nanotechnology 17, no. 11 (November 1, 2017): 8350–54. http://dx.doi.org/10.1166/jnn.2017.15133.

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Mohapatra, Eleena, Jhansirani Jena, Devika Jena, Sanghamitra Das, and Taraprasanna Dash. "Design technique co-optimization approach to GAA FETs for inverter design at advanced technology node." Nanomaterials and Energy 12, no. 2 (June 1, 2023): 1–7. http://dx.doi.org/10.1680/jnaen.23.00029.

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Gate-all-around Nanosheet field-effect transistor (GAA-NSFET) is a potential replacement for the state-of-art FinFET devices at advanced technology nodes. In this article, the impact of process-induced variability such as gate work function variation (WFV) on NSFETs using 3D TCAD numerical device simulation is studied. The WFV of NSFETs and NWFETs using multiple stack channels are also analyzed. The fluctuation in the threshold voltage (σVTH) and on-current (σION) of NSFETs is mainly affected by the WFV of the metal gate. It is investigated that single and 3-stacked NSFET shows superior immunity to WFV compared to NWFET. Furthermore, a layout-based NSFET inverter design using the DTCO technique is followed and the advantages of the stacked NSFET in terms of delay, power dissipation and switching energy are also reported.

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Seo, Jae Hwa, Young Jun Yoon, and In Man Kang. "Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET)." Journal of Nanoscience and Nanotechnology 18, no. 9 (September 1, 2018): 6602–5. http://dx.doi.org/10.1166/jnn.2018.15705.

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Dhake, Pratiksha, Jyotirmoy Ghosh, Mayuresh Joshi, Ribu Mathew, and Ankur Beohar. "Suppress Short Channel Effects on Split Channel-Cylindrical GAA TFET Using Buried Oxide Layer." Key Engineering Materials 934 (November 28, 2022): 15–22. http://dx.doi.org/10.4028/p-i221xc.

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The idea of a buried oxide layer (BOx) in a split channel Gate All Around-Tunnel Field Effect Transistor (GAA-TFET) was investigated in this paper. This work examined the impact of buried oxide layer on the device's performance. With the BOx layer present and channel length of 20nm, the channel area of the TFET device investigated in this study is divided equally on the same side. The doping concentration has been transferred to the split channel on the drain side. The device’s performance was examined using numerical simulation utilizing simulation software of CAD devices. The final results which incorporate the buried oxide layer were being compared to the uniform split channel GAA-TFET. The parameters like ON current (Ion),OFF current (Ioff), subthreshold swing (SS) and electric-field (E) intensity are observed and compared with silicon (Si) based GAA-TFET and Indium phosphide (InP) based GAA-TFET. It is found that InP based GAA-TFET with buried oxide layer is more advanced device design than the others with Ion and Ioff of 3.02 x 10-05 A/um and 2.09 x 10-22 A/um, respectively.

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Seo, Jae Hwa, Young Jun Yoon, Seongmin Lee, Jung-Hee Lee, Seongjae Cho, and In Man Kang. "Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)." Current Applied Physics 15, no. 3 (March 2015): 208–12. http://dx.doi.org/10.1016/j.cap.2014.12.013.

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Li, Yiming, Chieh-Yang Chen, Min-Hui Chuang, and Pei-Jung Chao. "Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits." Materials 12, no. 9 (May 8, 2019): 1492. http://dx.doi.org/10.3390/ma12091492.

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In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.

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Thakur, Rajiv Ranjan, and Nidhi Chaturvedi. "Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications." Nano 16, no. 08 (July 2021): 2150096. http://dx.doi.org/10.1142/s179329202150096x.

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In this paper, design and parameter optimization for the performance analysis of a Gate-All-Around GaN Nanowire Field Effect Transistor (GAA GaN NWFET) has been carried out based on the various quantum ballistic simulation models. The simulation results show a novel way to change the device mode of operation from Depletion-mode (D-Mode) to Enhancement mode (E-Mode) and vice-versa by varying the thickness of the nanowire channel ([Formula: see text], which has not been reported yet to the best of our knowledge. Also, the paper reveals novel approaches (i) threshold voltage ([Formula: see text] tuning using metal contact length ([Formula: see text], (ii) threshold voltage ([Formula: see text] tuning using metal electrode work functions ([Formula: see text] and (iii) threshold voltage ([Formula: see text] tuning using metal contact width ([Formula: see text]. The device has an [Formula: see text]/[Formula: see text] ratio of 105, suppressed off-state leakage in the range of 10[Formula: see text]–10[Formula: see text]A. The simulation work has been carried out on a commercially available ATLAS device simulator from Silvaco.

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Li, Ming, Gong Chen, and Ru Huang. "High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments." Applied Sciences 8, no. 9 (September 4, 2018): 1553. http://dx.doi.org/10.3390/app8091553.

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In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular or quadrate one in terms of the subthreshold swing, on/off ratio, and SCE immunity, which resulted from the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Following this, we fabricated triangular cross-sectional GAA SNWTs with a nanowire width down to 20 nm by TMAH wet etching. This process featured its self-stopped etching behavior on a silicon (1 1 1) crystal plane, which made the triangular cross section smooth and controllable. The fabricated triangular SNWT showed an excellent performance with a large Ion/Ioff ratio (~107), low SS (85 mV/dec), and preferable DIBL (63 mV/V). Finally, the surface roughness mobility of the fabricated device at a low temperature was also extracted to confirm the benefit of a stable cross section.

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Ajay, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)." Journal of Computational Electronics 17, no. 2 (March 27, 2018): 713–23. http://dx.doi.org/10.1007/s10825-018-1151-7.

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Solay, Leo Raj, S. Intekhab Amin, Pradeep Kumar, and Sunny Anand. "Enhancing the design and performance of a gate-all-around (GAA) charge plasma nanowire field-effect transistor with the help of the negative-capacitance technique." Journal of Computational Electronics 20, no. 6 (November 11, 2021): 2350–59. http://dx.doi.org/10.1007/s10825-021-01808-2.

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Bayani, Amir Hossein, Jan Voves, and Daryoosh Dideban. "Effective mass approximation versus full atomistic model to calculate the output characteristics of a gate-all-around germanium nanowire field effect transistor (GAA-GeNW-FET)." Superlattices and Microstructures 113 (January 2018): 769–76. http://dx.doi.org/10.1016/j.spmi.2017.12.019.

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Lee, Yao-Jen, Shu-Wei Chang, Wen-Hsi Lee, and Yeong-Her Wang. "(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1289. http://dx.doi.org/10.1149/ma2022-02351289mtgabs.

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Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit. [1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

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Wang, Dawei, Xin Sun, Tao Liu, Kun Chen, Jingwen Yang, Chunlei Wu, Min Xu, and Wei (David) Zhang. "Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node." Electronics 12, no. 3 (February 3, 2023): 770. http://dx.doi.org/10.3390/electronics12030770.

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Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (Isub) and punch-through leakage (IPT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (Ion, Ioff), subthreshold swing (SS), RC delay, and gate capacitance (Cgg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (Lrcs) variations. For both device types, larger Lrcs will result in a shorter effective channel length (Leff), so that the Ion and Ioff simultaneously increase. At the constant Ioff, the Lrcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger Cgg as a penalty. Secondly, S/D over recess depth (Hrcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less Ioff sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both Hrcs and Lrcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.

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Kim, Soohyun, Jungchun Kim, Doyoung Jang, Romain Ritzenthaler, Bertrand Parvais, Jerome Mitard, Hans Mertens, Thomas Chiarella, Naoto Horiguchi, and Jae Woo Lee. "Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET." Applied Sciences 10, no. 8 (April 24, 2020): 2979. http://dx.doi.org/10.3390/app10082979.

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The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (VTH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μeff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak Ninv (= 5 × 1012 cm2/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in μeff. On the other hand, at strong Ninv (= 1.5 × 1013 cm2/V∙s), GAA NW-FET shows 10 times higher dμeff/dT and 1.6 times smaller mobility degradation coefficient (α) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport.

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Samuel, T. S. Arun, N. Arumugam, and S. Theodore Chandra. "Analytical Approach and Simulation of GaN Single Gate TFET and Gate All around TFET." ECTI Transactions on Electrical Engineering, Electronics, and Communications 15, no. 2 (May 28, 2014): 1–7. http://dx.doi.org/10.37936/ecti-eec.2017152.171311.

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In this work, we investigate the impact of Gallium Nitride (GaN) based Single Gate Tunnel field effect transistors (SG TFET) and Gate All Around (GAA) TFET by using analytical models. The models are derived by solving the 2D-Poisson’s equation and Parabolic Approximation Technique. The analytical model includes the calculation of the surface potential, lateral electric field and vertical electric field. Finally the drain current is extracted by using Kane’s model. The device simulations are carried out using 2-D device simulator, Technology Computer Aided Design (TCAD). The model can be used to study the impact of GaN based SG TFET and GAA TFET in terms of higher ON current characteristics. The results expected by the model are compared with those obtained by 2-D simulation to verify the accuracy of the proposed analytical model.

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Li, Junjie, Yongliang Li, Na Zhou, Wenjuan Xiong, Guilei Wang, Qingzhu Zhang, Anyan Du, et al. "Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors." Nanomaterials 10, no. 4 (April 20, 2020): 793. http://dx.doi.org/10.3390/nano10040793.

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Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

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Veloso, Anabela, Geert Eneman, Eddy Simoen, Bogdan Cretu, An De Keersgieter, Anne Jourdain, and Naoto Horiguchi. "(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1059. http://dx.doi.org/10.1149/ma2022-01191059mtgabs.

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CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option to replace finFETs. Reduced gate lengths should be feasible thanks to their improved electrostatics, thus allowing further scaling of the contacted-gate-pitch and of the cell height via a reduced number of metal tracks. Other key characteristics include high design flexibility, with various NS widths possible on a given wafer, and larger drivability per layout footprint by increasing the number of vertically stacked NS per device and/or using wider NS [1,2] (Fig.1). An extension of this technology could in principle be envisioned by strongly reducing the p-n separation in the so-called forksheet configuration [3]. Beyond that, the concept of stacking devices with different polarity on top of each other is also being looked at [4,5]. Other future technology candidates include FETs with vertical transport [6] and non-silicon channels [7]. Each new architecture will have its own specific challenges such as the internal routeability for stacked structures in functional logic blocks (e.g., standard cell or SRAM) but, in general, many elements can be shared by the various branches of the NS family of devices. Overall, a careful balance between drive strength and capacitance is required in NS FETs engineering. In particular, the presence of dielectric inner spacers in-between vertically stacked nanosheets is a critical element, also as it leads to a different growth regime for the source/drain (S/D) epi as compared to the situation in finFETs [8]. This is an important differentiator as channel strain induced by S/D has been traditionally used to boost device performance. The feasibility of continuing using process-induced stress techniques for mobility enhancement is in fact a key challenge for several new architectures, namely for the top device in stacked structures or when S/D are placed in different vertical levels. Moreover, faced with power scaling stagnation, cold computing is also becoming an attractive option to consider for enabling high performance boosting in an energy efficient way. Our results confirm improved DC properties for NS FETs (e.g., subthreshold swing (SS), mobility), with similar mechanisms responsible for their noise behavior at room and low temperatures (300K (RT), 78K) [9]. In addition to the need for the introduction of new transistor technologies, given the increased complexity and cost in back-end-of-line processing, it has also become ever more pressing to address both wiring and power delivery network (PDN) bottlenecks to take full advantage of the scaling performance benefits at transistor level. The concept of moving the PDN to the wafer’s backside (BS) such that it can alleviate routing congestion on its frontside (FS) has been recently gaining traction [10,11]. This is illustrated in Fig.2 wherein, by combining logic and 3D technologies, both wafer sides are used. In our work, after frontside processing, device and carrier wafers are bonded at RT, including a 523K post-bond anneal. Extreme wafer thinning is then implemented prior to nano-through-silicon-vias (n-TSV) definition (landing on the metal-1 level (M1) in the frontside) and backside metallization. Evaluating the impact on scaled transistors from BS processing, our results show similar p/n threshold voltages (VTs) can be obtained with an extra sinter at the end of fabrication. Inclusion of an additional high-pressure H2-anneal prior to the final sinter is also seen to help lower the SS values for pmos without significant IOFF effect. Reliability-wise, constant ramped voltage stress measurements also show no BTI degradation for p/nmos, with additional indication of potential benefits by the final anneal(s) treatment selection. These findings are further corroborated by LF-noise analysis. References [1] N. Loubet et al., VLSI Tech. Dig., 2017, p.230. [2] A. Veloso et al., SSDM Tech. Dig., 2019, p.559. [3] P. Weckx et al., IEDM Tech. Dig., 2019, p.871. [4] W. Rachmady et al., IEDM Tech. Dig., 2019, p.697. [5] C.-Y. Huang et al., IEDM Tech. Dig., 2020, p.425. [6] A. Veloso et al., IEDM Tech. Dig., 2019, p.230. [7] P.-C. Shen et al., Nature, 2021, Vol.593, p.211. [8] G. Eneman et al., ECS Trans., 2020, Vol.98(5), p.253. [9] B. Cretu et al., EuroSOI-ULIS Tech. Dig., 2021. [10] A. Veloso et al., VLSI Tech. Dig., 2021, TFS2-6. [11] https://www.intel.com/content/www/us/en/events/accelerated.html. Figure 1

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Yang, Jingwen, Kun Chen, Dawei Wang, Tao Liu, Xin Sun, Qiang Wang, Ziqiang Huang, et al. "Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device." Micromachines 14, no. 3 (March 7, 2023): 611. http://dx.doi.org/10.3390/mi14030611.

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In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress caused serious deformation to suspended nanosheets. With the guidance of the experiment result, based on simulation studies using the COMSOL Multiphysics and Sentaurus tools, it is confirmed that the stress applied on the channel from source/drain plays an important role in nanosheet deformation during the fabrication process. The deformation of Si nanosheets would cause a serious degradation of the device performance due to an inability to control the work function of the metal gate. This study proposed that the uniformly stacked GAA nanosheets structure could be successfully demonstrated with suitable channel stress engineering provided by fitting S/D size and an appropriate channel length. The conclusions provide useful guidelines for future stacked GAA transistors’ design and fabrication.

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Lee, In-Geun, Hyeon-Bhin Jo, Ji-Min Baek, Sang-Tae Lee, Su-Min Choi, Hyo-Jin Kim, Wan-Soo Park, et al. "Lg = 50 nm Gate-All-Around In0.53Ga0.47As Nanosheet MOSFETs with Regrown In0.53Ga0.47As Contacts." Electronics 11, no. 17 (August 31, 2022): 2744. http://dx.doi.org/10.3390/electronics11172744.

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In this paper, we report the fabrication and characterization of Lg = 50 nm gate-all-around (GAA) In0.53Ga0.47As nanosheet (NS) metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-20 nm nanosheet thickness that were fabricated through an S/D regrowth process. The fabricated GAA In0.53Ga0.47As NS MOSFETs feature a bi-layer high-k dielectric layer of Al2O3/HfO2, together with an ALD-grown TiN metal-gate in a cross-coupled manner. The device with Lg = 50 nm, WNS = 200 nm and tNS = 10 nm exhibited an excellent combination of subthreshold-swing behavior (S < 80 mV/dec.) and carrier transport properties (gm_max = 1.86 mS/mm and ION = 0.4 mA/mm) at VDS = 0.5 V. To the best of our knowledge, this is the first demonstration of InxGa1-xAs GAA NS MOSFETs that would be directly applicable for their use in future multi-bridged channel (MBC) devices.

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Francis, P., A. Terao, D. Flandre, and F. Van de Wiele. "Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold." Microelectronic Engineering 19, no. 1-4 (September 1992): 815–18. http://dx.doi.org/10.1016/0167-9317(92)90551-2.

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Saravanan, M., Eswaran Parthasarathy, and K. Ramkumar. "Performance Analysis of InAs-GaAs Gate-all-around Tunnel Field Effect Transistors (GAA-TFET) for Analog/ RF applications." Journal of Physics: Conference Series 2335, no. 1 (September 1, 2022): 012043. http://dx.doi.org/10.1088/1742-6596/2335/1/012043.

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Abstract The purpose of this study to explore the performance of InAs-GaAs Gate-all-around (GAA) tunnelling field effect transistors (TFETs) in analogue and RF applications. The TCAD tool was used to assess the device’s overall performance. In order to achieve the InAs-GaAs channel design, the suggested TFET features a gate oxide made of SiO2 near the drain and HfO2 near the source region. As a result of the hetero dielectric gate oxide being used, the tunnelling width at junction between drain and channel (JDC) and junction between source and channel (JSC) is reduced, and the ON-current at the drain-channel junction is increased (ION). Device simulations have revealed that the SiO2-HfO2 gate dielectric has a low off-current (IOFF) of 2.27 x 10−17 A/m, a high enhanced ION of 7.39 x 10−6 A/m. At the time of operation, the sub-threshold swing (SS) was 16.8 mV/dec. Because of its low power consumption, the device could potentially be a better choice for power management circuits used in energy harvesting applications, according to the findings.

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Chen, Kun, Jingwen Yang, Tao Liu, Dawei Wang, Min Xu, Chunlei Wu, Chen Wang, Saisheng Xu, David Wei Zhang, and Wenchao Liu. "Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets." Micromachines 13, no. 7 (July 8, 2022): 1080. http://dx.doi.org/10.3390/mi13071080.

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A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology.

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Zhang, Qingzhu, Jie Gu, Renren Xu, Lei Cao, Junjie Li, Zhenhua Wu, Guilei Wang, et al. "Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices." Nanomaterials 11, no. 3 (March 5, 2021): 646. http://dx.doi.org/10.3390/nano11030646.

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In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

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Journal articles on the topic 'Gate-All-Around (GAA) Transistor'

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