Relevant bibliographies by topics / GATE EDGE ROUGHNESS

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'GATE EDGE ROUGHNESS'

Author: Grafiati
Published: 4 June 2021
Last updated: 19 February 2022

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Journal articles on the topic "GATE EDGE ROUGHNESS"

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Leunissen, Leonardus H. A., Rik Jonckheere, Kurt Ronse, and Giljam B. Derksen. "Influence of gate patterning on line edge roughness." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 21, no. 6 (2003): 3140. http://dx.doi.org/10.1116/1.1627799.

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Shuang, SUN, LI Ming, ZHANG Baotong, et al. "Analysis on Three‐Dimensional Gate Edge Roughness of Gate‐All‐Around Devices." Chinese Journal of Electronics 30, no. 5 (2021): 861–65. http://dx.doi.org/10.1049/cje.2021.06.008.

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Seoane, Natalia, Daniel Nagy, Guillermo Indalecio, Gabriel Espiñeira, Karol Kalna, and Antonio García-Loureiro. "A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs." Materials 12, no. 15 (2019): 2391. http://dx.doi.org/10.3390/ma12152391.

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An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 μA/μm, and an on-current (I ON) of 1770 μA/μm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from t
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Kim, Sang-Kon. "Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns." Journal of Nanoscience and Nanotechnology 20, no. 11 (2020): 6912–15. http://dx.doi.org/10.1166/jnn.2020.18814.

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The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm ar
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Espineira, G., D. Nagy, G. Indalecio, A. J. Garcia-Loureiro, K. Kalna, and N. Seoane. "Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET." IEEE Electron Device Letters 40, no. 4 (2019): 510–13. http://dx.doi.org/10.1109/led.2019.2900494.

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Dai, Liang, and Wei-Feng Lü. "Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (2020): 142–46. http://dx.doi.org/10.1166/jno.2020.2727.

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We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect t
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Xin Sun and Tsu-Jae King Liu. "Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness." IEEE Transactions on Semiconductor Manufacturing 23, no. 2 (2010): 311–15. http://dx.doi.org/10.1109/tsm.2010.2046050.

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Patel, Kedar, Tsu-Jae King Liu, and Costas J. Spanos. "Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability." IEEE Transactions on Electron Devices 56, no. 12 (2009): 3055–63. http://dx.doi.org/10.1109/ted.2009.2032605.

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Choi, Woo Young. "Influence of line-edge roughness on multiple-gate tunnel field-effect transistors." Japanese Journal of Applied Physics 56, no. 4S (2017): 04CD06. http://dx.doi.org/10.7567/jjap.56.04cd06.

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Asenov, A., S. Kaya, and A. R. Brown. "Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness." IEEE Transactions on Electron Devices 50, no. 5 (2003): 1254–60. http://dx.doi.org/10.1109/ted.2003.813457.

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Dissertations / Theses on the topic "GATE EDGE ROUGHNESS"

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Herrmann, Tom. "Simulation und Optimierung neuartiger SOI-MOSFETs." Doctoral thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-63173.

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Die vorliegende Arbeit beschreibt die Berechnung und Optimierung von Silicon-On-Insulator-Metal-Oxide-Semiconductor-Field-Effect-Transistors, einschließlich noch nicht in Massenproduktion hergestellter neuartiger Transistorarchitekturen für die nächsten Technologiegenerationen der hochleistungsfähigen Logik-MOSFETs mit Hilfe der Prozess- und Bauelementesimulation. Die neuartigen Transistorarchitekturen umfassen dabei vollständig verarmte SOI-MOSFETs, Doppel-Gate-Transistoren und FinFETs. Die statische und dynamische Leistungsfähigkeit der neuartigen Transistoren wird durch Simulation bestimmt
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Herrmann, Tom. "Simulation und Optimierung neuartiger SOI-MOSFETs." Doctoral thesis, 2009. https://monarch.qucosa.de/id/qucosa%3A19422.

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Die vorliegende Arbeit beschreibt die Berechnung und Optimierung von Silicon-On-Insulator-Metal-Oxide-Semiconductor-Field-Effect-Transistors, einschließlich noch nicht in Massenproduktion hergestellter neuartiger Transistorarchitekturen für die nächsten Technologiegenerationen der hochleistungsfähigen Logik-MOSFETs mit Hilfe der Prozess- und Bauelementesimulation. Die neuartigen Transistorarchitekturen umfassen dabei vollständig verarmte SOI-MOSFETs, Doppel-Gate-Transistoren und FinFETs. Die statische und dynamische Leistungsfähigkeit der neuartigen Transistoren wird durch Simulation bestimmt
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Conference papers on the topic "GATE EDGE ROUGHNESS"

1

Patel, Kedar, Tsu-Jae King Liu, and Costas Spanos. "Impact of gate line edge roughness on double-gate FinFET performance variability." In SPIE Advanced Lithography, edited by Vivek K. Singh and Michael L. Rieger. SPIE, 2008. http://dx.doi.org/10.1117/12.773065.

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Jiang, Xiaobo, Runsheng Wang, Ru Huang, and Jiang Chen. "Simulation of correlated line-edge roughness in multi-gate devices." In 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2013. http://dx.doi.org/10.1109/sispad.2013.6650590.

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Xiong, Shiying, Jeffrey Bokor, Qi Xiang, Philip Fisher, Ian M. Dudley, and Paula Rao. "Gate line-edge roughness effects in 50-nm bulk MOSFET devices." In SPIE's 27th Annual International Symposium on Microlithography, edited by Daniel J. C. Herr. SPIE, 2002. http://dx.doi.org/10.1117/12.473517.

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Kim, Seong-Dong, Sungkwon Hong, Jae-Kwan Park, and Jason C. S. Woo. "Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length." In 2002 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2002. http://dx.doi.org/10.7567/ssdm.2002.a-2-2.

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Sriram, S. R., and B. Bindu. "Study of Line Edge Roughness Induced Threshold Voltage Fluctuations in Double-Gate MOSFET." In 2018 15th IEEE India Council International Conference (INDICON). IEEE, 2018. http://dx.doi.org/10.1109/indicon45594.2018.8987069.

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Huang, Wen-Tsung, and Yiming Li. "The impact of fin/sidewall/gate line edge roughness on trapezoidal bulk FinFET devices." In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2014. http://dx.doi.org/10.1109/sispad.2014.6931618.

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Yu, Shimeng, Yuning Zhao, Yuncheng Song, et al. "Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs." In 2008 IEEE Silicon Nanoelectronics Workshop (SNW). IEEE, 2008. http://dx.doi.org/10.1109/snw.2008.5418481.

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Choi, Kang-Hoon, Rok Dittrich, Matthias Goldbach, et al. "Gate edge roughness in electron beam direct write and its influence to device characteristics." In SPIE Advanced Lithography, edited by Frank M. Schellenberg. SPIE, 2008. http://dx.doi.org/10.1117/12.772649.

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"Gate Line Edge Roughness Amplitude and Frequency Variation Effects on Intra Die MOS Device Characteristics." In 2005 International Semiconductor Device Research Symposium. IEEE, 2005. http://dx.doi.org/10.1109/isdrs.2005.1596140.

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Choi, W. Y., S. H. Choi, J. W. Lee, and I. Huh. "Influence of Line-Edge Roughness (LER) on Multiple-Gate (MG) Tunnel Field-Effect Transistors (TFETs)." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.ps-3-03.

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You might also be interested in the extended bibliographies on the topic 'GATE EDGE ROUGHNESS' for particular source types:
Journal articles
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