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Journal articles on the topic 'GATE EDGE ROUGHNESS'

Author: Grafiati

Published: 4 June 2021

Last updated: 19 February 2022

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1

Leunissen, Leonardus H. A., Rik Jonckheere, Kurt Ronse, and Giljam B. Derksen. "Influence of gate patterning on line edge roughness." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 21, no. 6 (2003): 3140. http://dx.doi.org/10.1116/1.1627799.

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2

Shuang, SUN, LI Ming, ZHANG Baotong, et al. "Analysis on Three‐Dimensional Gate Edge Roughness of Gate‐All‐Around Devices." Chinese Journal of Electronics 30, no. 5 (2021): 861–65. http://dx.doi.org/10.1049/cje.2021.06.008.

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3

Seoane, Natalia, Daniel Nagy, Guillermo Indalecio, Gabriel Espiñeira, Karol Kalna, and Antonio García-Loureiro. "A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs." Materials 12, no. 15 (2019): 2391. http://dx.doi.org/10.3390/ma12152391.

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An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 μA/μm, and an on-current (I ON) of 1770 μA/μm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from t

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4

Kim, Sang-Kon. "Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns." Journal of Nanoscience and Nanotechnology 20, no. 11 (2020): 6912–15. http://dx.doi.org/10.1166/jnn.2020.18814.

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The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm ar

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5

Espineira, G., D. Nagy, G. Indalecio, A. J. Garcia-Loureiro, K. Kalna, and N. Seoane. "Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET." IEEE Electron Device Letters 40, no. 4 (2019): 510–13. http://dx.doi.org/10.1109/led.2019.2900494.

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6

Dai, Liang, and Wei-Feng Lü. "Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (2020): 142–46. http://dx.doi.org/10.1166/jno.2020.2727.

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We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect t

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7

Xin Sun and Tsu-Jae King Liu. "Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness." IEEE Transactions on Semiconductor Manufacturing 23, no. 2 (2010): 311–15. http://dx.doi.org/10.1109/tsm.2010.2046050.

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8

Patel, Kedar, Tsu-Jae King Liu, and Costas J. Spanos. "Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability." IEEE Transactions on Electron Devices 56, no. 12 (2009): 3055–63. http://dx.doi.org/10.1109/ted.2009.2032605.

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9

Choi, Woo Young. "Influence of line-edge roughness on multiple-gate tunnel field-effect transistors." Japanese Journal of Applied Physics 56, no. 4S (2017): 04CD06. http://dx.doi.org/10.7567/jjap.56.04cd06.

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10

Asenov, A., S. Kaya, and A. R. Brown. "Intrinsic parameter fluctuations in decananometer mosfets introduced by gate line edge roughness." IEEE Transactions on Electron Devices 50, no. 5 (2003): 1254–60. http://dx.doi.org/10.1109/ted.2003.813457.

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11

Yu, Shimeng, Yuning Zhao, Lang Zeng, et al. "Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors." IEEE Transactions on Electron Devices 56, no. 6 (2009): 1211–19. http://dx.doi.org/10.1109/ted.2009.2017644.

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12

Yu, Tao, Runsheng Wang, Ru Huang, Jiang Chen, Jing Zhuge, and Yangyuan Wang. "Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs." IEEE Transactions on Electron Devices 57, no. 11 (2010): 2864–71. http://dx.doi.org/10.1109/ted.2010.2065808.

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13

Yang, Yunxiang, Shimeng Yu, Lang Zeng, et al. "Variability Induced by Line Edge Roughness in Double-Gate Dopant-Segregated Schottky MOSFETs." IEEE Transactions on Nanotechnology 10, no. 2 (2011): 244–49. http://dx.doi.org/10.1109/tnano.2009.2037222.

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14

Seoane, Natalia, Guillermo Indalecio, Enrique Comesana, Manuel Aldegunde, Antonio J. Garcia-Loureiro, and Karol Kalna. "Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET." IEEE Transactions on Electron Devices 61, no. 2 (2014): 466–72. http://dx.doi.org/10.1109/ted.2013.2294213.

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15

Hamadeh, Emad, Norman G. Gunther, Darrell Niemann, and Mahmud Rahman. "Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics." Solid-State Electronics 50, no. 6 (2006): 1156–63. http://dx.doi.org/10.1016/j.sse.2006.04.031.

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16

Diaz, C. H., Hun-Jan Tao, Yao-Ching Ku, A. Yen, and K. Young. "An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling." IEEE Electron Device Letters 22, no. 6 (2001): 287–89. http://dx.doi.org/10.1109/55.924844.

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17

Min, Jinhong, and Changhwan Shin. "Study of line edge roughness on various types of gate-all-around field effect transistor." Semiconductor Science and Technology 35, no. 1 (2019): 015004. http://dx.doi.org/10.1088/1361-6641/ab52e4.

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18

Ono, S., M. Yamane, A. Katakami, et al. "Three-Dimensional Observation of Edge-Roughness on Poly-Si/TiN Stacked Gate Using Three-Dimensional STEM." Microscopy and Microanalysis 15, S2 (2009): 634–35. http://dx.doi.org/10.1017/s1431927609092976.

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19

Fouchier, Marc, and Erwine Pargon. "Atomic force microscopy study of photoresist sidewall smoothing and line edge roughness transfer during gate patterning." Journal of Micro/Nanolithography, MEMS, and MOEMS 12, no. 4 (2013): 041308. http://dx.doi.org/10.1117/1.jmm.12.4.041308.

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20

Son, Dokyun, Kyul Ko, Changbeom Woo, Myounggon Kang, and Hyungcheol Shin. "Characteristics According to Parameters of Line Edge Roughness in Ultra-Scaled Gate-All-Around Nanowire FET." Journal of Nanoscience and Nanotechnology 17, no. 10 (2017): 7179–82. http://dx.doi.org/10.1166/jnn.2017.14719.

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21

Son, Dokyun, Kyul Ko, Changbeom Woo, Myounggon Kang, and Hyungcheol Shin. "Line Edge Roughness and Process Variation Effect of Three Stacked Gate-All-Around Silicon MOSFET Devices." Journal of Nanoscience and Nanotechnology 17, no. 10 (2017): 7130–33. http://dx.doi.org/10.1166/jnn.2017.14755.

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22

Thiault, J., J. Foucher, J. H. Tortai, O. Joubert, S. Landis, and S. Pauliac. "Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 23, no. 6 (2005): 3075. http://dx.doi.org/10.1116/1.2101789.

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23

Park, In Jun, and Changhwan Shin. "Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs." IEICE Electronics Express 10, no. 5 (2013): 20130108. http://dx.doi.org/10.1587/elex.10.20130108.

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24

Xiong, S., and J. Bokor. "A Simulation Study of Gate Line Edge Roughness Effects on Doping Profiles of Short-Channel MOSFET Devices." IEEE Transactions on Electron Devices 51, no. 2 (2004): 228–32. http://dx.doi.org/10.1109/ted.2003.821563.

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25

Fukutome, H., Y. Momiyama, T. Kubo, Y. Tagawa, T. Aoyama, and H. Arimoto. "Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs." IEEE Transactions on Electron Devices 53, no. 11 (2006): 2755–63. http://dx.doi.org/10.1109/ted.2006.882784.

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26

Lee, Jaehyun, Oves Badami, Hamilton Carrillo-Nuñez, et al. "Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs." Micromachines 9, no. 12 (2018): 643. http://dx.doi.org/10.3390/mi9120643.

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Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on Si x Ge 1 − x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from s p 3 d 5 s ∗ tight-binding band structures. In

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27

Liu, Keng-Ming, and Li-Syun Yang. "Investigation on Fin and Gate Line Edge Roughness Effects for Sub-22 nm Inversion- Mode and Junctionless FinFETs." International Journal of Engineering Trends and Technology 40, no. 2 (2016): 72–76. http://dx.doi.org/10.14445/22315381/ijett-v40p212.

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28

Damrongplasit, Nattapol, Sung Hwan Kim, Changhwan Shin, and Tsu-Jae King Liu. "Impact of Gate Line-Edge Roughness (LER) Versus Random Dopant Fluctuations (RDF) on Germanium-Source Tunnel FET Performance." IEEE Transactions on Nanotechnology 12, no. 6 (2013): 1061–67. http://dx.doi.org/10.1109/tnano.2013.2278153.

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29

Tilak, Vinayak, Kevin Matocha, and Greg Dunne. "Comparison of Inversion Layer Electron Transport of Lightly Doped 4H and 6H SiC MOSFETs." Materials Science Forum 645-648 (April 2010): 1005–8. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1005.

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nversion layers of 4H and 6H Silicon carbide based MOS devices are characterized by Gated Hall measurements to determine the trap density close to the conduction band edge and the main scattering mechanisms that limit the mobility. MOS gated Hall structures were fabricated on 4H SiC polytype with p-type doping of 5X1015cm-3 and 2X1017cm-3. MOS Gated Hall structures were also fabricated on 6H SiC polytype with p-type doping of 7.5X1015cm-3. The gate oxide was grown thermally with N2O as a precursor followed by a NO post oxidation anneal. The inversion layer Hall mobility on the 6H SiC MOSFET sa

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30

Yu, Shimeng, Yuning Zhao, Gang Du, Jinfeng Kang, Ruqi Han, and Xiaoyan Liu. "Triple-Gate Fin Field Effect Transistors with Fin-Thickness Optimization to Reduce the Impact of Fin Line Edge Roughness." Japanese Journal of Applied Physics 48, no. 4 (2009): 04C052. http://dx.doi.org/10.1143/jjap.48.04c052.

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31

Sudarsanan, Akhil, Sankatali Venkateswarlu, and Kaushik Nayak. "Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET." IEEE Transactions on Electron Devices 66, no. 11 (2019): 4646–52. http://dx.doi.org/10.1109/ted.2019.2941896.

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32

Kim, S. D., H. Wada, and J. C. S. Woo. "TCAD-Based Statistical Analysis and Modeling of Gate Line-Edge Roughness Effect on Nanoscale MOS Transistor Performance and Scaling." IEEE Transactions on Semiconductor Manufacturing 17, no. 2 (2004): 192–200. http://dx.doi.org/10.1109/tsm.2004.826935.

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33

Son, Dokyun, Kyul Ko, Myounggon Kang, and Hyungcheol Shin. "3D Technology Computer-Aided Design-Based Optimization of Channel Radius Considering Line Edge Roughness on Gate-All-Around Nanowire FET." Journal of Nanoscience and Nanotechnology 17, no. 5 (2017): 3060–64. http://dx.doi.org/10.1166/jnn.2017.14032.

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34

Xiong, S., J. Bokor, Q. Xiang, et al. "Is Gate Line Edge Roughness a First-Order Issue in Affecting the Performance of Deep Sub-Micro Bulk MOSFET Devices?" IEEE Transactions on Semiconductor Manufacturing 17, no. 3 (2004): 357–61. http://dx.doi.org/10.1109/tsm.2004.831560.

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35

SAIFULLAH, M. S. M. "SUB-10 NM DIRECT PATTERNING OF OXIDES USING AN ELECTRON BEAM — A REVIEW." COSMOS 05, no. 01 (2009): 1–21. http://dx.doi.org/10.1142/s0219607709000403.

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This article reviews the progress made in the sub-10 nm electron beam patterning of metal oxides over the last thirty years. The patterning of inorganic resists began with metal halides, they were soon taken over by metal oxides due to their excellent environmental stability. However, these inorganic materials, both halides and oxides, suffered from the requirement of very steep dose, thus rendering them useless for practical applications. This gave way to highly electron beam-sensitive stabilized metal alkoxides and metal naphthenates, with sensitively close to conventional electron beam resi

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36

Park, In Jun, and Changhwan Shin. "Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs." JSTS:Journal of Semiconductor Technology and Science 13, no. 5 (2013): 511–15. http://dx.doi.org/10.5573/jsts.2013.13.5.511.

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37

Meško, J., R. Nigrovič, and A. Zrak. "The Influence of Different Assist Gases on Ductile Cast Iron Cutting by CO2 Laser." Archives of Foundry Engineering 17, no. 4 (2017): 109–14. http://dx.doi.org/10.1515/afe-2017-0139.

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Abstract This article deals with the technology and principles of the laser cutting of ductile cast iron. The properties of the CO2 laser beam, input parameters of the laser cutting, assist gases, the interaction of cut material and the stability of cutting process are described. The commonly used material (nodular cast iron - share of about 25% of all castings on the market) and the method of the laser cutting of that material, including the technological parameters that influence the cutting edge, are characterized. Next, the application and use of this method in mechanical engineering pract

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38

Nilsson, S., I. Berglund, U. Erikson, J. Johansson, and G. Walldius. "Optimization of ecg gating in quantitative femoral angiography." Acta Radiologica 44, no. 5 (2003): 489–93. http://dx.doi.org/10.1080/j.1600-0455.2003.00101.x.

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Purpose: To determine which phase of the heart cycle would yield the highest reproducibility in measuring atherosclerosis-related variables such as arterial lumen volume and edge roughness. Material and Methods: 35 patients with hypercholesterolemia underwent select‐ ive femoral angiography, repeated four times at 10-min intervals. The angiographies were performed with ECG-gated exposures. In angiographies 1 and 2 the delay from R-wave maximum to each exposure was 0.1 s, in angiographies 3 and 4 the delay was 0.1, 0.3, 0.5 or 0.7 s or the exposures were performed 1/s without ECG gating. Arteri

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39

Tilak, Vinayak, Kevin Matocha, and Greg Dunne. "Interface Trap Density and Mobility Characterization of Silicon Carbide MOSFET Inversion Layers." Materials Science Forum 615-617 (March 2009): 801–4. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.801.

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Silicon Carbide (SiC) based metal oxide semiconductor field effect transistors (MOSFETs) were fabricated and characterized using gated hall measurements with different p-type substrate doping concentration (7.2X1016cm-3 and 2X1017 cm-3). An interface trap state density of 5X1013 cm-2eV-1 was observed nearly 0.1 eV above the conduction band edge leading to the conclusion that these states are present in the silicon dioxide rather than the interface. The Hall mobility of the MOSFETs decreased from 26.5 to 20 cm2/Vs as the doping was increased from 7.2X1016 to 2X1017cm-3. The decrease in mobility

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40

Akbulut, Mustafa B., Helena Silva, and Ali Gokirmak. "Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors." MRS Proceedings 1510 (2013). http://dx.doi.org/10.1557/opl.2013.529.

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ABSTRACTAccumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.

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41

Sidhu, Ramneek, and Mayank Kumar Rai. "Edge scattering limited crosstalk analysis in adjacent multilayer graphene interconnects and its impact on gate oxide reliability." Circuit World ahead-of-print, ahead-of-print (2021). http://dx.doi.org/10.1108/cw-09-2020-0233.

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Purpose This paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied. Design/methodology/approach An equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are

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42

Kim, Yonghyun, Chang Yong Kang, Se-Hoon Lee, et al. "Role of Boron TED and Series Resistance in SiGe/Si Heterojunction pMOSFETs." MRS Proceedings 1155 (2009). http://dx.doi.org/10.1557/proc-1155-c02-05.

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AbstractWe investigate boron transient enhanced diffusion (TED) and series resistance in SiGe/Si heterojunction channel pMOSFET. The stress gradient at the SiGe/Si interface near the gate edge in high Ge concentrations are found to determine boron TED as well as extension junction shape, which has a significant impact on the parasitic LDD and source/drain (S/D) series resistance. In addition, high Ge concentrations in the epitaxial SiGe layer on top of Si substrate result in a high sheet resistance during a 1000°C/5s rapid thermal processing (RTP), which is mainly due to alloy scattering and i

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