Relevant bibliographies by topics / Gate induced drain lowering

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Gate induced drain lowering'

Author: Grafiati
Published: 4 June 2025
Last updated: 1 August 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Gate induced drain lowering.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Gate induced drain lowering"

1

Kim, Young, Jin Lee, Geon Kim, et al. "Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors." Electronics 8, no. 1 (2018): 8. http://dx.doi.org/10.3390/electronics8010008.

Full text
Abstract:
In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower Ioff than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing Ion reduction compared to RFinFET. Our results also confirmed that th
APA, Harvard, Vancouver, ISO, and other styles
2

Peng, Zehui, Huangbai Liu, Hao Yu, Lei Li, and Kuan-Chang Chang. "Constructing drain surrounded double gate structure in AlGaN/GaN HEMT for boosting breakdown voltage." RSC Advances 14, no. 31 (2024): 22238–43. http://dx.doi.org/10.1039/d4ra03508a.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Abdoul, Rjoub, Al-Mistarihi Mamoun, and Al Taradeh Nedal. "Accurate leakage current models for MOSFET nanoscale devices." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2313–21. https://doi.org/10.11591/ijece.v10i3.pp2313-2321.

Full text
Abstract:
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) was investigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate
APA, Harvard, Vancouver, ISO, and other styles
4

ROY, KAUSHIK, SAIBAL MUKHOPADHYAY, and HAMID MAHMOODI-MEIMAND. "LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS." Journal of Circuits, Systems and Computers 11, no. 06 (2002): 575–600. http://dx.doi.org/10.1142/s021812660200063x.

Full text
Abstract:
The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.
APA, Harvard, Vancouver, ISO, and other styles
5

Hakkee Jung. "Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric." International Journal of Engineering and Technology Innovation 14, no. 2 (2024): 189–200. http://dx.doi.org/10.46604/ijeti.2023.12887.

Full text
Abstract:
This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gate-all-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metal-insulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an
APA, Harvard, Vancouver, ISO, and other styles
6

Zhu, C. L., E. Rusli, J. Almira, Chin Che Tin, S. F. Yoon, and J. Ahn. "Physical Simulation of Drain-Induced Barrier Lowering Effect in SiC MESFETs." Materials Science Forum 483-485 (May 2005): 849–52. http://dx.doi.org/10.4028/www.scientific.net/msf.483-485.849.

Full text
Abstract:
The drain-induced barrier lowering (DIBL) effect in 4H-SiC MESFETs has been studied using the physical drift and diffusion model. Our simulation results showed that the high drain voltage typically applied in short-channel 4H-SiC MESFETs could substantially reduce the channel barrier and result in large threshold voltage shift. It is also found that the DIBL effect is more dependent on the ratio of the gate length to channel thickness (Lg/a), rather than the channel thickness itself. In order to minimize the DIBL effect, the ratio of Lg/a should be kept greater than 3 for practical 4H-SiC MESF
APA, Harvard, Vancouver, ISO, and other styles
7

Jagtap, Sarika Madhukar, and Vitthal Janardan Gond. "Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics." International Journal of Natural Computing Research 10, no. 3 (2021): 12–28. http://dx.doi.org/10.4018/ijncr.2021070102.

Full text
Abstract:
The scrambling of MOSFET below 22nm, 14nm, unwanted Short Channel Effects (SCE) like punch through, drain-induced barrier lowering (DIBL), along with huge leakage current are flowing through the device, which is not recognized for better performance. Multi-gate MOSFET generally measured as Fin-FET is the best substitute vital to stunned short channel effects. The work highlights results of the current-voltage electrical characteristics of the n-channel triple gate Fin-FET gatherings. The paper focuses on the study of geometry-based device design of Fin-FET by changing high k dielectrics materi
APA, Harvard, Vancouver, ISO, and other styles
8

Jung, Hakkee. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 232. http://dx.doi.org/10.11591/ijece.v11i1.pp232-239.

Full text
Abstract:
The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtain
APA, Harvard, Vancouver, ISO, and other styles
9

Hakkee, Jung. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 232–39. https://doi.org/10.11591/ijece.v11i1.pp232-239.

Full text
Abstract:
The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L)×10 -7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is o
APA, Harvard, Vancouver, ISO, and other styles
10

HAVALDAR, DNAYNESH S., AMITAVA DASGUPTA, and NANDITA DASGUPTA. "STUDY OF DUAL-MATERIAL GATE (DMG) FinFET USING THREE-DIMENSIONAL NUMERICAL SIMULATION." International Journal of Nanoscience 05, no. 04n05 (2006): 541–45. http://dx.doi.org/10.1142/s0219581x06004760.

Full text
Abstract:
In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and leng
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Gate induced drain lowering"

1

Lin, Hao-Hsun, and 林浩勳. "Modeling of Gate-Induced Drain Leakage Currents of MOSFETs." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/67665048667196830973.

Full text
Abstract:
碩士<br>國立臺灣科技大學<br>電子工程系<br>87<br>In this thesis we present compact drain leakage current models for submicron surface-channel nMOSFETs, buried-channel MOSFETs and silicon-on-insulator pMOSFETs. The analytical and physics-based models were developed using a quasi-two dimensional approach, in which the longitudinal and vertical surface channel electric fields can be calculated. The effective gate-overlap drain region for band-to-band tunneling drain leakage current can be calculated, and it is a function of gate and drain biases. The drain leakage current can be accurately calculated
APA, Harvard, Vancouver, ISO, and other styles
2

Kuo, Pei-Chen, and 郭珮甄. "Statistical Variability of Line Edge Roughness Induced Drain- Induced Barrier Lowering Shift in Nanoscale FinFETs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/n2wm8n.

Full text
Abstract:
碩士<br>國立交通大學<br>電子研究所<br>107<br>The fin edge roughness in fin field-effect transistor (FinFET) is one of the important topics in semiconductor manufacturing, concerning the threshold voltage and drain-induced barrier lowering variation, device reliability and yield rate. In this work, through the help of modern 3-D technology computer aided design (TCAD) software, we can pay attention to the impact of fin edge roughness in devices, decouple other variability sources while manufacturing processes. Also, we can perform simulation tasks with different structure and process. In this simulation wor
APA, Harvard, Vancouver, ISO, and other styles
3

Kun, Huang Tao, and 黃道坤. "The impact of poly gate sidewall oxide thickness on MOSFET’s gate-induced drain leakage behavior." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/12981841264445016012.

Full text
Abstract:
碩士<br>長庚大學<br>電子工程研究所<br>93<br>The leakage in the drain region is a crucial issue for scaling of the MOSFET. The off-state gate-induced drain leakage (GIDL) current is one of the major contributors to the overall MOSFET leakage. GIDL is induced by band-to-band tunneling (BTBT) effect in the depletion region and generated in the gate to drain overlap region with high electric field. GIDL leakage is a function of many process parameters such as spacer material, spacer width, gate oxide thickness, doped concentration; anneal temperature, and poly re-oxidation conditions etc. Devices used in this
APA, Harvard, Vancouver, ISO, and other styles
4

Lee, E.-Long, and 李一龍. "Charaterization and Modeling of Gate-Induced Drain Leakage Current in Thin Oxide MOSFET." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/76517656074810341258.

Full text
Abstract:
碩士<br>國立交通大學<br>電子研究所<br>81<br>Recent developments in MOS technologies, have led to an increase in electric field strength in the gate-to-drain overlap region. Therefore, the gate-induced drain leakage current (GIDL) by the gate-induced surface electric field will dominate the drain leakage in off-state thin oxide MOSFETs. In this thesis we present a new way for eliminating the uncertainties in modeling the GIDL current in p-MOSFET's by simultaneously accoun
APA, Harvard, Vancouver, ISO, and other styles
5

Liao, Chiang-Ting, and 廖姜婷. "Natural Length Based Predictive TCAD for the Subthreshold Swing and Drain-Induced Barrier Lowering in Bulk FinFETs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/52019736117709425994.

Full text
Abstract:
碩士<br>國立交通大學<br>電子研究所<br>105<br>In order to keep pace with the Moore’s Law, suppressing short-channel effects through novel multiple gate geometry architectures of device is a practical solution to make shrinking possible. To accurately predict the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) of multi-gate FETs, we employ a commercial TCAD code on the industrial bulk FinFETs. The TCAD calibration task is well done via a natural length and its experimentally determined correction coefficient. This predictive TCAD enables the optimization of multi-gate FETs with suppressed S
APA, Harvard, Vancouver, ISO, and other styles
6

Sahay, Shubham. "Design and analysis of emerging nanoscale junctionless fets from gate-induced drain leakage perspective." Thesis, 2018. http://localhost:8080/xmlui/handle/12345678/7579.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Tsai, Yu-Shiuan, and 蔡宇宣. "Application of Natural Length Model for Subthreshold Swing and Drain-Induced Barrier Lowering in Nanoscale Bulk FinFETs through TCAD Simulation." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/aqd77a.

Full text
Abstract:
碩士<br>國立交通大學<br>電子研究所<br>106<br>While the devices are pushed to nanoscale, how to overcome the short channel effect is a great challenge, therefore, different multiple-gate geometry architectures of devices have been proposed. Except for the variations of the metal gate granularity, line edge roughness and random dopants fluctuation, the subthreshold swing and drain-induced barrier lowering are prime and direct representative of device. As a result, through the bulk FinFETs simulation with different dimensions and the theoretical formulas with natural length, the two characters can be effectiv
APA, Harvard, Vancouver, ISO, and other styles
8

Chen, Ja-Hao, and 陳家豪. "Study of 2D Analysis Gate-Induced Drain Leakage (GIDL) Model and DC pulse Hot-Carrier Effect on GIDL of nMOSFETs." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/59jjyg.

Full text
Abstract:
博士<br>國立成功大學<br>電機工程學系碩博士班<br>90<br>The gate-induced drain leakage current model and the leakage degradation induced by DC pulse hot-carrier effect have been studied. First, an analytic three-terminal band-to-band tunneling current model for the gate-induced drain leakage current (GIDL) in an n-MOSFET is developed. This model considers impurity doping concentration, vertical field, lateral field and so-induced electron momentum enhancement, as well as the surface electrostatic potential in the gate-to-drain overlapped region. Based on a constant surface-potential approximation, a closed-form e
APA, Harvard, Vancouver, ISO, and other styles
9

Liao, Jing-chyi, and 廖竟淇. "Investigations of Gate Induced Drain Leakage (GIDL) and Bias Temperature Instability (BTI) on LTPS TFTs and Hf-based High-k CMOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/70836009323483888143.

Full text
Abstract:
博士<br>國立成功大學<br>微電子工程研究所碩博士班<br>97<br>In this thesis, the trapping characteristics of positive bias temperature instability (PBTI) on a high-k/metal gate n-type metal oxide semiconductor field effect transistor (nMOSFET) have been firstly investigated with a complementary multi-pulse technique (CMPT) in detail. With the CMPT technique, we find that the threshold voltage shifts after PBTI are higher than that with the conventional direct current method, and the thickness of the SiO2 interfacial layer has a significant effect on the measured results. The observation of these new results is attri
APA, Harvard, Vancouver, ISO, and other styles
10

Tsai, Kai-Shiang, and 蔡凱翔. "Embedded SiGe Source/Drain Induced-Compressive Strain on Low Frequency Noise in 28nm High-K/Metal Gate P-Channel Metal-Oxide-Semiconductor Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/94482419693221028385.

Full text
Abstract:
碩士<br>正修科技大學<br>電子工程研究所<br>102<br>In this work, introduction of a SiGe material into source/drain (S/D) regions provides uniaxial compressive strain on low frequency noise (LFN) in high-k/metal gate (HK/MG) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFET). We use high dielectric constant material (hafnium oxide ,HfO2) and titanium nitride (TiN) material in barrier layer and metal gate (MG) electrodes to produced P-type metal oxide semiconductor field effect transistor. The introduction of a SiGe material into source/drain (S/D) regions provides uniaxial compressive strain
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Gate induced drain lowering"

1

Cham, Kit Man, Soo-Young Oh, Daeje Chin, and John L. Moll. "Drain-Induced Barrier Lowering In Short Channel Transistors." In Computer-Aided Design and VLSI Device Development. Springer US, 1986. http://dx.doi.org/10.1007/978-1-4613-2553-6_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Cham, Kit Man, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, and Daeje Chin. "Drain-Induced Barrier Lowering in Short Channel Transistors." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1988. http://dx.doi.org/10.1007/978-1-4613-1695-4_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Zhu, C. L., E. Rusli, J. Almira, Chin Che Tin, S. F. Yoon, and J. Ahn. "Physical Simulation of Drain-Induced Barrier Lowering Effect in SiC MESFETs." In Materials Science Forum. Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-963-6.849.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Amirtha, Varshini K., and Shubham Sahay. "Impact of High-k Dielectric on the Gate-Induced Drain Leakage of Multi-Gate FETs." In High-k Materials in Multi-Gate FET Devices. CRC Press, 2021. http://dx.doi.org/10.1201/9781003121589-5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Roy, Krishnendu, Anal Roy Chowdhury, and Arpan Deyasi. "Computation of Gate-Induced-Drain-Leakage Current Due to Band-to-Band Tunneling for Ultrathin MOSFET." In Lecture Notes in Networks and Systems. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9453-0_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Malavena, Gerardo. "Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks." In Special Topics in Information Technology. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_4.

Full text
Abstract:
AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenome
APA, Harvard, Vancouver, ISO, and other styles
7

Kandpal, Jyoti, and Ekta Goel. "Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS." In Nanoscale Field Effect Transistors: Emerging Applications. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815165647123010005.

Full text
Abstract:
Low-power application devices and inexpensive transistors are essential for today's technological world. A 3 nm MOSFET nanoelectronic device has just been created by researchers. Even though a MOSFET shrinks in size and uses less power, SCEs still cause a few problems, leakage current, including Hot electron, Impact Ionization, threshold voltage roll-off, Drain Induced Barrier Lowering (DIBL), and others. One of the best-proposed structures to replace the MOSFET structure is the FIN FET structure, which overcomes the limitations brought on by the CMOS transistor. For low-power applications, th
APA, Harvard, Vancouver, ISO, and other styles
8

Shah, Raj, and Rasika Dhavse. "CMOS Compatible Single-Gate Single Electron Transistor (SG-SET) Based Hybrid SETMOS Logic." In Nanoscale Field Effect Transistors: Emerging Applications. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815165647123010010.

Full text
Abstract:
The continuous development of CMOS technology today beyond many obstacles has been witnessed by all of us. After three decades of aggressive scaling to ever-smaller dimensions, today, MOSFET gate lengths can be less than 22 nm. There are many challenges and limitations at the device level. Short channel effects, such as drain induced barrier lowering, Vth roll-off, gate induced drain leakage, static leakage, punch through, and contact resistance, are among the major blockades for sub-22 nm technology. Many physicists have explored this extremely small dimension device and the effects of charge
APA, Harvard, Vancouver, ISO, and other styles
9

"Gate-Induced Drain Leakage in Junctionless Field-Effect Transistors." In Junctionless Field-Effect Transistors. Wiley, 2019. http://dx.doi.org/10.1002/9781119523543.ch5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

"Stress-induced degradation and lifetime estimation in commercial power VDMOS transistors." In Book of Abstracts - RAD 2025 Conference. RAD Centre, Niš, Serbia, 2025. https://doi.org/10.21175/rad.abstr.book.2025.9.6.

Full text
Abstract:
In this study commercial power VDMOS (Vertical Double Diffused MOS) transistors subjected to different stress conditions were investigated. Power VDMOS transistors are a type of power MOSFET designed for high-current and high-voltage applications. As shown in the technical documentation of the manufacturers, p-channel devices are usually designed to withstand currents of up to 6.8 A and drain-source voltages of – 100 V. Similar situation is for the n-channel devices, they exhibit comparable characteristics, with maximum current ratings of about 5.6 A and drain-source voltages of +100 V. These
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Gate induced drain lowering"

1

Ding, Hongbo, Jared Pannell, and Dirk van Oostendorp. "Stray Current Induced Localized Corrosion of Stainless-Steel Plates in a Tainter Gate System." In CORROSION 2021. AMPP, 2021. https://doi.org/10.5006/c2021-16238.

Full text
Abstract:
Abstract Abnormal localized corrosion of stainless steel 304 components in a Tainter gate system was observed in a low-chloride natural water environment. Through calculations, field observations and measurements, the direct cause was attributed to the combined effect of local crevice geometry and stray current interference that is induced by an adjacent foreign cathodic protection system. Based on the direct cause and the field test, mitigation strategies were proposed. It is understood that by reducing the level of stray current interference, the local potential of the stainless steel (SS) c
APA, Harvard, Vancouver, ISO, and other styles
2

Wang, Chen, Xin Wang, Junjie Yang, et al. "Deeply Scaled Gate Field Plate to Suppress Drain-Induced Dynamic Threshold Voltage Instability in Schottky-Type p-GaN Gate HEMT." In 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2025. https://doi.org/10.1109/edtm61175.2025.11041314.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

del Castillo, Alex Marionne, Alfred Jay Rafael, Jolina May Matibag, Jae Saladar, Robin Evangelista, and Raymond Mendaros. "Effective FA Approach in Uncovering Gate-to-D/S Tungsten Spur Fabrication Defect." In ISTFA 2024. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0427.

Full text
Abstract:
Abstract A series of power supply line controller failures at Analog Devices Incorporated (ADI) exhibited abnormal output voltage and quiescent current symptoms. Our failure analysis revealed a gate-to-drain/source tungsten spur defect, which required a sophisticated multi-step detection process. The investigation combined several advanced techniques: light emission microscopy (LEM) and optical beam induced resistance change (OBIRCH) identified the failing circuit, passive voltage contrast (PVC) located the affected transistor, and nanoprobing with electron beam induced resistance change (EBIR
APA, Harvard, Vancouver, ISO, and other styles
4

Chen, Wei-Chen, Hang-Ting Lue, Ming-Hung Wu, et al. "A Multi-WL Approach to Suppress Gate-Induced Drain Leakage, Floating Body Effect, and Row Hammer Effect in Array Transistor of 4F2 DRAM and 3D Stackable DRAM." In 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024. https://doi.org/10.1109/iedm50854.2024.10873338.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Hu, Guangxi, Shuyan Hu, Jianhua Feng, Ran Liu, Lingli Wang, and Lirong Zheng. "Analytical models for threshold voltage, drain induced barrier lowering effect of junctionless triple-gate FinFETs." In 2015 IEEE 11th International Conference on ASIC (ASICON ). IEEE, 2015. http://dx.doi.org/10.1109/asicon.2015.7517154.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Sato, T., K. Uryu, J. Okayasu, M. Kimishima, and T. Suzuki. "Drain-induced barrier lowering in normally-off AlGaN-GaN MOSFETs with single- or double-recess overlapped gate." In 2017 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2017. http://dx.doi.org/10.7567/ssdm.2017.n-3-05.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Su, Hsin-Wen, Yiming Li, Yu-Yu Chen, Chieh-Yang Chen, and Han-Tung Chang. "Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants." In 2012 70th Annual Device Research Conference (DRC). IEEE, 2012. http://dx.doi.org/10.1109/drc.2012.6256976.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Goh, W. Z., B. Fong, H. Hussin, and S. F. Wan Muhamad Hatta. "Study of Scaling Limits of Multi-Gate Fets (Finfet) With High-K Dielectric." In International Technical Postgraduate Conference 2022. AIJR Publisher, 2022. http://dx.doi.org/10.21467/proceedings.141.18.

Full text
Abstract:
Scaling of Multi-Gate FETs (FinFETs) to sub nanometer has seen several challenging problems such as short channel effects which significantly affect the device performance and huge off-state power leakage. High-k dielectric materials had always been looked at as a potential replacement to the conventional SiO2 to increase gate control over the channel which could be a possible solution. This paper examines the impact of scaling FinFETs with varying geometric conditions in the presence of high-k gate dielectrics oxide layer, and further demonstrate conflicting technical trade-off that emerges f
APA, Harvard, Vancouver, ISO, and other styles
9

Lamba, V. K., Derick Engles, and S. S. Malik. "Modeling and Designing a Device Using MuGFETs." In ASME 2008 3rd Energy Nanotechnology International Conference collocated with the Heat Transfer, Fluids Engineering, and Energy Sustainability Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/enic2008-53015.

Full text
Abstract:
This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studi
APA, Harvard, Vancouver, ISO, and other styles
10

Matsukawa, T., K. Fukuda, Y. X. Liu, et al. "Fluctuation in drain induced barrier lowering (DIBL) for FinFETs caused by granular work function variation of metal gates." In 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-tsa.2014.6839648.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Gate induced drain lowering' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography