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Journal articles on the topic 'Gate induced drain lowering'

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Published: 4 June 2025

Last updated: 1 August 2025

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1

Kim, Young, Jin Lee, Geon Kim, et al. "Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors." Electronics 8, no. 1 (2018): 8. http://dx.doi.org/10.3390/electronics8010008.

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In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower Ioff than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing Ion reduction compared to RFinFET. Our results also confirmed that th

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2

Peng, Zehui, Huangbai Liu, Hao Yu, Lei Li, and Kuan-Chang Chang. "Constructing drain surrounded double gate structure in AlGaN/GaN HEMT for boosting breakdown voltage." RSC Advances 14, no. 31 (2024): 22238–43. http://dx.doi.org/10.1039/d4ra03508a.

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3

Abdoul, Rjoub, Al-Mistarihi Mamoun, and Al Taradeh Nedal. "Accurate leakage current models for MOSFET nanoscale devices." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2313–21. https://doi.org/10.11591/ijece.v10i3.pp2313-2321.

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This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) was investigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate

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4

ROY, KAUSHIK, SAIBAL MUKHOPADHYAY, and HAMID MAHMOODI-MEIMAND. "LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS." Journal of Circuits, Systems and Computers 11, no. 06 (2002): 575–600. http://dx.doi.org/10.1142/s021812660200063x.

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The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.

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5

Hakkee Jung. "Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric." International Journal of Engineering and Technology Innovation 14, no. 2 (2024): 189–200. http://dx.doi.org/10.46604/ijeti.2023.12887.

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This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gate-all-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metal-insulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an

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6

Zhu, C. L., E. Rusli, J. Almira, Chin Che Tin, S. F. Yoon, and J. Ahn. "Physical Simulation of Drain-Induced Barrier Lowering Effect in SiC MESFETs." Materials Science Forum 483-485 (May 2005): 849–52. http://dx.doi.org/10.4028/www.scientific.net/msf.483-485.849.

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The drain-induced barrier lowering (DIBL) effect in 4H-SiC MESFETs has been studied using the physical drift and diffusion model. Our simulation results showed that the high drain voltage typically applied in short-channel 4H-SiC MESFETs could substantially reduce the channel barrier and result in large threshold voltage shift. It is also found that the DIBL effect is more dependent on the ratio of the gate length to channel thickness (Lg/a), rather than the channel thickness itself. In order to minimize the DIBL effect, the ratio of Lg/a should be kept greater than 3 for practical 4H-SiC MESF

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7

Jagtap, Sarika Madhukar, and Vitthal Janardan Gond. "Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics." International Journal of Natural Computing Research 10, no. 3 (2021): 12–28. http://dx.doi.org/10.4018/ijncr.2021070102.

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The scrambling of MOSFET below 22nm, 14nm, unwanted Short Channel Effects (SCE) like punch through, drain-induced barrier lowering (DIBL), along with huge leakage current are flowing through the device, which is not recognized for better performance. Multi-gate MOSFET generally measured as Fin-FET is the best substitute vital to stunned short channel effects. The work highlights results of the current-voltage electrical characteristics of the n-channel triple gate Fin-FET gatherings. The paper focuses on the study of geometry-based device design of Fin-FET by changing high k dielectrics materi

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8

Jung, Hakkee. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 232. http://dx.doi.org/10.11591/ijece.v11i1.pp232-239.

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The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtain

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9

Hakkee, Jung. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 232–39. https://doi.org/10.11591/ijece.v11i1.pp232-239.

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The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L)×10 -7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is o

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10

HAVALDAR, DNAYNESH S., AMITAVA DASGUPTA, and NANDITA DASGUPTA. "STUDY OF DUAL-MATERIAL GATE (DMG) FinFET USING THREE-DIMENSIONAL NUMERICAL SIMULATION." International Journal of Nanoscience 05, no. 04n05 (2006): 541–45. http://dx.doi.org/10.1142/s0219581x06004760.

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In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and leng

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11

DR., Y. V. CHAVAN. "NOVEL DOUBLE GATE JUNCTION-LESS MOSFET USING GERMANIUM." IJIERT - International Journal of Innovations in Engineering Research and Technology ICITER- 16 PUNE (June 20, 2016): 115–18. https://doi.org/10.5281/zenodo.1463581.

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<strong><strong> </strong>temperature applications though its mobility is higher than silicon. So to overcome this problem a high - k dielectric gate oxide such as HfO 2 is used. The performance of 16 - nm germanium symmetric double - gate junctionless transistor (Ge - DGJL T) is evaluated and compared with different gate materials and analysis has been carried out by using 2D - Cogenda Visual TCAD simulator. The performance par ameters,such as drain current (Id),threshold voltage (Vt),drain induced barrier lowering (DIBL),subthreshold slope (SS),are systematically investigated for n - ty

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12

Jung, Hakkee. "Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect." AIMS Electronics and Electrical Engineering 7, no. 1 (2022): 38–49. http://dx.doi.org/10.3934/electreng.2023003.

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<abstract> <p>We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It h

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13

Jung, Hak-Kee. "Analysis of Drain Induced Barrier Lowering for Double Gate MOSFET Using Gaussian Distribution." Journal of the Korean Institute of Information and Communication Engineering 16, no. 2 (2012): 325–30. http://dx.doi.org/10.6109/jkiice.2012.16.2.325.

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14

Jung, Hakkee. "Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile." Journal of the Korea Institute of Information and Communication Engineering 19, no. 11 (2015): 2643–48. http://dx.doi.org/10.6109/jkiice.2015.19.11.2643.

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15

Et. al., Ajay kumar Dharmireddy ,. "3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (2021): 1245–59. http://dx.doi.org/10.17762/turcomat.v12i2.1180.

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This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. Th

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16

Rjoub, Abdoul, Mamoun Mistarihi, and Nedal Al Taradeh. "Accurate leakage current models for MOSFET nanoscale devices." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (2020): 2313. http://dx.doi.org/10.11591/ijece.v10i3.pp2313-2321.

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This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (

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17

Kim, Young, Jin Lee, Geon Kim та ін. "Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors". Electronics 7, № 10 (2018): 227. http://dx.doi.org/10.3390/electronics7100227.

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In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlappe

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18

Chen, Zhuo, Huilong Zhu, Guilei Wang, et al. "Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing." Nanomaterials 13, no. 11 (2023): 1786. http://dx.doi.org/10.3390/nano13111786.

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Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned

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19

Trevisoli, Renan D., Rodrigo T. Doria, Michelly De Souza, and Marcelo Antonio Pavanello. "Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors." Journal of Integrated Circuits and Systems 8, no. 2 (2013): 116–24. http://dx.doi.org/10.29292/jics.v8i2.382.

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Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.

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20

Tan, Michael Loong Peng. "Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs." Journal of Nanomaterials 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/831252.

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Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of dr

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21

Mohammed Abdul Muqeet and Tummala Ranga Babu. "Temperature Characterization and Performance Enhancement of a 7nm FinFET Structure Using HK Materials and GaAs as Metal Gate (MG)." International Journal of Nanoelectronics and Materials (IJNeaM) 17, no. 3 (2024): 355–61. http://dx.doi.org/10.58915/ijneam.v17i3.1116.

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The progress in semiconductor technology has played a crucial role in enhancing human existence by introducing significant innovations. The pursuit of high-performance devices utilizing novel materials has emerged as a crucial avenue for surmounting the existing limitations of silicon-based technologies. This paper presents an evaluation of the diverse short channel effects (SCEs) exhibited by the double gate n-FinFET structure, considering the influence of temperature on channel materials using metal gate (MG) as Gallium Arsenide (GaAs) alongside High-K dielectric oxide materials such as Hafn

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22

Karsenty, Avi, and Avraham Chelly. "Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process." Active and Passive Electronic Components 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/609828.

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Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the chan

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23

Yan, Siao-Cheng, Chen-Han Wu, Chong-Jhe Sun, Yi-Wen Lin, Yi-Ju Yao, and Yung-Chun Wu. "Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application." Nanomaterials 12, no. 13 (2022): 2165. http://dx.doi.org/10.3390/nano12132165.

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Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-

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24

Dasgupta, Arpan, Rahul Das, Shramana Chakraborty, Arka Dutta, Atanu Kundu, and Chandan K. Sarkar. "Comparisons between Dual and Tri Material Gate on a 32 nm Double Gate MOSFET." Nano 11, no. 10 (2016): 1650117. http://dx.doi.org/10.1142/s1793292016501174.

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The paper reports a comparative analysis between the dual material gate double gate (DMG-DG) nMOSFET and the tri material gate double gate (TMG-DG) nMOSFET in terms of their analog and RF performance. Three different devices having the DMG-DG structure have been considered. Each of the devices have different higher workfunction material gate length (L1) to lower workfunction material gate length (L2) ratio (L1:L2). Along with the three devices, the performance of the TMG-DG nMOSFET is compared. The analog parameters considered for the comparison are the drain current ([Formula: see text]), the

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25

Li, Zhuang, Shiyu Long, Chunpeng Zhang, and Fei Ai. "P‐1.13: Electrical Performance of Side Wrapped Thin Film Transistor." SID Symposium Digest of Technical Papers 55, S1 (2024): 667–69. http://dx.doi.org/10.1002/sdtp.17169.

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With the miniaturization of thin film transistor (TFT), it exhibits severe short channel effect (SCE) including drain‐induced barrier lowering (DIBL). In this paper, the authors have manufactured a novel side wrapped TFT to enhance gate electrode's control over the channel and optimize the electric field distribution, which leads to stronger DIBL immunity.

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26

Kim, Tae-Woo. "Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications." Electronics 9, no. 1 (2019): 29. http://dx.doi.org/10.3390/electronics9010029.

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We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degr

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27

Mukherjee, Debasis, and B. V. R. Reddy. "Leakage Process and Minimization -Transistor Stacking Effect, Data Retention Gated Ground Cache, Drowsy Cache." Advanced Materials Research 403-408 (November 2011): 4287–94. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.4287.

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Leakage Current is found to be gradually increasing in CMOS VLSI circuits with advance of technologies, specially in nanometer range. Though area of a transistor is becoming less and lesser, but precious control over the operations of a transistor is not possible in such a small structure. Reductions of threshold voltage, channel length, and gate oxide thickness are responsible for generation of leakage current. In this paper we have reviewed eight types of leakage current present in CMOS VLSI circuits, namely 1. Reverse Bias pn Junction Current, 2. Sub-threshold Leakage, 3. Drain Induced Barr

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28

Liaw, Yue-Gie, Chii-Wen Chen, Wen-Shiang Liao, Mu-Chun Wang, and Xuecheng Zou. "Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs." Modern Physics Letters B 32, no. 15 (2018): 1850157. http://dx.doi.org/10.1142/s0217984918501579.

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Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text

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29

Faisal, Md Saud Al, Md Rokib Hasan, Marwan Hossain, and Mohammad Saiful Islam. "Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs." Circulation in Computer Science 2, no. 2 (2017): 15–19. http://dx.doi.org/10.22632/ccs-2017-251-50.

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GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade a

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Islam, Md Rabiul, Md Kamrul Hasan, Md Abdul Mannan, M. Tanseer Ali, and Md Rokib Hasan. "Gate Length Effect on Gallium Nitride Based Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor." AIUB Journal of Science and Engineering (AJSE) 18, no. 2 (2019): 73–80. http://dx.doi.org/10.53799/ajse.v18i2.43.

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We have investigated the performance of Gallium Nitride (GaN) based Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Atlas Device Simulation Framework -Silvaco has been used to access Non-Equilibrium Green Function to distinguish the transfer characteristics curve, ON state current (ION), OFF-state current (IOFF), Drain Induced Barrier Lowering (DIBL), Subthreshold Swing, Electron Current Density, Conduction Band Energy and Electric Field. The concept of Solid state device physics on the effect of gate length studied for the next generation logic applications. GaN-b

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31

Arul, P., and K. Helen Prabha. "A Comprehensive Analysis of Short Channel Effects on Carbon Nano Tube Field Effect Transistors." Journal of Nanoelectronics and Optoelectronics 16, no. 12 (2021): 1905–12. http://dx.doi.org/10.1166/jno.2021.3144.

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As the direction of World health organization (WHO) report the diseases like male infertility, brain tumor, hearing impairment, fetus issues, effect on eyes and other various parts of the human body caused by harmful radiations released by portable electronic devices. To reduce radiation and size, a deep scaling has been applied on MOSFETs. Due to this aggressive scaling MOSFET devices are affected by Short Channel Effects (SCE) in Nanometer regime (<10 nm). The Short Channel Effects Such as Subthreshold Swing (SS), Drain Induced barrier Lowering (DIBL) and threshold voltage roll-off (VT),

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32

Ramakrishnan, Mathangi, Nurul Ezaila Alias, Afiq Hamzah, Michael Loong Peng Tan, Yusmeeraz Yusof, and Mathan Natarajamoorthy. "Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET." Journal of Physics: Conference Series 2622, no. 1 (2023): 012020. http://dx.doi.org/10.1088/1742-6596/2622/1/012020.

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Abstract Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across th

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33

Xu Li-Jun and Zhang He-Ming. "Drain-induced barrier-lowering effect in surrounding-gate schottky barrier metal-oxide semiconductor field transistor." Acta Physica Sinica 62, no. 10 (2013): 108502. http://dx.doi.org/10.7498/aps.62.108502.

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34

Jung, Hak-Kee. "Dependence of Drain Induced Barrier Lowering for Doping Profile of Channel in Double Gate MOSFET." Journal of the Korean Institute of Information and Communication Engineering 15, no. 9 (2011): 2000–2006. http://dx.doi.org/10.6109/jkiice.2011.15.9.2000.

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35

Jung, Hak-Kee. "Analysis of Drain Induced Barrier Lowering for Double Gate MOSFET According to Channel Doping Concentration." Journal of the Korean Institute of Information and Communication Engineering 16, no. 3 (2012): 579–84. http://dx.doi.org/10.6109/jkiice.2012.16.3.579.

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36

Jung, Hakkee. "Dependence of Channel Doping Concentration on Drain Induced Barrier Lowering for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 4 (2016): 805–10. http://dx.doi.org/10.6109/jkiice.2016.20.4.805.

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37

Imam, Safayat-Al, Nasheen Kalam, and Sharmin Abdullah. "Comparative Analysis of Control Coefficients on the Performance of CNTFET Under Different Parameters." International Journal of Nanoscience 15, no. 03 (2016): 1640005. http://dx.doi.org/10.1142/s0219581x16400056.

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This paper deals with the performance of both gate and drain control coefficients to analyze the behavior of carbon nanotube field effect transistors (CNTFETs) under ballistic conditions and based on the change of different parameter value, such as oxide thickness of structure and temperature variation. A thorough study of both gate and drain control coefficient effects on the performance of CNTFETs has been conducted under different temperature and oxide layers and the output of the device has been analyzed through different parameters. Higher values of control coefficient help to attain larg

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Qu, Jiang Tao, He Ming Zhang, Hui Yong Hu, Xiao Bo Xu, Guan Yu Wang, and Xiao Yan Wang. "The Impact of Drain-Induced Barrier Lowering Effect on Threshold Voltage for Small-Scaled Strained Si/SiGe nMOSFET." Applied Mechanics and Materials 110-116 (October 2011): 5457–63. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5457.

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The impact of Drain-Induced Barrier Lowering effect (DIBL) on the shift of threshold voltage is prominent as the feature size of MOS device continue reducing. In this paper, a threshold voltage model for small-scaled strained Si nMOSFET is proposed to illustrate the impact of DIBL effect on the threshold voltage, which is based on the distribution of the charge in depletion layer when strong inversion occurred. By simulation, the influence of DIBL to variation threshold voltage with its design physical and geometric parameters can be predicted, such as gate length, drain bias, Ge content, oxid

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Samia, Slimani, and Djellouli Bouaza. "Quantum Effects on the Performance of SOI Double-Gate Mosfet." Advanced Materials Research 685 (April 2013): 185–90. http://dx.doi.org/10.4028/www.scientific.net/amr.685.185.

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In spite of progress in silicon technology, the end of Mosfet scaling can be anticipated for the year 2015 so the introduction of high permittivity gate dielectric is the envisaged solution to reduce the current leakage that drives up power consumption. In this paper we investigate the impact of different gate length on SOI double gate MOSFET when SiO2 is replaced by ZrO2 as the gate dielectric using Nextnano Simulator. The impact of the quantum effects also observed on performance parameters of the DG-MOSFET such as on current, off current, drain induced barrier lowering, and sub-threshold. I

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Jung, Hakkee. "SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1288. http://dx.doi.org/10.11591/ijece.v10i2.pp1288-1295.

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We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current meth

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Hakkee, Jung. "SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1288–95. https://doi.org/10.11591/ijece.v10i2.pp1288-1295.

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We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current metho

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Djamil, Rechem, Benkara Salima та Lamamra Kheireddine. "Performance Enhancement of CNTFETs with High-Κ Dielectric". Advanced Materials Research 685 (квітень 2013): 340–44. http://dx.doi.org/10.4028/www.scientific.net/amr.685.340.

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The potential impact of high permittivity gate dielectrics on the performance of a ballistic nanoscale CNTFET is studied over a wide range of dielectric permittivities with low temperatures ranging from room temperature down to 100 K. Using the non-equilibrium Greens function (NEGF) formalism. Device characteristics such as ION/IOFF current ratio, threshold voltage, the drain induced barrier lowering (DIBL). The effects of temperature varying are also examined.

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Alam, Sayem Ul, Rukon Uddin, Md Jahangir Alam, Ahamed Raihan, Sheikh S. Mahtab, and Subrata Bhowmik. "Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET." Modelling and Simulation in Engineering 2022 (October 19, 2022): 1–9. http://dx.doi.org/10.1155/2022/8345513.

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Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi-3D mathematical model. The result has been signified steeper surface potential (ψ), lower threshold voltage (Vth), 1.2 mA of on-state current (Ion), and enhanced immunity of negative capacitance FinFET against short channel effects (SCE’s) like 3

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Nura Muhammad Shehu, Garba Babaji, and Mutari Hajara Ali. "Gate work function variability-dependent short channel effects in nanoscale double gate finFETs: an in-depth comparative analysis." International Journal of Engineering & Technology 12, no. 2 (2023): 76–81. http://dx.doi.org/10.14419/ijet.v12i2.32412.

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We explored the impact of gate work-function variations on Short Channel Effects (SCEs) in nanoscale Double Gate FinFETs utilizing GaAs, GaSb, GaN, and Si as semiconductor channel materials. The analysis is carried out using PADRE Simulator. Critical performance parameters examined are Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), Threshold Voltage Roll-off, On-Current and Transconductance. The results show that GaAs-FinFET excels in terms of DIBL and threshold voltage and on-current. GaN-FinFET shows higher superiority in terms of SS. While GaAs and GaN outperform the other

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Atamuratov, Atabek E., Khushnudbek Sh Saparov, Ahmed Yusupov, and Jean Chamberlain Chedjou. "Combined Influence of Gate Oxide and Back Oxide Materials on Self-Heating and DIBL Effect in 2D MOS2-Based MOSFETs." Applied Sciences 13, no. 10 (2023): 6131. http://dx.doi.org/10.3390/app13106131.

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In this paper, degradation effects, such as self-heating effect (SHE) and drain-induced barrier lowering (DIBL) effect in 2D MoS2-based MOSFETs are investigated through simulations. The SHE is simulated based on the thermodynamic transport model. The dependence of the DIBL effect and the lattice temperature in the middle of the channel on the gate length is considered for transistors with different gate oxide and back oxide (BOX) materials. The effects of Al2O3 and HfO2 as gate oxide and SiO2 and HfO2 as BOX materials are compared. Transistors, in which the channel is fully and partially (i.e.

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Zhichao, Zhao, Wu Tiefeng, Li Jing, Wang Quan, and Han Wanglong. "Gate Tunneling Current Model of Scaled Strained Si n-MOSFET with Drain Induced Barrier Lowering Effects." Journal of Nanoelectronics and Optoelectronics 12, no. 7 (2017): 724–30. http://dx.doi.org/10.1166/jno.2017.2100.

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Chen, Zehua, Hei Wong, Yan Han, Shurong Dong, and B. L. Yang. "Temperature dependences of threshold voltage and drain-induced barrier lowering in 60nm gate length MOS transistors." Microelectronics Reliability 54, no. 6-7 (2014): 1109–14. http://dx.doi.org/10.1016/j.microrel.2013.12.005.

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Abdul-Kadir, Firas Natheer, Yasir Hashim, Muhammad Nazmus Shakib, and Faris Hassan Taha. "Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 780. http://dx.doi.org/10.11591/ijece.v11i1.pp780-787.

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3n

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Firas, Natheer Abdul-Kadir, Hashim Yasir, Nazmus Shakib Mohammed, and Hassan Taha Faris. "Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 780–87. https://doi.org/10.11591/ijece.v11i1.pp780-787.

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This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (V T ). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and

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Mohanty, Soumya S., Urmila Bhanja, and Guru P. Mishra. "An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor." Nanoscience & Nanotechnology-Asia 10, no. 2 (2020): 157–65. http://dx.doi.org/10.2174/2210681209666181126151239.

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Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET) with gate underlap on both source and drain end to improve the DC and RF performance. Methods: A comprehensive and methodological investigation of DC and RF performance of III-V semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of the device, which is used to mitigate the short channel issues to improve the device performance. Hydrodynamic model has been taken into consideration for the

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