Relevant bibliographies by topics / Gate-level

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Gate-level'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 February 2022

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Journal articles on the topic "Gate-level"

1

Saigo, T., K. Niwa, T. Ohto, S. Kurosawa, and T. Takada. "A triple-level wired 24K-gate CMOS gate array." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1005–11. http://dx.doi.org/10.1109/jssc.1985.1052428.

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Smith, S. C., R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson. "Delay-insensitive gate-level pipelining." Integration 30, no. 2 (October 2001): 103–31. http://dx.doi.org/10.1016/s0167-9260(01)00013-x.

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Fan, X., W. R. Moore, C. Hora, and G. Gronthoud. "Extending gate-level diagnosis tools to CMOS intra-gate faults." IET Computers & Digital Techniques 1, no. 6 (2007): 685. http://dx.doi.org/10.1049/iet-cdt:20060206.

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Chatterjee, Debapriya, Andrew Deorio, and Valeria Bertacco. "Gate-Level Simulation with GPU Computing." ACM Transactions on Design Automation of Electronic Systems 16, no. 3 (June 2011): 1–26. http://dx.doi.org/10.1145/1970353.1970363.

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Golić, J. Dj, and R. Menicocci. "Universal masking on logic gate level." Electronics Letters 40, no. 9 (2004): 526. http://dx.doi.org/10.1049/el:20040385.

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BAE, T. I., J. W. KIM, and Y. H. KIM. "New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 12 (December 1, 2008): 3488–96. http://dx.doi.org/10.1093/ietfec/e91-a.12.3488.

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RAEMY, F., and W. H. HAGER. "HYDRAULIC LEVEL CONTROL BY HINGED FLAP GATE." Proceedings of the Institution of Civil Engineers - Water Maritime and Energy 130, no. 2 (June 1998): 95–103. http://dx.doi.org/10.1680/iwtme.1998.30478.

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., Md Moyeed Abrar. "LOGIC GATE BASED AUTOMATIC WATER LEVEL CONTROLLER." International Journal of Research in Engineering and Technology 03, no. 04 (April 25, 2014): 477–82. http://dx.doi.org/10.15623/ijret.2014.0304085.

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Cabodi, G., S. Gai, and M. Sonza Reorda. "A transputer-based gate-level fault simulator." Microprocessing and Microprogramming 30, no. 1-5 (August 1990): 529–34. http://dx.doi.org/10.1016/0165-6074(90)90294-j.

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Takach, A. R., and N. K. Jha. "Easily testable gate-level and DCVS multipliers." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 7 (July 1991): 932–42. http://dx.doi.org/10.1109/43.87603.

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Dissertations / Theses on the topic "Gate-level"

1

Shelly, Jacinda R. (Jacinda Rene). "Concurrent gate-level circuit simulation." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61576.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 42).
In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. I also analyze a test circuit's performance in order to quantitatively demonstrate the benefit of considering these principles in advance of running simulations.
by Jacinda R. Shelly.
M.Eng.
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Kathuria, Tarun. "Gate-level Leakage Assessment and Mitigation." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/101862.

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Side-channel leakage, caused by imperfect implementation of cryptographic algorithms in hardware, has become a serious security threat for connected devices that generate and process sensitive data. This side-channel leakage can divulge secret information in the form of power consumption or electromagnetic emissions. The side-channel leakage of a crytographic device is commonly assessed after tape-out on a physical prototype. This thesis presents a methodology called Gate-level Leakage Assessment (GLA), which evaluates the power-based side-channel leakage of an integrated circuit at design time. By combining side-channel leakage assessment with power simulations on the gate-level netlist, GLA is able to pinpoint the leakiest cells in the netlist in addition to assessing the overall side-channel vulnerability to side-channel leakage. As the power traces obtained from power simulations are noiseless, GLA is able to precisely locate the sources of side-channel leakage with fewer measurements than on a physical prototype. The thesis applies the methodology on the design of a encryption co-processor to analyze sources of side-channel leakage. Once the gate-level leakage sources are identified, this thesis presents a logic level replacement strategy for the leakage sources that can thwart side-channel leakage. The countermeasures presented selectively replaces gate-level cells with a secure logic style effectively removing the side-channel leakage with minimal impact in area. The assessment methodology along with the countermeasures demonstrated is a turnkey solution for IP module designers and is also applicable to larger system level designs.
Master of Science
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Chow, Raymond W. L. Carleton University Dissertation Information and Systems Science. "Gate level transistor sizing by nonlinear optimization." Ottawa, 1992.

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Babb, Jonathan William. "High level compilation for gate reconfigurable architectures." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8217.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 205-215).
A continuing exponential increase in the number of programmable elements is turning management of gate-reconfigurable architectures as "glue logic" into an intractable problem; it is past time to raise this abstraction level. The physical hardware in gate-reconfigurable architectures is all low level - individual wires, bit-level functions, and single bit registers - hence one should look to the fetch-decode-execute machinery of traditional computers for higher level abstractions. Ordinary computers have machine-level architectural mechanisms that interpret instructions - instructions that are generated by a high-level compiler. Efficiently moving up to the next abstraction level requires leveraging these mechanisms without introducing the overhead of machine-level interpretation. In this dissertation, I solve this fundamental problem by specializing architectural mechanisms with respect to input programs. This solution is the key to efficient compilation of high-level programs to gate reconfigurable architectures. My approach to specialization includes several novel techniques. I develop, with others, extensive bitwidth analyses that apply to registers, pointers, and arrays. I use pointer analysis and memory disambiguation to target devices with blocks of embedded memory. My approach to memory parallelization generates a spatial hierarchy that enables easier-to-synthesize logic state machines with smaller circuits and no long wires.
(cont.) My space-time scheduling approach integrates the techniques of high-level synthesis with the static routing concepts developed for single-chip multiprocessors. Using DeepC, a prototype compiler demonstrating my thesis, I compile a new benchmark suite to Xilinx Virtex FPGAs. Resulting performance is comparable to a custom MIPS processor, with smaller area (40 percent on average), higher evaluation speeds (2.4x), and lower energy (18x) and energy-delay (45x). Specialization of advanced mechanisms results in additional speedup, scaling with hardware area, at the expense of power. For comparison, I also target IBM's standard cell SA-27E process and the RAW microprocessor. Results include sensitivity analysis to the different mechanisms specialized and a grand comparison between alternate targets.
by Jonathan William Babb.
Ph.D.
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Kim, Dong-Wook. "CMOS digital circuit test generation for transistor level and gate-level implementation." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/13890.

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Baweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.

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Acharya, Vineeth Vadiraj. "Branch Guided Metrics for Functional and Gate-level Testing." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/51661.

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With the increasing complexity of modern day processors and system-on-a-chip (SOCs), designers invest a lot of time and resources into testing and validating these designs. To reduce the time-to-market and cost, the techniques used to validate these designs have to constantly improve. Since most of the design activity has moved to the register transfer level (RTL), test methodologies at the RTL have been gaining momentum. We present a novel functional test generation framework for functional test generation at RTL. A popular software-based metric for measuring the effectiveness of an RTL test suite is branch coverage. But exercising hard-to-reach branches is still a challenge and requires good understanding of the design semantics. The proposed framework uses static analysis to extract certain semantics of the circuit and uses several data structures to model these semantics. Using these data structures, we assist the branch-guided search to exercise these hard-to-reach branches. Since the correlation between high branch coverage and detecting defects and bugs is not clear, we present a new metric at the RTL which augments the RTL branch coverage with state values. Vectors which have higher scores on the new metric achieve higher branch and state coverages, and therefore can be applied at different levels of abstraction such as post-silicon validation. Experimental results show that use of the new metric in our test generation framework can achieve a high level of branch and fault coverage for several benchmark circuits, while reducing the length of the vector sequence. This work was supported in part by the NSF grant 1016675.
Master of Science
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Misera, Silvio, and Andre´ Sieber. "Fehlerinjektionstechniken in SystemC-Beschreibungen mit Gate- und Switch-Level Verhalten." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700865.

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Zur Beschreibung elektronischer Systeme hat SystemC inzwischen eine festen Platz in der Entwurfslandschaft gefunden. Ein wesentlicher Vorteil eines SystemC-Modells ist die bereits vorhandene Möglichkeit einer Simulation. Neben der rein funktionalen Simulation zur Entwurfsvalidierung ergeben sich für eine Simulation mit injizierten Fehlern zusätzliche Herausforderungen. In dieser Arbeit werden diverse Techniken zur Fehlerinjektion in SystemC vorgestellt. Einige vergleichende Experimente helfen diese Techniken zu bewerten. Anschließend werden einige Modelle präsentiert, die es gestatten, SystemC auch auf niederen Ebenen des Hardwareentwurfs einzusetzen. Mit den vorgeschlagenen Methoden eröffnet sich hiermit die Möglichkeit einer genauen Untersuchung zur Auswirkung von Hardwarefehlern in digitalen Schaltungen mit Hilfe von SystemC.
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Rabe, Dirk. "Accurate power analysis of integrated CMOS circuits on gate level." [S.l.] : [s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962733520.

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Jangid, Anuradha. "Verifying IP-Cores by Mapping Gate to RTL-Level Designs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878.

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Books on the topic "Gate-level"

1

Shahriari, Mehrdad. A gate-level timing model for SOI circuits. Ottawa: National Library of Canada, 2002.

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Stroud, Jonathan. Ptolemy's Gate. New York: Miramax Books/Hyperion Books For Children, 2006.

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Stroud, Jonathan. Ptolemy's gate. New York: Hyperion Books For Children, 2006.

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Gate, Heavens. How and When "Heaven's Gate" (The Door to the Physical Kingdom Level Above Human) May Be Entered: An Anthology of Our Materials. Mill Spring, Usa: Wildflower Press, 1997.

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Avinash, Lakshminarayana, and Shukla Sandeep K, eds. Low power design with high-level power estimation and power-aware synthesis. New York: Springer, 2012.

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The Gate Opener: Level 2 (Mystery Mansion). Concordia Pub House (J), 2001.

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The Gate Opener: Level 1 (Mystery Mansion). Concordia Pub House (J), 2001.

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Straka, Marilyn. On the Level San Francisco: Golden Gate Park Walking Tour. On The Level San Francisco, 2002.

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Straka, Marilyn. On the Level San Francisco: Golden Gate Bridge / Fort Point Walking Tour. On The Level San Francisco, 2002.

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Center, Langley Research, ed. Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1995.

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Book chapters on the topic "Gate-level"

1

Saleh, Resve A., and A. Richard Newton. "Gate-Level Simulation." In The Kluwer International Series in Engineering and Computer Science, 101–32. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-0695-5_5.

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Saleh, Resve, Shyh-Jye Jou, and A. Richard Newton. "Gate-Level Simulation." In Mixed-Mode Simulation and Analog Multilevel Simulation, 123–52. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4757-5854-2_5.

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Thomas, Donald E., and Philip R. Moorby. "Defining Gate Level Primitives." In The Verilog® Hardware Description Language, 99–111. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_5.

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Thomas, Donald E., and Philip R. Moorby. "Defining Gate Level Primitives." In The Verilog® Hardware Description Language, 127–38. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2365-6_5.

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Reynders, Nele, and Wim Dehaene. "Gate-Level Building Blocks." In Analog Circuits and Signal Processing, 47–84. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-16136-5_3.

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Navabi, Zainalabedin. "Gate Level Combinational Design." In Digital Design and Implementation with Field Programmable Devices, 187–98. Boston, MA: Springer US, 2005. http://dx.doi.org/10.1007/1-4020-8012-3_7.

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Buard, Nadine, and Lorena Anghel. "Gate Level Modeling and Simulation." In Soft Errors in Modern Electronic Systems, 77–102. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6993-4_4.

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Keymeulen, Didier, Kenji Konaka, Masaya Iwata, Yasuo Kuniyoshi, and Tetsuya Higuchi. "Robot Learning using Gate-Level Evolvable Hardware." In Learning Robots, 173–88. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/3-540-49240-2_12.

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Dai, Yu-Yun, and Robert K. Brayton. "Identifying Transparent Logic in Gate-Level Circuits." In Advanced Logic Synthesis, 103–24. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-67295-3_5.

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Hillebrand, Mark, and Sergey Tverdyshev. "Formal Verification of Gate-Level Computer Systems." In Computer Science - Theory and Applications, 322–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03351-3_30.

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Conference papers on the topic "Gate-level"

1

Wei, Sheng, Saro Meguerdichian, and Miodrag Potkonjak. "Gate-level characterization." In the 47th Design Automation Conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1837274.1837332.

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Fujita, Masahiro, Yoshihisa Kojima, and Amir Masoud Gharehbaghi. "Debugging from high level down to gate level." In the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630077.

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Smith, J. W. "The gsim gate-level simulator." In the 38th annual. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/1127716.1127732.

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Mishchenko, Alan, Niklas Een, Robert Brayton, Jason Baumgartner, Hari Mony, and Pradeep Nalla. "GLA: Gate-Level Abstraction Revisited." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.286.

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Jain, Alok, and Randal E. Bryant. "Mapping switch-level simulation onto gate-level hardware accelerators." In the 28th conference. New York, New York, USA: ACM Press, 1991. http://dx.doi.org/10.1145/127601.127668.

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Ghosal, Sandip, and Debasis Mitra. "Secure transmission of gate level description." In 2012 1st International Conference on Recent Advances in Information Technology (RAIT). IEEE, 2012. http://dx.doi.org/10.1109/rait.2012.6194498.

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Fox, A., M. Mikulics, H. Hardtdegen, St Trellenkamp, Y. C. Arango, D. Grutzmacher, Z. Sofer, et al. "Novel double-level-T-gate technology." In 2014 10th International Conference on Advanced Semiconductor Devices & Microsystems (ASDAM). IEEE, 2014. http://dx.doi.org/10.1109/asdam.2014.6998653.

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Kim, Dusung, Maciej Ciesielski, Kyuho Shim, and Seiyang Yang. "Temporal parallel gate-level timing simulation." In 2008 IEEE International High Level Design Validation and Test Workshop (HLDVT). IEEE, 2008. http://dx.doi.org/10.1109/hldvt.2008.4695886.

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Juretus, Kyle, and Ioannis Savidis. "Reduced Overhead Gate Level Logic Encryption." In GLSVLSI '16: Great Lakes Symposium on VLSI 2016. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2902961.2902972.

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Viamontes, George F., Manoj Rajagopalan, Igor L. Markov, and John P. Hayes. "Gate-level simulation of quantum circuits." In the 2003 conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/1119772.1119829.

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Reports on the topic "Gate-level"

1

Li, Wenchao. Formal Methods for Reverse Engineering Gate-Level Netlists. Fort Belvoir, VA: Defense Technical Information Center, December 2013. http://dx.doi.org/10.21236/ada623698.

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Schafer, Ingo. Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.1338.

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