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1
Shelly, Jacinda R. (Jacinda Rene). "Concurrent gate-level circuit simulation." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61576.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 42).
In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. I also analyze a test circuit's performance in order to quantitatively demonstrate the benefit of considering these principles in advance of running simulations.
by Jacinda R. Shelly.
M.Eng.
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Kathuria, Tarun. "Gate-level Leakage Assessment and Mitigation." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/101862.
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Side-channel leakage, caused by imperfect implementation of cryptographic algorithms in
hardware, has become a serious security threat for connected devices that generate and
process sensitive data. This side-channel leakage can divulge secret information in the form of
power consumption or electromagnetic emissions. The side-channel leakage of a crytographic
device is commonly assessed after tape-out on a physical prototype.
This thesis presents a methodology called Gate-level Leakage Assessment (GLA), which
evaluates the power-based side-channel leakage of an integrated circuit at design time. By
combining side-channel leakage assessment with power simulations on the gate-level netlist,
GLA is able to pinpoint the leakiest cells in the netlist in addition to assessing the overall
side-channel vulnerability to side-channel leakage. As the power traces obtained from power
simulations are noiseless, GLA is able to precisely locate the sources of side-channel leakage
with fewer measurements than on a physical prototype. The thesis applies the methodology
on the design of a encryption co-processor to analyze sources of side-channel leakage.
Once the gate-level leakage sources are identified, this thesis presents a logic level replacement
strategy for the leakage sources that can thwart side-channel leakage. The countermeasures
presented selectively replaces gate-level cells with a secure logic style effectively removing
the side-channel leakage with minimal impact in area. The assessment methodology along
with the countermeasures demonstrated is a turnkey solution for IP module designers and
is also applicable to larger system level designs.Master of Science
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Chow, Raymond W. L. Carleton University Dissertation Information and Systems Science. "Gate level transistor sizing by nonlinear optimization." Ottawa, 1992.
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Babb, Jonathan William. "High level compilation for gate reconfigurable architectures." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8217.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 205-215).
A continuing exponential increase in the number of programmable elements is turning management of gate-reconfigurable architectures as "glue logic" into an intractable problem; it is past time to raise this abstraction level. The physical hardware in gate-reconfigurable architectures is all low level - individual wires, bit-level functions, and single bit registers - hence one should look to the fetch-decode-execute machinery of traditional computers for higher level abstractions. Ordinary computers have machine-level architectural mechanisms that interpret instructions - instructions that are generated by a high-level compiler. Efficiently moving up to the next abstraction level requires leveraging these mechanisms without introducing the overhead of machine-level interpretation. In this dissertation, I solve this fundamental problem by specializing architectural mechanisms with respect to input programs. This solution is the key to efficient compilation of high-level programs to gate reconfigurable architectures. My approach to specialization includes several novel techniques. I develop, with others, extensive bitwidth analyses that apply to registers, pointers, and arrays. I use pointer analysis and memory disambiguation to target devices with blocks of embedded memory. My approach to memory parallelization generates a spatial hierarchy that enables easier-to-synthesize logic state machines with smaller circuits and no long wires.
(cont.) My space-time scheduling approach integrates the techniques of high-level synthesis with the static routing concepts developed for single-chip multiprocessors. Using DeepC, a prototype compiler demonstrating my thesis, I compile a new benchmark suite to Xilinx Virtex FPGAs. Resulting performance is comparable to a custom MIPS processor, with smaller area (40 percent on average), higher evaluation speeds (2.4x), and lower energy (18x) and energy-delay (45x). Specialization of advanced mechanisms results in additional speedup, scaling with hardware area, at the expense of power. For comparison, I also target IBM's standard cell SA-27E process and the RAW microprocessor. Results include sensitivity analysis to the different mechanisms specialized and a grand comparison between alternate targets.
by Jonathan William Babb.
Ph.D.
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Kim, Dong-Wook. "CMOS digital circuit test generation for transistor level and gate-level implementation." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/13890.
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Baweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.
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Acharya, Vineeth Vadiraj. "Branch Guided Metrics for Functional and Gate-level Testing." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/51661.
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With the increasing complexity of modern day processors and system-on-a-chip (SOCs), designers invest a lot of time and resources into testing and validating these designs. To reduce the time-to-market and cost, the techniques used to validate these designs have to constantly improve. Since most of the design activity has moved to the register transfer level (RTL), test methodologies at the RTL have been gaining momentum. We present a novel functional test generation framework for functional test generation at RTL. A popular software-based metric for measuring the effectiveness of an RTL test suite is branch coverage. But exercising hard-to-reach branches is still a challenge and requires good understanding of the design semantics. The proposed framework uses static analysis to extract certain semantics of the circuit and uses several data structures to model these semantics. Using these data structures, we assist the branch-guided search to exercise these hard-to-reach branches. Since the correlation between high branch coverage and detecting defects and bugs is not clear, we present a new metric at the RTL which augments the RTL branch coverage with state values. Vectors which have higher scores on the new metric achieve higher branch and state coverages, and therefore can be applied at different levels of abstraction such as post-silicon validation. Experimental results show that use of the new metric in our test generation framework can achieve a high level of branch and fault coverage for several benchmark circuits, while reducing the length of the vector sequence.
This work was supported in part by the NSF grant 1016675.Master of Science
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Misera, Silvio, and Andre´ Sieber. "Fehlerinjektionstechniken in SystemC-Beschreibungen mit Gate- und Switch-Level Verhalten." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700865.
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Zur Beschreibung elektronischer Systeme hat SystemC inzwischen eine festen Platz in der
Entwurfslandschaft gefunden. Ein wesentlicher Vorteil eines SystemC-Modells ist die bereits
vorhandene Möglichkeit einer Simulation. Neben der rein funktionalen Simulation zur
Entwurfsvalidierung ergeben sich für eine Simulation mit injizierten Fehlern zusätzliche
Herausforderungen. In dieser Arbeit werden diverse Techniken zur Fehlerinjektion in SystemC
vorgestellt. Einige vergleichende Experimente helfen diese Techniken zu bewerten. Anschließend
werden einige Modelle präsentiert, die es gestatten, SystemC auch auf niederen Ebenen des
Hardwareentwurfs einzusetzen. Mit den vorgeschlagenen Methoden eröffnet sich hiermit die
Möglichkeit einer genauen Untersuchung zur Auswirkung von Hardwarefehlern in digitalen
Schaltungen mit Hilfe von SystemC.
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Rabe, Dirk. "Accurate power analysis of integrated CMOS circuits on gate level." [S.l.] : [s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962733520.
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Jangid, Anuradha. "Verifying IP-Cores by Mapping Gate to RTL-Level Designs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878.
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Raahemifar, Kaamran. "Testing asynchronous logic circuits from transistor networks to gate-level designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0010/NQ52440.pdf.
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Mabry, Ryan. "Gate Level Dynamic Energy Estimation In Asynchronous Circuits Using Petri Nets." Scholar Commons, 2007. http://scholarcommons.usf.edu/etd/3826.
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This thesis introduces a new methodology for energy estimation in asynchronous circuits. Unlike existing probabilistic methods, this is the first simulative work for energy estimation in all types of asynchronous circuits.
The new simulative methodology is based on Petri net modeling. A real delay model is incorporated to capture both gate delays and interconnect delays. The switching activity at each gate is captured to measure the average dynamic energy consumed per request/acknowledge handshaking pair. The new type of Petri net is called Hierarchical Colored Asynchronous Hardware Petri net (HCAHPN). The HCAHPN is able to capture the temporal and spatial correlations of signals within a circuit, while preserving gate logic behavior and timing information.
While Petri nets have been previously used for simulating combinational and sequential circuits, this is the first work that uses Petri nets for simulating asynchronous circuits. While different asynchronous design styles make various assumptions on the gate and wire delays present with the circuit, the physical implementations of these circuits always have gate and interconnect delays. Unlike previous methods, the proposed methodology is independent of the asynchronous design style used and it can be adapted for all types of asynchronous circuits that use handshaking communication.
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Meraji, Seyed Sina. "Towards optimazation techniques for dynamic load balancing of parallel gate level simulation." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104767.
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As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this thesis, we examine the performance of a parallel Verilog simulator, VXTW, on four large, real designs using an optimistic synchronization scheme named Time Warp. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. Because of the low computational granularity of a gate level simulation and because the computational and communication loads vary throughout the course of the simulation, the performance of Time Warp can be severely degraded or can even be unstable. Dynamic load balancing algorithms for balancing the computational and communication loads during the simulation are described in this thesis. Like all load balancing algorithms, the proposed algorithms have some tuning parameters which must be optimized. In addition, in order to avoid the simulation from being too optimistic, we make use of a time window. In the thesis, we make use of learning techniques from artificial intelligence (N-armed Bandit, Multi-state Q-learning) and heuristic searches (Genetic Algorithm, Simulated Annealing) to tune the parameters of the dynamic load balancing algorithms and to determine the size of the time window. we evaluated the performance of these algorithms on open source Sparc and Leon processor designs and on two Viterbi decoder designs and observed up to a 70% improvement in simulation time using these approaches.Une des conséquences de la loi de Moore est la croissance significative de lataille des circuits intégrés; il en résulte que la simulation est devenue le goulot d'étranglement majeur dans le processus de conception de tels circuits. Conséquemment, la simulation parallèle se veut une approche qui a le potentiel d'être à la fois rapide etrentable. Dans cette thèse, nous examinerons la performance d'un simulateur Verilog parallèle appelé VXTW sur quatre conceptions de processeurs réelles de grande taille, en utilisant un algorithme de synchronisation optimiste appelé Time Warp. Puisque les travaux précédents ont utilisé des circuits synthétiques ou des tests de performance de taille relativement petite, l'utilisation de ces circuits est beaucoup plus réaliste. Puisque les simulations au niveau des portes logiques impliquent une granularité calculatoire peu élevée, et puisque les charges calculatoires et de communication varient au cours de la simulation, la performance de Time Warp peut se dégrader sévèrement ou devenir instable. Dans cette thèse, nous décrivons des algorithmes dynamiques d'équilibrage de charge visant à équilibrer les charges calculatoires et de communicationdurant la simulation. Comme tous les algorithmes d'équilibrage de charge, les algorithmes proposés comportent des paramètres de réglage qui doivent être optimisés. De plus, nous utilisons une fenêtre de temps pour éviter que la simulation ne soit trop optimiste. Dans cette thèse, nous utilisons des techniques d'apprentissage provenant du domaine de l'intelligence artificielle (machine à sous à leviers multiples, Q-learning avec plusieurs agents) et des recherches heuristiques (algorithmes génétiques, méthode du circuit simulé) pour régler les paramètres des algorithmes dynamiques d'équilibrage des charges, ainsi que pour déterminer la taille de la fenêtre de temps. Nous évaluons la performance de ces algorithmes sur des conceptions de processeurs Sparc et Leon libres de droits, ainsi que sur deux décodeurs Viterbi, et nous avons pu observer une amélioration du temps de simulation de 70% en utilisant ces approches.
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Nilsson, Jesper. "Mixed RTL and gate-level power estimation with low power design iteration." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1685.
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In the last three decades we have witnessed a remarkable development in the area of integrated circuits. From small logic devices containing some hundred transistors to modern processors containing several tens of million transistors. However, power consumption has become a real problem and may very well be the limiting factor of future development. Designing for low power is therefore increasingly important. To accomplice an efficient low power design, accurate power estimation at early design stage is essential. The aim of this thesis was to set up a power estimation flow to estimate the power consumption at early design stage. The developed flow spans over both RTL- and gate-level incorporating Mentor Graphics Modelsim (RTL-level simulator), Cadence PKS (gate- level synthesizer) and own developed power estimation tools. The power consumption is calculated based on gate-level physical information and RTL- level toggle information. To achieve high estimation accuracy, real node annotations is used together with an own developed on-chip wire model to estimate node voltage swing.
Since the power estimation may be very time consuming, the flow also includes support for low power design iteration. This gives efficient power estimation speedup when concentrating on smaller sub- parts of the design.
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Samala, Harikrishna. "Methodology to Derive Resource Aware Context Adaptable Architectures for Field Programmable Gate Arrays." DigitalCommons@USU, 2009. https://digitalcommons.usu.edu/etd/484.
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The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a Field Programmable Gate Array (FPGA) with a heterogeneous mixture of device primitives. This thesis presents scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. Results of a rigorous analysis of the methodology on multiple test cases are presented. Results are compared against published techniques and show an area savings and execution time savings of 46% each.
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Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183139647.
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Hemmert, Karl S. "Source Level Debugging of Circuits Synthesized from High Level Language Descriptions." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd405.pdf.
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OSBAKK, ALEXANDER, and HARALD VAKSDAL. "New Product Development : A Stage-Gate model in a B2B setting for product development with a low level of technological innovation." Thesis, KTH, Industriell Management, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-190924.
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Företag utvecklar nya produkter för att öka intäkterna och fortsätta vara konkurrenskraftiga. Produktutveckling är ett område det forskats mycket inom och forskningen fokuserar ofta på innovativa produkter. Det ursprungliga problemet för denna uppsats var att göra en undersökning inför utvecklingen av en produkt med låg grad av teknisk innovation. Den tidigare forskningens höga fokus på innovation kombinerat med att uppdragsgivaren inte har några processer för produktutveckling gjorde att uppsatsens omfattning utökades. Denna uppsats presenterar en modell för utveckling av produkter med låg innovation samt en applicering av modellen. Modellen utvecklades genom att studera tidigare litteratur om produktutveckling, främst kring Stage-Gate modeller, och även om kriterier och best-practice inom produktutveckling. Litteraturstudien kombinerades med resultat från intervjuer och resulterade i en modell för utveckling av låginnovativa produkter. Modellen är delad i två delar, den första fokuserar på analys av produktförslaget och den andra fokuserar på att utveckla produkten. Jämfört med tidigare modeller har omfattningen för de olika stegen och gaterna blivit mer fokuserad och tydlig. Den första delen av modellen testades genom att applicera den på det ursprungliga produktförslaget. Testet visade att modellen är passande för den typen av produkter och att de föreslagna generella kriterierna var rimliga. För den specifika produkten visade modellen att produkten var strategiskt passande för företaget och att den är tekniskt genomförbar. De finansiella beräkningarna visade att produkten möjligen inte är tillräckligt attraktiv finansiellt. Några av uppsatsens huvudsakliga slutsatser rör skillnader beroende på hur innovativ produkten är. Processens start skiljer sig signifikant, för innovativa produkter börjar den med en idé och för denna forsknings miljö med ett specifikt förslag. Fokus i finansiella frågor skiljer sig också. Överlag kunde slutsatsen att produktutveckling med en Stage-Gate-metod passar för produkter med låg grad av teknisk innovation dras men det krävs förändringar från tidigare forskningTo increase revenues and continue to stay competitive companies develop new products. Newproduct development is a widely researched field and the focus of the research is often on highly innovative products. The original problem for this thesis was to perform research for the development of a product with a low level of technological innovation. The high focus on innovation in previous research combined with the lack of product development processes in the case company led to a new more extensive scope of this thesis than the original problem. This thesis presents a model for development of products with low level of innovation that has been developed and tested.The model was developed by reviewing previous literature on new product development in general and Stage-Gate models for product development in particular. Literature about criteria and best practices in product development was also studied. The literature review was combined with findings from early interviews and resulted in a development model for low innovative products. The model is divided in two parts, the first focused on analysis of the product suggestion and the second focused on developing the actual product. Compared to previous models, the scope of the stages and gates has been more focused and clear.The first part of the model was tested by applying it to the initial case. The test showed that the model is suitable for a product of that type and that the general criteria proposed was reasonable. For the specific case, the model showed that the product was a strategic fit for the company and that it is technically feasible. The financial calculations showed that the product might not financially attractive enough.Some of the main conclusions of the research are regarding differences depending on how innovative the product is. The starting point differs significantly, with an idea for innovative products and a specific suggestion in the setting of this research. The financial focus also differs. Overall it could be concluded that development with a Stage-Gate approach is suitable for products with low level of technological innovation with some changes from previous literature.
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Andler, Daniel [Verfasser]. "Experimental Investigation of Three-Level Active Neutral Point Clamped Voltage Source Converters using Integrated Gate-Commutated Thyristors / Daniel Andler." München : Verlag Dr. Hut, 2014. http://d-nb.info/1051550092/34.
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Gu, Pei. "Prototyping the simulation of a gate level logic application program interface (API) on an explicit-multi-threaded (XMT) computer." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/2626.
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Thesis (M.S.) -- University of Maryland, College Park, 2005.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Metzdorf, Malte Christoph [Verfasser], Wolfgang [Akademischer Betreuer] Nebel, and Steffen [Akademischer Betreuer] Paul. "Integration einer Zuverlässigkeitsbewertung und -optimierung in den RT- und Gate-Level Entwurfsfluss / Malte Christoph Metzdorf ; Wolfgang Nebel, Steffen Paul." Oldenburg : BIS der Universität Oldenburg, 2018. http://d-nb.info/116415494X/34.
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Andler, Osorio Daniel Andrés [Verfasser]. "Experimental Investigation of Three-Level Active Neutral Point Clamped Voltage Source Converters using Integrated Gate-Commutated Thyristors / Daniel Andler." München : Verlag Dr. Hut, 2014. http://d-nb.info/1051550092/34.
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Bussa, Pavan Kumar. "Accelerating in-system debug of high-level synthesis generated circuits on field-programmable gate arrays using incremental compilation techniques." Thesis, University of British Columbia, 2017. http://hdl.handle.net/2429/62550.
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High-Level Synthesis (HLS) has emerged as a promising technology that allows designers to create a digital hardware circuit using a high-level language like C, allowing even software developers to obtain the benefits of hardware implementation. HLS will only be successful if it is accompanied by a suitable debug ecosystem. There are existing debugging methodologies based on software simulation, however, these are not suitable for finding bugs which occur only during the actual execution of the circuit. Recent efforts have presented in-system debug techniques which allow a designer to debug an implementation, running on a Field-Programmable Gate Array (FPGA) at its actual speed, in the context of the original source code. These techniques typically add instrumentation to store a history of all user variables in a design on-chip. To maximize the effectiveness of the limited on-chip memory and to simplify the debug instrumentation logic, it is desirable to store only selected user variables. Unfortunately, this may lead to multiple debug runs. In existing frameworks, changing the variables to be stored between runs changes the debug instrumentation circuitry. This requires a complete recompilation of the design before reprogramming it on an FPGA.
In this thesis, we quantify the benefits of recording fewer variables and solve the problem of lengthy full compilations in each debug run using incremental compilation techniques present in the commercial FPGA CAD tools. We propose two promising debug flows that use this technology to reduce the debug turn-around time for an in-system debug framework. The first flow, in which the user circuit and instrumentation are co-optimized during compilation, gives the fastest debug clock speeds but suffers in user circuit performance once the debug instrumentation is removed. In the second flow, the optimization of the user circuit is sacrosanct. It is placed and routed first without having any constraints and the debug instrumentation is added later leading to the fastest user circuit clock speeds, but performance suffers slightly during debug. Using either flow, we achieve 40% reduction in debug turn-around times, on average.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Metzdorf, Malte Christoph Verfasser], Wolfgang [Akademischer Betreuer] [Nebel, and Steffen [Akademischer Betreuer] Paul. "Integration einer Zuverlässigkeitsbewertung und -optimierung in den RT- und Gate-Level Entwurfsfluss / Malte Christoph Metzdorf ; Wolfgang Nebel, Steffen Paul." Oldenburg : BIS der Universität Oldenburg, 2018. http://nbn-resolving.de/urn:nbn:de:gbv:715-oops-37239.
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Velagapudi, Ramakrishna. "Modeling and reduction of gate leakage during behavioral synthesis of nanoscale CMOS circuits." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5590/.
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The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).
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Ramani, Shiva Shankar. "Graphical Probabilistic Switching Model: Inference and Characterization for Power Dissipation in VLSI Circuits." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000497.
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Schafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.
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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient. Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACTâ„¢ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates. The mapping to the new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm". To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks: (1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they cannot take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis. To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the specified and the not specified part of the function to a single spectral coefficient. Moreover, the T spectrum is an extension of the known spectra like Walshtype, Adding, Arithmetic, and Reed-Muller spectra to any orthogonal and nonorthogonal transform describing logic functions. Thus, transforms can be constructed that describe certain gate structures, as for example the realizable functions of a FPGA macrocell. This allows the development of special synthesis algorithms for the different types of FPGA architectures. As an exemplification of this method, a complete multi-level synthesis algorithm is introduced for the circuit realization with multiplexer modules, which form the basic macrocell of the Actel ACfâ„¢ FPGA series. Additionally, this dissertation presents the classification of the applications of spectral methods in logic synthesis into three categories: (1) The decomposition of logic functions based on the information obtained by the computation of a single spectrum. As an example the linearization procedure developed by Karpowsky is generalized to incompletely specified multi-output Boolean functions. The linearization procedure is based on the computation of the Rademacher-Walsh spectrum with a following decomposition of the underlying function based on high value spectral coefficients. (2) The circuit realization of a logic function based on the repetitive application of (1). This synthesis method is exemplified by an multi-level synthesis algorithm for multiplexer gates. (3) The realization of a logic function as an AND-EXOR circuit based on a GF 2 (Galois Field (2)) spectrum. The GF 2 transforms exhibit the property that they describe a realization of the underlying function as a two-level AND-EXOR circuit. The Multiple-Valued Input Kronecker Reed-Muller (MIKRM) form is introduced as an application of GF 2 transforms. To overcome the drawbacks of spectral methods concerning the computational complexity and high memory requirements, this dissertation presents a computation method for spectra from disjoint representations. The introduced application of the disjoint cube representation and the Ordered Decision Diagrams for the computation of spectra proves to be an ideal concept. Thus, this dissertation presents general synthesis methods based on new spectral methods that overcome the deficiencies of current logic synthesis methods with respect to the synthesis for FPGAs as well as the computational complexity and memory requirements of spectral methods.
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Ghissoni, Sidinei. "Decomposição de coeficientes trigonométricos para a redução de área e potência em arquiteturas FFT híbridas na base 2." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/67864.
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A crescente utilização de equipamentos móveis que empregam a transformada rápida de Fourier (FFT) nas operações de sinal digital pode ter seu uso restrito devido ao comprometimento da durabilidade da bateria e de suas dimensões. Estas possíveis limitações de uso fazem crescer a necessidade do desenvolvimento de técnicas que visam à otimização nos três requisitos básicos de projeto digital: dissipação de potência, área e atraso. Para tanto, é abordado neste trabalho um método que realiza a implementação de arquiteturas FFT com ênfase na otimização através da decomposição dos coeficientes trigonométricos. No cálculo da FFT, as borboletas desempenham um papel central, uma vez que permitem o cálculo de termos complexos. Neste cálculo, que envolve multiplicações dos dados de entrada com coeficientes trigonométricos apropriados, a otimização das borboletas pode contribuir diretamente para a redução de potência e área. Na técnica proposta são analisados quais são os coeficientes trigonométricos existentes na arquitetura FFT utilizada como base e a escolha para decomposição será o que apresentar o menor custo de implementação em hardware. A decomposição de um coeficiente deve garantir a reconstituição de todos os demais coeficientes necessários para a implementação de toda a arquitetura FFT. Assim, a decomposição diminui o número de coeficientes necessários para reconstruir a FFT original. O conjunto dos novos coeficientes gerados são implementados com apenas somadores\subtratores e deslocamentos através de Multiplicação de Matrizes Constantes (CMM – Constant Matrix Multiplication), associados a um sistema de controle com multiplexadores que controlam o caminho para a correta operação da FFT. As implementações dos circuitos somadores/subtratores são realizadas com métrica no nível de portas lógicas, visando menor atraso e dissipação de potência para topologias com somadores dos tipos CSA (Carry Save Adder) e Ripple carry. Os resultados apresentados pelo método proposto, quando comparados com soluções da literatura, são significativamente satisfatórios, pois minimizaram a dissipação de potência e área em 30% e 24% respectivamente. Os resultados apresentam também a redução de componentes somadores necessários para a implementação de arquiteturas FFTs.The increasing use of mobile devices using the Fast Fourier Transform (FFT) operations in digital signal may have its use restricted due compromising the durability of the battery and its dimensions. These possible limitations on usage makes grow the need to develop techniques aimed at optimizing the three basic requirements of digital design: power dissipation, area and delay. Therefore, this thesis discusses a method that performs the FFT implementation of architectures with emphasis on optimization through decomposition of twiddle factors (trigonometric coefficients). In the FFT the butterflies play a key role, since it allows the computation of complex terms. In this calculation, which involves multiplications of input data with appropriate twiddle factors, optimization of the butterflies can contribute directly to the reduction in power and area. In the proposed technique are analyzed what are the twiddle factors existing in FFT architecture used as a basis and to choose the decomposition that provide the lowest cost hardware implementation. The decomposition of coefficient to must ensure the rebuilding of all the other twiddle factors necessary for the implementation of the architecture FFT. Thus, the decomposition decreases the number of twiddle factors needed to reconstruct the original FFT. The new sets of coefficients generated are implemented with only adders\subtracters and shifting through of Constants Matrix Multiplication (CMM). A control system of multiplexers makes the way for the correct operation of the FFT. The implementations of the circuits arithmetic adders/subtracters are performed at the gate level, seeking lower delay and power consumption for topologies with adders types of CSA (Carry Save Adder) and Ripple carry. The results presented by the proposed method, compared with literature solutions are significantly satisfactory, since minimized power dissipation and area as well as reduced component adders required for implementation architectures FFTs.
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Sasikumar, Anup. "Quantitative spectroscopy of reliability limiting traps in operational gallium nitride based transistors using thermal and optical methods." The Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1415298691.
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Nadimi, Ebrahim. "Quantum Mechanical and Atomic Level ab initio Calculation of Electron Transport through Ultrathin Gate Dielectrics of Metal-Oxide-Semiconductor Field Effect Transistors." Doctoral thesis, Universitätsbibliothek Chemnitz, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200800477.
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The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigatedDie vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden
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Tormo, Borreda Daniel. "Évaluation de dispositifs système-sur-puce pour des applications de type simulateurs temps réel embarqués de systèmes électriques." Thesis, Cergy-Pontoise, 2018. http://www.theses.fr/2018CERG0969/document.
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L’objectif de ce travail de Thèse est d’évaluer les capacités de composants numérique de type Système-sur-Puce (SoC en anglais) pour l’implantation de Simulateurs Temps Réel Embarqués (ERTS en anglais) de systèmes électromécaniques et d’électronique de puissance. En effet, l’utilisation de ces simulateurs n’est pas seulement limitée aux validations matériel dans la boucle (en anglais Hardware-in-the-Loop ou HIL) du système mais doivent également être embarqués avec le contrôleur afin d’assurer plusieurs fonctionnalités additionnelles comme l'observation, l'estimation, commande sans capteur (ou sensorless), le diagnostic ou la surveillance de la santé, commande tolérante aux défauts, etc.La réalisation de ces simulateurs doit néanmoins considérer plusieurs contraintes à plusieurs niveaux de développement : durant la modélisation de la partie du système à simuler en temps-réel, durant la réalisation numérique et enfin durant l’implantation sur le composant numérique utilisé. Ainsi, le travail réalisé durant cette Thèse s’est focalisé sur ce dernier niveau et l’objectif était d’évaluer les capacités temps/ressources des composants de type SoC pour l’implantation de modules ERTS. Ce type de plateformes intègrent dans un même composant de puissants processeurs, un circuit logique programmable (de type Field-Programmable Gate Array ou FPGA), et d’autres périphériques, ce qui offre plusieurs opportunités d’implantation.Afin de pallier les limitations liées au codage VHDL de la partie FPGA, il existe des outils High-Level Synthesis (HLS) qui permettent de programmer ces dispositifs en utilisant des langages à haut niveau d'abstraction comme C, C++ ou SystemC. De plus, en incluant des directives et contraintes au code source, ces outils peuvent produire des implémentations matérielles différentes (architecture totalement combinatoire, « pipeline », architecture parallélisées ou factorisées, arranger les données et leurs formats pour une meilleure utilisation des ressources de mémoire, etc.).Dans le but d’évaluer ces différentes implantations, deux cas d’études ont été choisis : le premier se compose d’un Générateur Asynchrone à Double Alimentation (GADA) et le second d’un Convertisseur Modulaire Multiniveau (ou Modular Multi-level Converter - MMC). Vu que la GADA a une dynamique basse/moyenne (dynamiques électriques et mécaniques), deux versions d’implantations ont été évaluées : (i) une implantation full-software en utilisant seulement les processeurs ARM; et (ii) une implantation full-hardware en utilisant l’outil HLS pour programmer la partie FPGA. Ces deux versions ont été évaluées avec différentes optimisations du compilateur et trois formats de données: 64/32-bit en virgule flottante, et 32-bit en virgule flottante. L’approche mixe software/hardware a également été évaluée à travers la caractérisation des transferts de données entre le processeur et l’IP ERTS implantée dans la partie FPGA. Quant au convertisseur MMC, sa complexité et sa forte dynamique (dynamique de commutation) impose une implantation exclusivement full-hardware. Celle-ci a également été réalisée à base d’outils HLS.Enfin pour la validation expérimentale de ce travail de Thèse, une maquette à base de convertisseur MMC a été construite dans le but de comparer des mesures du système réel avec les résultats fournis par l’IP ERTSThis Doctoral Thesis is a detailed study of how suitable System-on-Chip (SoC) devices are for implementing Embedded Real-Time Simulators (ERTS) of electromechanical and power electronic systems. This emerging class of Real-Time Simulators (RTS) are not only expected for Hardware-in-the-Loop (HIL) validations of systems; but they also have to be embedded within the controller to play several roles like observers, parameter estimation, diagnostic, health monitoring, fault-tolerant and sensorless control, etc.The design of these Intellectual Properties (IP) must rigorously consider a set of constraints at different development stages: (i) during the modeling of the system to be real-time simulated; (ii) during the digital realization of the IP; and also (iii) during its final implementation in the digital platform. Thus, the conducted work of this Thesis focuses specially on this last stage and its aim is to evaluate the time/resource performances of recent SoC devices and study how suitable they are for implementing ERTSs. These kind of digital platforms combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for controlling and monitoring a complete system.One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which needs extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ or SystemC. Moreover, by inserting directives and constraints to the source code, these tools can produce different hardware implementations (e.g. full-combinatorial design, pipelined design, parallel or factorized design, partition or arrange data for a better utilisation of memory resources, etc.).This dissertation is based on the implementation of two representative applications that are well known in our laboratory: a Doubly-fed Induction Generator (DFIG) commonly used as wind turbines; and a Modular Multi-level Converter (MMC) that can be arranged in different configurations and utilized for many different energy conversion purposes. Since the DFIG has low/medium system dynamics (electrical and mechanical ones), both a full-software implementation using solely the ARM processor and a full-hardware implementation using HLS to program the FPGA will be evaluated with different design optimizations and data formats (64/32-bit floating-point and 32-bit fixed-point). Moreover, it will also be investigated whether a system of these characteristics is interesting to be run as a hardware accelerator. Different data transfer options between the Processor System (PS) and the Programmable Logic (PL) have been studied as well for this matter. Conversely, because of its harsh dynamics (switching dynamics), the MMC will be implemented only with a full-hardware approach using HLS tools, as well.For the experimental validation of this Thesis work, a complete MMC test bench has been built from scratch in order to compare the real-world results with its SoC ERTS implementation
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Perera, Lasantha Bernard. "Multi Level Reinjection ac/dc Converters for HVDC." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1085.
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A new concept, the multi level voltage/current reinjection ac/dc conversion, is described in this thesis. Novel voltage and current source converter configurations, based on voltage and current reinjection concepts are proposed. These converter configurations are thoroughly analyzed in their ac and dc system sides. The fundamentals of the reinjection concept is discussed briefly, which lead to the derivation of the ideal reinjection waveform for complete harmonic cancellation and approximations for practical implementation. The concept of multi level voltage reinjection VSC is demonstrated through two types of configurations, based on standard 12-pulse parallel and series connected VSC modified with reinjection bridges and transformers. Firing control strategies and steady state waveform analysis are presented and verified by EMTDC simulations. The multi level current reinjection CSC is also described using two configurations based on standard 12-pulse parallel and series connected CSC modified with associated reinjection circuitry. Firing control strategies and steady state waveform analysis are presented and verified by EMTDC simulations. Taking the advantage of zero current switching in the main bridge valves, achieved through multi level current reinjection, an advanced multi level current reinjection scheme, consisting thyristor main bridges and self-commutated reinjection circuitry is proposed. This hybrid scheme effectively incorporates self-commutated capability into a conventional thyristor converter. The ability of the main bridge valves to commutate without the assistance of a turn-off pulse or line commutating voltage under the zero current condition is explained and verified by EMTDC simulations. Finally, the applications of the MLCR-CSC are discussed in terms of a back to back HVDC link and a long distance HVDC transmission system. The power and control structures and closed loop control strategies are presented. Dynamic simulation is carried out on PSCAD/EMTDC to demonstrate the two systems ability to respond to varying active and reactive power operating conditions.
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Venkataraman, Mahalingam. "Techniques for VLSI Circuit Optimization Considering Process Variations." Scholar Commons, 2009. https://scholarcommons.usf.edu/etd/66.
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Technology scaling has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely power, area, and delay are highly correlated and conflicting in nature. The inception of variations in process parameters have made their relationship intricate and more difficult to optimize. Traditional deterministic methods ignoring variation effects negatively impacts timing yield. A pessimistic worst case consideration of variations, on the other hand, can lead to severe over design. In this context, there is a strong need for re-invention of circuit optimization methods with a statistical perspective.
In this dissertation, we model and develop novel variation aware solutions for circuit optimization methods such as gate sizing, timing based placement and buffer insertion. The uncertainty due to process variations is modeled using interval valued fuzzy numbers and a fuzzy programming based optimization is proposed to improve circuit yield without significant over design. In addition to the statistical optimization methods, we have proposed a novel technique that dynamically detects and creates the slack needed to accommodate the delay due to variations.
The variation aware gate sizing technique is formulated as a fuzzy linear program and the uncertainty in delay due to process variations is modeled using fuzzy membership functions. The timing based placement technique, on the other hand, due to its quadratic dependence on wire length is modeled as nonlinear programming problem. The variations in timing based placement are modeled as fuzzy numbers in the fuzzy formulation and as chance constraints in the stochastic formulation. Further, we have proposed a piece-wise linear formulation for the variation aware buffer insertion and driver sizing (BIDS) problem. The BIDS problem is solved at the logic level, with look-up table based approximation of net lengths for early variation awareness.In the context of dynamic variation compensation, a delay detection circuit is used to identify the uncertainty in critical path delay. The delay detection circuit controls the instance of data capture in critical path memory flops to avoid a timing failure in the presence of variations. In summary, the various formulation and solution techniques developed in this dissertation achieve significantly better optimization compared to related works in the literature. The proposed methods have been rigorously tested on medium and large sized benchmarks to establish the validity and efficacy of the solution techniques.
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Larsson, Karin. "Mälarens vattennivå i ett framtida klimat." Thesis, Uppsala University, Department of Earth Sciences, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-88877.
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The discharge from Lake Mälaren is regulated to keep the lake water level within limits set by a water decree. Despite this, in the year 2000 the lake water level rose above the upper limit. Studies conducted at the climate modeling unit Rossby Centre at the Swedish Meteorological and Hydrological Institute (SMHI) indicate that the inflow to the lake may increase in the future. A flood in the area will, among other things, strike infrastructure and residential districts.
The aim of this study was to investigate the water levels of Lake Mälaren in future climates. In addition to this possible future expansion of the lake discharge though the sluice gates in order to keep water levels below limits set by the water decree and to prevent flooding of the shoreline were discussed. This was done by examining past lake and sea water level data and by using a discharge model to simulate future lake water levels resulting from high future inflow. The study was commissioned by SMHI.
High lake water levels were reproduced fairly well by the discharge model, whereas it was more difficult to draw any coclusions concerning low lake water levels. The examination of data on past lake water levels demonstrated that the regulation of the lake discharge caused a reduction of the highest lake water levels, but above all an increase of low lake water levels. Data on past sea levels in the Baltic Sea showed high values during wintertime. In combination with future high inflow to Lake Mälaren during this season, this indicates that the greatest future flood risk may prevail during wintertime. The conclusion from the simulated future lake water levels was that the lake discharge needs to be expanded to prevent flood in the area. In all scenarios examined in this study, the lake water level will not rise above the upper limit set by the water decree if the discharge is increased to 1 370 m3/s, which almost corresponds to a doubling of the existing discharge of 710 m3/s.
Mälarens utlopp är reglerat för att kunna hålla vattenståndet inom acceptabla gränser. Trots regleringen översteg vattenståndet under vintern 2000/01 den högsta föreskrivna nivån i regleringsbestämmelserna. Studier som bedrivs på klimatforskningsavdelningen Rossby Centre på SMHI pekar på att det framtida inflödet till Mälaren kan komma att bli högre än vad det är idag, något som skulle innebära ännu högre vattennivåer i Mälaren.
En omfattande översvämning av Mälarens stränder går bland annat ut över infrastruktur och bostäder. Problemet idag är att avbördningen genom sjöns utskov är för liten för att förhindra att översvämning uppstår. Att försöka skydda Stockholm mot vattnet med hjälp av skyddsmurar och invallning skulle bli alltför kostsamt. Ett bättre alternativ är istället att öka avtappningskapaciteten genom slussarna.
Syftet med det här arbetet var att undersöka hur vattennivån i Mälaren kan komma att bli i ett framtida förändrat klimat. I samband med detta gavs ett underlag för diskussioner om kommande utbyggnader av Mälarens utlopp för att kunna hålla vattennivån under vattendomens högsta föreskrivna nivå även vid ett högre framtida inflöde. Detta uppnåddes genom att genomföra analyser med historiska vattenståndsdata och genom att använda en beräkningsmodell för avtappning, Mälarmodellen, för simulering av ett antal framtida inflödessituationer. Arbetet har genomförts på uppdrag av SMHI.
Avtappningsmodellen återskapade de höga vattenstånden förhållandevis väl, medan det var svårare att bedöma hur precist den beräknade de allra lägsta vattennivåerna. Ett viktigt resultat från analysen med historiska data var att införandet av regleringen av Mälarens utlopp bidrog till att sänka de höga vattenstånden, men framförallt till att höja de låga. Ett annat resultat från studierna av historiska data var att vattenståndet i Östersjön antar högst nivåer under vintern. Detta i kombination med ett framtida högre inflöde till Mälaren under denna årstid indikerar att störst risk för översvämning kan komma att föreligga under vintern. För att säkert kunna hålla Mälarens vattennivå inom acceptabla gränser måste sjöns utlopp byggas ut. I alla scenarier som har undersökts i det här arbetet kan vattennivån hållas under den högsta föreskrivna nivån om avbördningen utökas till 1 370 m3/s. Det krävs alltså nästan en fördubbling av dagens avbördningskapacitet på 710 m3/s.
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Lorusso, Marco. "FPGA implementation of muon momentum assignment with machine learning at the CMS level-1 trigger." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23211/.
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With the advent of the High-Luminosity phase of the LHC (HL-LHC), the instantaneous luminosity of the Large Hadron Collider at CERN is expected to increase up to around 7.5 x 10^34 cm^-2s^-1. Therefore, new strategies for data acquisition and processing will be necessary, in preparation for the higher number of signals produced inside the detectors, that would eventually make the trigger and readout electronics currently in use at the LHC experiments obsolete. In the context of an upgrade of the trigger system of the Compact Muon Solenoid (CMS), new reconstruction algorithms, aiming for an improved performance, are being developed. For what concerns the online tracking of muons, one of the figures that is being improved is the accuracy of the transverse momentum (pT) measurement.
Machine Learning techniques have already been considered as a promising solution for this problem, as they make possible, with the use of more information collected by the detector, to build models able to predict the pT with an improved precision.
In this Master Thesis, a step further in increasing the performance of the pT assignment is taken by implementing such models onto a type of programmable processing unit called Field Programmable Gate Array (FPGA). FPGAs, indeed, allow a smaller latency with a relatively small loss in accuracy with respect to traditional inference algorithms running on a CPU, both important aspects for a trigger system. The analysis carried out in this work uses data obtained through Monte Carlo simulations of muons crossing the barrel region of the CMS muon chambers, and compare the results with the pT assigned by the current (Phase-1) CMS Level 1 Barrel Muon Track Finder (BMTF) trigger system.
Together with the final results, the steps needed to create an accelerated inference machine for muon pT are also presented.
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Wilson, Veas Alan Hjalmar [Verfasser], Steffen [Gutachter] Bernet, Mariusz [Gutachter] Malinowski, and Steffen [Akademischer Betreuer] Bernet. "Investigation of Multi-Level Neutral Point Clamped Voltage Source Converters using Isolated Gate Bipolar Transistor Modules / Alan Hjalmar Wilson Veas ; Gutachter: Steffen Bernet, Mariusz Malinowski ; Betreuer: Steffen Bernet." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/1226899463/34.
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Rößler, Marko. "Parallel Hardware- and Software Threads in a Dynamically Reconfigurable System on a Programmable Chip." Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-129626.
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Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken at runtime is given.
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Zbierska, Inga Jolanta. "Study of electrical characteristics of tri-gate NMOS transistor in bulk technology." Thesis, Lyon 1, 2014. http://www.theses.fr/2014LYO10282/document.
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Afin de dépasser la limite d'échelle, il existe une solution innovante qui permet de fabriquer des structures multi-grilles. Ainsi, un NMOSFET composé de trois grilles indépendantes fabriquées dans la technologie CMOS. En dehors de leur forme, géométrique, le transistor multi-grille est similaire à une structure classique. Une multi-grille NMOSFET peut être fabriquée par l'intégration de tranchées de polysilicium. Ces tranchées sont utilisées dans diverses applications telles que les mémoires DRAM, électronique de puissance ou de capteurs d'image. Les capteurs d'image présentent le problème des charges parasites entre les pixels, appelées diaphonie. Les tranchées sont l'une des solutions qui réduisent ce phénomène. Ces tranchées assurent l'isolation électrique sur toute la matrice des pixels. Nous avons étudié ses caractéristiques en utilisant des mesures I-V, méthode du split C-V et de pompage de charge à deux et à trois niveaux. Son multi-seuil caractéristique a été vérifié. Nous n'avons observé aucune dégradation significative de ces caractéristiques grâce à l'intégration des tranchées. La structure a été simulée par la méthode des éléments finis en 3D via le logiciel TCAD. Ses caractéristiques électriques ont été simulées et confrontées avec les résultats obtenus à partir de mesures électriques. La tension de seuil et la longueur de canal effective ont été extraites. Sa mobilité effective et les pièges de l'interface Si/SiO2 ont également été simulés ou calculés. En raison des performances électriques satisfaisantes et d'un bon rendement, nous avons remarqué que ce dispositif est une solution adéquate pour les applications analogiques grâce aux niveaux de tension multi-seuilOne of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages
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Jarrah, Amin. "Development of Parallel Architectures for Radar/Video Signal Processing Applications." University of Toledo / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1415806786.
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Arvidsson, Klas. "Simulering av miljoner grindar med Count Algoritmen." Thesis, Linköping University, Department of Computer and Information Science, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2476.
Full textAbstract:
A key part in the development and verification of digital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a large number of gates. As today’s digital zesigns constantly grow in size (number of gates), and that trend shows no signs to end, faster simulators handling millions of gates are needed.
We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist representation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the performance to the speed of main memory.
We have selected the Counting Algorithm to implement the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated in a simple and standard way.
The report describes the issues and solutions encountered and evaluate the resulting simulator. MICA simulates a SPARC architecture processor called Leon. Larger netlists are achieved by simulating several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA this design correspond to 2.5 million gates.
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Lin, Yu Colin, and 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.
Full textAbstract:
Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step.
ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer.
Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption
spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required.
Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X.published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
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Rullmann, Markus. "Models, Design Methods and Tools for Improved Partial Dynamic Reconfiguration." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-61526.
Full textAbstract:
Partial dynamic reconfiguration of FPGAs has attracted high attention from both academia and industry in recent years. With this technique, the functionality of the programmable devices can be adapted at runtime to changing requirements. The approach allows designers to use FPGAs more efficiently: E. g. FPGA resources can be time-shared between different functions and the functions itself can be adapted to changing workloads at runtime. Thus partial dynamic reconfiguration enables a unique combination of software-like flexibility and hardware-like performance. Still there exists no common understanding on how to assess the overhead introduced by partial dynamic reconfiguration. This dissertation presents a new cost model for both the runtime and the memory overhead that results from partial dynamic reconfiguration. It is shown how the model can be incorporated into all stages of the design optimization for reconfigurable hardware. In particular digital circuits can be mapped onto FPGAs such that only small fractions of the hardware must be reconfigured at runtime, which saves time, memory, and energy. The design optimization is most efficient if it is applied during high level synthesis. This book describes how the cost model has been integrated into a new high level synthesis tool. The tool allows the designer to trade-off FPGA resource use versus reconfiguration overhead. It is shown that partial reconfiguration causes only small overhead if the design is optimized with regard to reconfiguration cost. A wide range of experimental results is provided that demonstrates the benefits of the applied methodPartielle dynamische Rekonfiguration von FPGAs hat in den letzten Jahren große Aufmerksamkeit von Wissenschaft und Industrie auf sich gezogen. Die Technik erlaubt es, die Funktionalität von progammierbaren Bausteinen zur Laufzeit an veränderte Anforderungen anzupassen. Dynamische Rekonfiguration erlaubt es Entwicklern, FPGAs effizienter einzusetzen: z.B. können Ressourcen für verschiedene Funktionen wiederverwendet werden und die Funktionen selbst können zur Laufzeit an veränderte Verarbeitungsschritte angepasst werden. Insgesamt erlaubt partielle dynamische Rekonfiguration eine einzigartige Kombination von software-artiger Flexibilität und hardware-artiger Leistungsfähigkeit. Bis heute gibt es keine Übereinkunft darüber, wie der zusätzliche Aufwand, der durch partielle dynamische Rekonfiguration verursacht wird, zu bewerten ist. Diese Dissertation führt ein neues Kostenmodell für Laufzeit und Speicherbedarf ein, welche durch partielle dynamische Rekonfiguration verursacht wird. Es wird aufgezeigt, wie das Modell in alle Ebenen der Entwurfsoptimierung für rekonfigurierbare Hardware einbezogen werden kann. Insbesondere wird gezeigt, wie digitale Schaltungen derart auf FPGAs abgebildet werden können, sodass nur wenig Ressourcen der Hardware zur Laufzeit rekonfiguriert werden müssen. Dadurch kann Zeit, Speicher und Energie eingespart werden. Die Entwurfsoptimierung ist am effektivsten, wenn sie auf der Ebene der High-Level-Synthese angewendet wird. Diese Arbeit beschreibt, wie das Kostenmodell in ein neuartiges Werkzeug für die High-Level-Synthese integriert wurde. Das Werkzeug erlaubt es, beim Entwurf die Nutzung von FPGA-Ressourcen gegen den Rekonfigurationsaufwand abzuwägen. Es wird gezeigt, dass partielle Rekonfiguration nur wenig Kosten verursacht, wenn der Entwurf bezüglich Rekonfigurationskosten optimiert wird. Eine Anzahl von Beispielen und experimentellen Ergebnissen belegt die Vorteile der angewendeten Methodik
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Stamenkovich, Joseph Allan. "Enhancing Trust in Autonomous Systems without Verifying Software." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/89950.
Full textAbstract:
The complexity of the software behind autonomous systems is rapidly growing, as are the
applications of what they can do. It is not unusual for the lines of code to reach the millions,
which adds to the verification challenge. The machine learning algorithms involved are often
"black boxes" where the precise workings are not known by the developer applying them, and
their behavior is undefined when encountering an untrained scenario. With so much code, the
possibility of bugs or malicious code is considerable. An approach is developed to monitor and
possibly override the behavior of autonomous systems independent of the software controlling
them. Application-isolated safety monitors are implemented in configurable hardware to
ensure that the behavior of an autonomous system is limited to what is intended. The sensor
inputs may be shared with the software, but the output from the monitors is only engaged
when the system violates its prescribed behavior. For each specific rule the system is expected
to follow, a monitor is present processing the relevant sensor information. The behavior is
defined in linear temporal logic (LTL) and the associated monitors are implemented in a
field programmable gate array (FPGA). An off-the-shelf drone is used to demonstrate the
effectiveness of the monitors without any physical modifications to the drone. Upon detection
of a violation, appropriate corrective actions are persistently enforced on the autonomous
system.Master of Science
Autonomous systems are surprisingly vulnerable, not just from malicious hackers, but from design errors and oversights. The lines of code required can quickly climb into the millions, and the artificial decision algorithms can be inscrutable and fully dependent upon the information they are trained on. These factors cause the verification of the core software running our autonomous cars, drones, and everything else to be prohibitively difficult by traditional means. Independent safety monitors are implemented to provide internal oversight for these autonomous systems. A semi-automatic design process efficiently creates error-free monitors from safety rules drones need to follow. These monitors remain separate and isolated from the software typically controlling the system, but use the same sensor information. They are embedded in the circuitry and act as their own small, task-specific processors watching to make sure a particular rule is not violated; otherwise, they take control of the system and force corrective behavior. The monitors are added to a consumer off-the-shelf (COTS) drone to demonstrate their effectiveness. For every rule monitored, an override is triggered when they are violated. Their effectiveness depends on reliable sensor information as with any electronic component, and the completeness of the rules detailing these monitors.
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Luo, Cheng Computer Science & Engineering Faculty of Engineering UNSW. "Robust object tracking using the particle filtering and level set methods." Publisher:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/43682.
Full textAbstract:
Robust object tracking plays a central role in many applications of image processing, computer vision and automatic control. In this thesis, robust object tracking under complex environments, including heavy clutters in the background, low resolution of the image sequences and non-stationary camera, has been studied. The interest of this study stems from the improvement of the performance of visual tracking using particle filtering. A Geometric Active contour-based Tracking Estimator, namely GATE, has been developed in order to tackle the problems in robust object tracking where the existence of multiple features or good object detection is not guaranteed. GATE combines particle filtering and the level set-based active contour method. The particle filtering method is able to deal with nonlinear and non-Gaussian recursive estimation problems, and the level set-based active contour method is capable of classifying state space of particle filtering under the methodology of one class classification. By integrating this classifier into the particle filtering, geometric information introduced by the shape prior and pose invariance of the tracked object in the level set-based active contour method can be utilised to prevent the particles corresponding to outlier measurements from being heavily reweighted. Hence, this procedure reshapes and refines the posterior distribution of the particle filtering. To verify the performance of GATE, the performance of the standard particle filter is compared with that of GATE. Since video sequences in different applications are usually captured by diverse devices, GATE and the standard particle filters with the identical initialisation are studied on image sequences captured by the handhold, stationary and PTZ camera, respectively. According to experimental results, even though a simple color observation model based on the Hue-Saturation-Value (HSV) color histogram is adopted, the newly developed. GATE significantly improves the performance of the particle filtering for object tracking in complex environments. Meanwhile, GATE initialises a novel approach to tackle the impoverishment problem for recursive Bayesian estimation using sampling method.
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Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.
Full textAbstract:
Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.QC 20140609
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Donachy, Paul. "Design and implementation of a high level image processing machine using reconfigurable hardware." Thesis, Queen's University Belfast, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337688.
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Rößler, Marko. "Dynamische Anwendungspartitionierung für heterogene adaptive Computersysteme." Doctoral thesis, Universitätsbibliothek Chemnitz, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-151837.
Full textAbstract:
Die Dissertationsschrift stellt eine Methodik und die Infrastruktur zur Entwicklung von dynamisch verteilbaren Anwendungen für heterogene Computersysteme vor. Diese Computersysteme besitzen vielfältige Rechenwerke, die Berechnungen in den Domänen Software und Hardware realisieren. Als erster Schritt wird ein übergreifendes und integriertes Vorgehen für den Anwendungsentwurf auf Basis eines abstrakten “Single-Source” Ansatzes entwickelt. Durch die Virtualisierung der Rechenwerke wird die preemptive Verteilung der Anwendungen auch über die Domänengrenzen möglich. Die Anwendungsentwicklung für diese Computersysteme bedarf einer durchgehend automatisierten Entwurfsunterstützung. In der Arbeit wird der dazu vorgeschlagene Ansatz formalisiert und eine neuartige Unterbrechungspunktsynthese entwickelt, die ein hinsichtlich Zeit und Fläche optimiertes, präemptives Verhalten für beliebige Anwendungsbeschreibungen generiert. Das Verfahren wird beispielhaft implementiert und mittels einer FPGA- Prototypenplattform mit Linux-basierter Laufzeitumgebung anhand dreier Fallbeispiele unterschiedlicher Komplexität validiert und evaluiertThis thesis introduces a methodology and infrastructure for the development of dynamically distributable applications on heterogeneous computing systems. Such systems execute computations using resources from both the hardware and the software domain. An integrated approach based on an abstract single-source design entry is developed that allows preemptive partitioning through virtualization of computing resources across the boundaries of differing computational domains. Application design for heterogeneous computing systems is a complex task that demands aid by electronic design automation tools. This work provides a novel synthesis approach for breakpoints that generates preemptive behaviour for arbitrary applications. The breakpoint scheme is computed for a minimal additional resource utilization and given timing constraints. The approach is implemented on an FPGA prototyping platform driven by a Linux based runtime environment. Evaluation and validation of the approach have been carried out using three different application examples
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Alotaibi, Khalid F. D. "A high level hardware description environment for FPGA-based image processing applications." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.287288.
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Makni, Mariem. "Un framework haut niveau pour l'estimation du temps d'exécution, des ressources matérielles et de la consommation d'énergie dans les accélérateurs à base de FPGA." Thesis, Valenciennes, 2018. http://www.theses.fr/2018VALE0042.
Full textAbstract:
Les systèmes embarqués sur puce (SoC: Systems-on-Chip) sont devenus de plus en plus complexes grâce à l’évolution de la technologie des circuits intégrés. Les applications récentes nécessitent des systèmes à haute performances. Les FPGAs (Field Programmable Gate Arrays) peuvent répondre à ces besoins. On retrouve ces FPGA dans de nombreux domaines d’application : systèmes embarqués, télécommunications, traitement du signal et des images, serveurs de calcul HPC, etc. De nombreux défis sont rencontrés par les concepteurs de ces applications, parmi lesquels : le développement des applications complexes, la vérification du code, la nécessité d’automatiser le processus de conception pour augmenter la productivité et satisfaire la contrainte du « time-to-market ». Récemment, la synthèse de haut niveau (ou HLS) est considérée comme une solution efficace pour résoudre ces défis en utilisant un niveau d’abstraction plus élevé. En effet, cette technique permet de transformer automatiquement une spécification du système en C, C++, systemC en une implémentation au niveau transfert de registre (ou RTL pour Register Transfer Level). Les outils de HLS offrent un espace de solutions avec un grand nombre d’optimisations possibles au niveau du code comme l’utilisation du dépliage de boucles, le flot de données et partitionnement des tableaux, etc. Le concepteur doit explorer toutes ces alternatives et mesurer les performances obtenues en termes de temps d’exécution, de ressources matérielles, et de consommation d’´energie. Dans ce travail de thèse, nous avons utilisé les accélérateurs matériels à base de FPGAs et nous avons développé l’outil HAPE. Ce dernier permet d’aider les concepteurs à estimer la performance, la surface et l’énergie pour diverses configurations au niveau du code source. L’approche proposée comprend quatre contributions principales : (i) Nous avons proposé un modèle analytique de haut niveau pour estimer le temps de communications et le temps d’exécution total (ii) nous avons proposé un modèle analytique pour estimer les différentes ressources du FPGAs (DSPs, LUTs, FFs, BRAMs), (iii) nous avons proposé un modèle analytique pour estimer la consommation d’énergie basé sur l’utilisation du matériel (BRAMs, FFs, LUTs, etc) en explorant l’espace de solutions pour les différentes optimisations, (iv) Nous avons enfin proposé un environnement de conception (HAPE) permettant l’exploration des 3 critères : temps, ressources matérielles et consommation de puissance. L’approche proposée dans cette thèse est basée sur une analyse dynamique du code exécutée pour extraire les dépendances des données. Cette approche augmente la précision dans l’estimation du : temps de communication, de la consommation des ressources matérielles et de la consommation d’énergie dans les accélérateurs à base de FPGA. HAPE permet d’estimer ces paramètres avec une erreur inférieure à 5% par rapport aux implémentations RTLIn recent years, the complexity of system-on-chip (SoC) designs has been dramatically increased. As a result, the increased demands for high performance and minimal power/area costs for embedded streaming applications need to find new emerged architectures. The trend towards FPGA-based accelerators is giving a great potential of computational power and performance required for diverse applications. The advantages of such architectures result from many sources. The most important advantage stems from more efficient adaptation to the various application needs. In fact, many compute-intensive applications demand different levels of processing capabilities and energy consumption trade-offs which may be satisfied by using FPGA-based accelerators. Current researches in performance, area and power analysis rely on register-transfer level (RTL) based synthesis flows to produce accurate estimates. However, complex hardware programming model (Verilog or VHDL) makes FPGA development a time-consuming process even as the time-to-market constraints continue to tighten. Such techniques not only require advanced hardware expertise and time but are also difficult to use, making large design space exploration and time-to-market costly. High-Level Synthesis (HLS) technology has been emerged in the last few years as a solution to address these problems and managing design complexity at a more abstract level. This technique aims to bridge the gap between the traditional RTL design process and the ever-increasing complexity of applications. The important advantage of HLS tools is the ability to automatically generate RTL implementations from high-level specifications (e.g., C/C++/SystemC). The HLS tools provide various optimization pragmas such as loop unrolling, loop pipelining, dataflow, array partitioning, etc. Unfortunately, the large design space resulting from the various combinations of pragmas makes exhaustive design space exploration prohibitively time-consuming with HLS tools. In addition, to thoroughly evaluate such architectures, designers must perform large design space exploration to understand the tradeoffs across the entire system, which is currently infeasible due to the lack of a fast simulation infrastructure for FPGA-based accelerators. Hence, there is a clear need for a pre-RTL and high-level framework to enable rapid design space exploration for FPGA-based accelerators
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Mitra, Abhishek. "Acceleration of streaming applications on FPGAs from high level constructs." Diss., [Riverside, Calif.] : University of California, Riverside, 2008. http://proquest.umi.com/pqdweb?index=0&did=1663077901&SrchMode=2&sid=1&Fmt=2&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1268251432&clientId=48051.
Full textAbstract:
Thesis (Ph. D.)--University of California, Riverside, 2008.Includes abstract. Title from first page of PDF file (viewed March 8, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 150-168). Also issued in print.