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Journal articles on the topic 'Gate-level'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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1

Saigo, T., K. Niwa, T. Ohto, S. Kurosawa, and T. Takada. "A triple-level wired 24K-gate CMOS gate array." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1005–11. http://dx.doi.org/10.1109/jssc.1985.1052428.

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2

Smith, S. C., R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson. "Delay-insensitive gate-level pipelining." Integration 30, no. 2 (October 2001): 103–31. http://dx.doi.org/10.1016/s0167-9260(01)00013-x.

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3

Fan, X., W. R. Moore, C. Hora, and G. Gronthoud. "Extending gate-level diagnosis tools to CMOS intra-gate faults." IET Computers & Digital Techniques 1, no. 6 (2007): 685. http://dx.doi.org/10.1049/iet-cdt:20060206.

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4

Chatterjee, Debapriya, Andrew Deorio, and Valeria Bertacco. "Gate-Level Simulation with GPU Computing." ACM Transactions on Design Automation of Electronic Systems 16, no. 3 (June 2011): 1–26. http://dx.doi.org/10.1145/1970353.1970363.

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5

Golić, J. Dj, and R. Menicocci. "Universal masking on logic gate level." Electronics Letters 40, no. 9 (2004): 526. http://dx.doi.org/10.1049/el:20040385.

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6

BAE, T. I., J. W. KIM, and Y. H. KIM. "New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 12 (December 1, 2008): 3488–96. http://dx.doi.org/10.1093/ietfec/e91-a.12.3488.

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7

RAEMY, F., and W. H. HAGER. "HYDRAULIC LEVEL CONTROL BY HINGED FLAP GATE." Proceedings of the Institution of Civil Engineers - Water Maritime and Energy 130, no. 2 (June 1998): 95–103. http://dx.doi.org/10.1680/iwtme.1998.30478.

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8

., Md Moyeed Abrar. "LOGIC GATE BASED AUTOMATIC WATER LEVEL CONTROLLER." International Journal of Research in Engineering and Technology 03, no. 04 (April 25, 2014): 477–82. http://dx.doi.org/10.15623/ijret.2014.0304085.

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9

Cabodi, G., S. Gai, and M. Sonza Reorda. "A transputer-based gate-level fault simulator." Microprocessing and Microprogramming 30, no. 1-5 (August 1990): 529–34. http://dx.doi.org/10.1016/0165-6074(90)90294-j.

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10

Takach, A. R., and N. K. Jha. "Easily testable gate-level and DCVS multipliers." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 7 (July 1991): 932–42. http://dx.doi.org/10.1109/43.87603.

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11

Cheng, Kwang-Ting. "Gate-level test generation for sequential circuits." ACM Transactions on Design Automation of Electronic Systems 1, no. 4 (October 1996): 405–42. http://dx.doi.org/10.1145/238997.238999.

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12

Xiao, Ran, and Chunhong Chen. "Gate-Level Circuit Reliability Analysis: A Survey." VLSI Design 2014 (July 10, 2014): 1–12. http://dx.doi.org/10.1155/2014/529392.

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Circuit reliability has become a growing concern in today’s nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.

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13

Pandian, V., and V. Kumar. "Single‐gate deep level transient spectroscopy technique." Journal of Applied Physics 67, no. 1 (January 1990): 560–63. http://dx.doi.org/10.1063/1.345192.

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14

Viamontes, George F., Igor L. Markov, and John P. Hayes. "Improving Gate-Level Simulation of Quantum Circuits." Quantum Information Processing 2, no. 5 (October 2003): 347–80. http://dx.doi.org/10.1023/b:qinp.0000022725.70000.4a.

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15

Monaghan, Sean. "A gate-level reconfigurable Monte carlo processor." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 2 (August 1993): 139–53. http://dx.doi.org/10.1007/bf01607878.

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16

Bareisa, Eduardas, Vacius Jusas, Kestutis Motiejunas, and Rimantas Seinauskas. "Test generation at the algorithm-level for gate-level fault coverage." Microelectronics Reliability 48, no. 7 (July 2008): 1093–101. http://dx.doi.org/10.1016/j.microrel.2008.03.017.

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17

JI, YING-HUA, JU-JU HU, and SHI-HUA CAI. "INVESTIGATION COMPARISON ON THE GATE SPEED OF THREE-LEVEL AND TWO-LEVEL QUANTUM NOT GATES WITH ASYMMETRIC POTENTIAL OF rf-SQUID." Modern Physics Letters B 21, no. 19 (August 20, 2007): 1261–70. http://dx.doi.org/10.1142/s0217984907013699.

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We investigate the relation between the speed of quantum NOT gate and the asymmetry or detuning of the potential in system of the interaction of a two-level rf-SQUID qubit with a classical microwave pulse. The rf-SQUID is characterized by an asymmetric double well potential that gives rise to diagonal matrix elements. Then in resonance, we compare the gate speeds for three-level and two-level quantum NOT gates. We show that in general, a three-level gate is much faster than the conventional two-level gate.

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18

Kadirova, Mukaddas-Gaukhar. "Hydraulic automatic regulator of level with flexible working bodies." E3S Web of Conferences 264 (2021): 03039. http://dx.doi.org/10.1051/e3sconf/202126403039.

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To eliminate the shortcomings of the known hydraulic autoregulators of the water level, together with Ya. V. Bochkarev, we developed a design of a hydraulic autoregulator of the level with flexible working bodies, combined with an automatic gate for washing sediments, which provides the discharge of floating bodies and bottom sediments in front of the partition structure. To ensure stable vibration-free operation of this hydro-automatic level controller, the task was set to justify the shape and size of the elements of its main gate and the gate-automatic washing of deposits and determine the throughput of the automatic gate washing of deposits. As a result of solving this problem, for the stable vibration-free operation of the hydro-automatic level controller, a non-vacuum shape of the profile of the spillway part of its main gate was adopted, the shapes and sizes of other gate elements were justified, and a theoretical formula for the throughput of the automatic gate for washing sediments was obtained, taking into account the lateral outflows.

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19

Han, Sangwoo, Junho Lee, Byung-Su Kim, and Juho Kim. "An Accurate Gate-level Stress Estimation for NBTI." JSTS:Journal of Semiconductor Technology and Science 13, no. 2 (April 30, 2013): 139–44. http://dx.doi.org/10.5573/jsts.2013.13.2.139.

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20

Meade, Travis, Shaojie Zhang, and Yier Jin. "IP protection through gate-level netlist security enhancement." Integration 58 (June 2017): 563–70. http://dx.doi.org/10.1016/j.vlsi.2016.10.014.

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21

Hoppe, B. "Circuit optimization: Gate level modelling and multiobjective programming." Microprocessing and Microprogramming 25, no. 1-5 (January 1989): 171–76. http://dx.doi.org/10.1016/0165-6074(89)90191-9.

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22

Hu, Wei, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner. "Theoretical Fundamentals of Gate Level Information Flow Tracking." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 8 (August 2011): 1128–40. http://dx.doi.org/10.1109/tcad.2011.2120970.

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23

Chih-Shun Ding, Chi-Ying Tsui, and M. Pedram. "Gate-level power estimation using tagged probabilistic simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 11 (1998): 1099–107. http://dx.doi.org/10.1109/43.736184.

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24

Chakraborty, Angshuman, and Sambhu Nath Pradhan. "Gate level leakage minimisation at 90 nm technology." International Journal of Computer Aided Engineering and Technology 5, no. 4 (2013): 375. http://dx.doi.org/10.1504/ijcaet.2013.056816.

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25

Baldiotti, M. C., and D. M. Gitman. "Four-level systems and a universal quantum gate." Annalen der Physik 17, no. 7 (July 1, 2008): 450–59. http://dx.doi.org/10.1002/andp.200810303.

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26

Hu, Wei, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. "Gate-Level Information Flow Tracking for Security Lattices." ACM Transactions on Design Automation of Electronic Systems 20, no. 1 (November 18, 2014): 1–25. http://dx.doi.org/10.1145/2676548.

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27

Tiwari, Mohit, Xun Li, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T. Chong, and Timothy Sherwood. "Gate-Level Information-Flow Tracking for Secure Architectures." IEEE Micro 30, no. 1 (January 2010): 92–100. http://dx.doi.org/10.1109/mm.2010.17.

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28

Pal, D., S. Pal, and D. N. Bose. "Deep level transient spectroscopy of anisotropic semiconductor GaTe." Bulletin of Materials Science 17, no. 4 (August 1994): 347–54. http://dx.doi.org/10.1007/bf02745221.

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29

Ubar, Raimund, Jaan Raik, Eero Ivask, and Marina Brik. "Defect-oriented mixed-level fault simulation in digital systems." Facta universitatis - series: Electronics and Energetics 15, no. 1 (2002): 123–36. http://dx.doi.org/10.2298/fuee0201123u.

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A new method for mixed level defect-oriented fault simulation of Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gate- and RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.

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30

Suntaranont, Benya, Somrawee Aramkul, Manop Kaewmoracharoen, and Paskorn Champrasert. "Water Irrigation Decision Support System for Practical Weir Adjustment Using Artificial Intelligence and Machine Learning Techniques." Sustainability 12, no. 5 (February 27, 2020): 1763. http://dx.doi.org/10.3390/su12051763.

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This research proposes a decision support system for weir sluice gate level adjusting. The proposed system, named AWARD (Appropriate Weir Adjustment with Water Requirement Deliberation), is composed of three modules, which are (1) water level prediction, (2) sluice gates setting period estimation, and (3) sluice gates level adjusting calculation. The AWARD system applies an artificial neural network technique for water level prediction, a fuzzy logic control algorithm for sluice gate setting period estimation, and hydraulics equations for sluice gate level adjusting. The water requirements and supplies are deducted from the field-survey and telemetry stations in Chiang Rai Province, Thailand. The results show that the proposed system can accurately estimate the water volume. Water level prediction shows high accuracy. The standard error of prediction (SEP) is 2.58 cm and the mean absolute percentage error (MAPE) is 7.38%. The sluice gate setting period is practically adjusted. The sluice gate level is adjusted according to the water requirement.

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31

Sedaghat, Reza, Mayuri Kunchwar, Raha Abedi, and Reza Javaheri. "Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates." Microelectronics Reliability 46, no. 12 (December 2006): 2149–58. http://dx.doi.org/10.1016/j.microrel.2005.12.005.

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32

Cai, Shuo, Ji-shun Kuang, Tie-qiao Liu, and Ying-bo Zhou. "An Efficient Reliability Estimation Method for Gate-level Circuit." Journal of Electronics & Information Technology 35, no. 5 (February 14, 2014): 1262–66. http://dx.doi.org/10.3724/sp.j.1146.2012.01169.

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33

Amagasaki, Motoki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, and Hiroto Ito. "R-GCN Based Function Inference for Gate-level Netlist." IPSJ Transactions on System LSI Design Methodology 13 (2020): 69–71. http://dx.doi.org/10.2197/ipsjtsldm.13.69.

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34

KIMURA, Yusuke, Amir Masoud GHAREHBAGHI, and Masahiro FUJITA. "Signal Selection Methods for Debugging Gate-Level Sequential Circuits." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 12 (December 1, 2019): 1770–80. http://dx.doi.org/10.1587/transfun.e102.a.1770.

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35

Cioffi, Giacomo, Paolo Libri, and Alfredo Micarelli. "A gate level simulator for MS-DOS personal computers." Microprocessing and Microprogramming 18, no. 1-5 (December 1986): 47–51. http://dx.doi.org/10.1016/0165-6074(86)90023-2.

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36

Hu, Wei, Baolei Mao, Jason Oberg, and Ryan Kastner. "Detecting Hardware Trojans with Gate-Level Information-Flow Tracking." Computer 49, no. 8 (August 2016): 44–52. http://dx.doi.org/10.1109/mc.2016.225.

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37

Svensson, C. M., and R. Tjarnstrom. "Switch-level simulation and the pass transistor EXOR gate." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 9 (1988): 994–97. http://dx.doi.org/10.1109/43.7797.

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38

Kasper, Roland, and Thomas Reinemann. "Gate Level Implementation of High Speed Controllers and Filters." IFAC Proceedings Volumes 34, no. 22 (November 2001): 170–75. http://dx.doi.org/10.1016/s1474-6670(17)32932-4.

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39

Sharma, Satinder K., B. Prasad, Dinesh Kumar, and Raj kumar. "Alteration of gate oxides thickness for SOC level integration." Materials Science in Semiconductor Processing 12, no. 3 (June 2009): 99–105. http://dx.doi.org/10.1016/j.mssp.2009.08.003.

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40

M. S, Thilagavathy, and GopalaKrishnan S. "Des IGN of Inexact Circuits using Gate-Level Pruning." International Journal of Electronics and Communication Engineering 4, no. 12 (December 25, 2017): 1–3. http://dx.doi.org/10.14445/23488549/ijece-v4i12p101.

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41

LaRose, Ryan. "Overview and Comparison of Gate Level Quantum Software Platforms." Quantum 3 (March 25, 2019): 130. http://dx.doi.org/10.22331/q-2019-03-25-130.

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Quantum computers are available to use over the cloud, but the recent explosion of quantum software platforms can be overwhelming for those deciding on which to use. In this paper, we provide a current picture of the rapidly evolving quantum computing landscape by comparing four software platforms - Forest (pyQuil), Qiskit, ProjectQ, and the Quantum Developer Kit (Q#) - that enable researchers to use real and simulated quantum devices. Our analysis covers requirements and installation, language syntax through example programs, library support, and quantum simulator capabilities for each platform. For platforms that have quantum computer support, we compare hardware, quantum assembly languages, and quantum compilers. We conclude by covering features of each and briefly mentioning other quantum computing software packages.

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42

Bagrodia, Rajive, Yu-an Chen, Vikas Jha, and Nicki Sonpar. "Parallel gate-level circuit simulation on shared memory architectures." ACM SIGSIM Simulation Digest 25, no. 1 (July 1995): 170–74. http://dx.doi.org/10.1145/214283.214336.

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43

Chunhong Chen, A. Srivastava, and M. Sarrafzadeh. "On gate level power optimization using dual-supply voltages." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 5 (October 2001): 616–29. http://dx.doi.org/10.1109/92.953496.

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44

Walsh, Sean, and Robert Miskewitz. "Impact of sea level rise on tide gate function." Journal of Environmental Science and Health, Part A 48, no. 4 (March 2013): 453–63. http://dx.doi.org/10.1080/10934529.2013.729924.

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45

Shigetomi, Shigeru, Tetsuo Ikari, and Hiroshi Nakashima. "Annealing Behavior of Deep Trap Level in p-GaTe." Japanese Journal of Applied Physics 37, Part 1, No. 6A (June 15, 1998): 3282–83. http://dx.doi.org/10.1143/jjap.37.3282.

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46

Oberg, Jason, Sarah Meiklejohn, Timothy Sherwood, and Ryan Kastner. "Leveraging Gate-Level Properties to Identify Hardware Timing Channels." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 9 (September 2014): 1288–301. http://dx.doi.org/10.1109/tcad.2014.2331332.

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47

Wei Hu, J. Oberg, J. Barrientos, Dejun Mu, and R. Kastner. "Expanding Gate Level Information Flow Tracking for Multilevel Security." IEEE Embedded Systems Letters 5, no. 2 (June 2013): 25–28. http://dx.doi.org/10.1109/les.2013.2261572.

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48

Caro, J., K. L. Hagemans, F. de Schutter, and J. Danneels. "Submicron gate level process step using e-beam lithography." Microelectronic Engineering 3, no. 1-4 (December 1985): 519–24. http://dx.doi.org/10.1016/0167-9317(85)90065-6.

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49

Stigall, Paul D., and Kumar Shiv. "Development of a user friendly gate-level logic simulator." Computers & Electrical Engineering 13, no. 3-4 (January 1987): 147–67. http://dx.doi.org/10.1016/0045-7906(87)90009-7.

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50

Zhang, Zuodong, Runsheng Wang, Xuguang Shen, Dehuang Wu, Jiayang Zhang, Zhe Zhang, Joddy Wang, and Ru Huang. "Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis." IEEE Transactions on Electron Devices 68, no. 9 (September 2021): 4201–7. http://dx.doi.org/10.1109/ted.2021.3096171.

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