Relevant bibliographies by topics / Gate Oxide Asymmetry

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Gate Oxide Asymmetry'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Gate Oxide Asymmetry"

1

Chang, Sheng, Gaofeng Wang, Qijun Huang, and Hao Wang. "Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 56, no. 10 (2009): 2297–301. http://dx.doi.org/10.1109/ted.2009.2028379.

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Sharan, Neha, and Santanu Mahapatra. "A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 61, no. 8 (2014): 2732–37. http://dx.doi.org/10.1109/ted.2014.2331191.

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Sharan, Neha, and Santanu Mahapatra. "Compact noise modelling for common double‐gate metal–oxide–semiconductor field‐effect transistor adapted to gate‐oxide‐thickness asymmetry." IET Circuits, Devices & Systems 10, no. 1 (2016): 62–67. http://dx.doi.org/10.1049/iet-cds.2015.0128.

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4

Jandhyala, Srivatsava, Rutwick Kashyap, Costin Anghel, and Santanu Mahapatra. "A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 59, no. 4 (2012): 1002–7. http://dx.doi.org/10.1109/ted.2012.2184543.

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5

Sharan, Neha, and Santanu Mahapatra. "Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 60, no. 7 (2013): 2419–22. http://dx.doi.org/10.1109/ted.2013.2262943.

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Baruah, R. K., and N. Bora. "Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry." Journal of Computational and Theoretical Nanoscience 8, no. 10 (2011): 2025–28. http://dx.doi.org/10.1166/jctn.2011.1920.

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Jandhyala, S., and S. Mahapatra. "Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry." Electronics Letters 48, no. 13 (2012): 794. http://dx.doi.org/10.1049/el.2012.1295.

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Pyo, Jooyoung, Akio Ihara, Wendi Zhang, Shuma Nishino, and Shun-ichiro Ohmi. "Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer." Japanese Journal of Applied Physics 61, SB (2022): SB1001. http://dx.doi.org/10.35848/1347-4065/ac340c.

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Abstract This paper investigated the multi-level 2-bit/cell operation utilizing a Hf-based metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile memory (NVM) device with a HfO2 and HfON tunneling layer (TL). The 2-bit/cell operation is realized by utilizing the localized charge injection method. It was found that drain-current–gate-voltage (I D–V G) characteristics of the programmed states were affected by asymmetry localized in a trapped location along the channel direction. Moreover, the amount of localized trapped charge is strongly affected by drain-source voltage (V DS) in the case of HfON TL. HfON TL shows distinguishable separated all programmed states compared to HfO2 TL. Finally, it was found that all programmed states of HfO2 and HfON TL show similar characteristics according to the channel length and width (L/W) of 2–10/15–90 μm.
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Popov, Vladimir P., Fedor V. Tikhonenko, Valentin A. Antonov, et al. "Diode-Like Current Leakage and Ferroelectric Switching in Silicon SIS Structures with Hafnia-Alumina Nanolaminates." Nanomaterials 11, no. 2 (2021): 291. http://dx.doi.org/10.3390/nano11020291.

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Silicon semiconductor-insulator-semiconductor (SIS) structures with high-k dielectrics are a promising new material for photonic and CMOS integrations. The “diode-like” currents through the symmetric atomic layer deposited (ALD) HfO2/Al2O3/HfO2… nanolayers with a highest rectification coefficient 103 are observed and explained by the asymmetry of the upper and lower heterointerfaces formed by bonding and ALD processes. As a result, different spatial charge regions (SCRs) are formed on both insulator sides. The lowest leakages are observed through the stacks, with total Al2O3 thickness values of 8–10 nm, which also provide a diffusive barrier for hydrogen. The dominant mechanism of electron transport through the built-in insulator at the weak field E < 1 MV/cm is thermionic emission. The Poole-Frenkel (PF) mechanism of emission from traps dominates at larger E values. The charge carriers mobility 100–120 cm2/(V s) and interface states (IFS) density 1.2 × 1011 cm−2 are obtained for the n-p SIS structures with insulator HfO2:Al2O3 (10:1) after rapid thermal annealing (RTA) at 800 °C. The drain current hysteresis of pseudo-metal-oxide-semiconductor field effect transistor (MOSFET) with the memory window 1.2–1.3 V at the gate voltage |Vg| < ±2.5 V is maintained in the RTA treatment at T = 800–900 °C for these transistors.
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Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.

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Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.
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Dissertations / Theses on the topic "Gate Oxide Asymmetry"

1

Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3489.

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Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.
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2

Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.

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Abstract:
Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.
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3

Hsu, Shih-Yuan, and 徐士垣. "Study of Asymmetric Trapezoidal Gate Structure of Metal-Oxide- Semiconductor Device." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/59283525761097699405.

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碩士<br>國立成功大學<br>電機工程研究所<br>84<br>The theoretical models of the conventional MOSFET with rectangular gate have been well done. In order to reduce the Miller effect which is caused by the gate to drain junction and overlap capacitance, the modifying of the conventional MOSFET gate structure is done and the improvement of the device performance is expected. The MOSFET with asymmetric trapezoidal gate is proposed and fabricated in this work. The DC model of the device that can be used in linear and saturation region is developed and the characteristic of the device threshold voltage is discussed. Besides, the complete measurements of the device have been done and were seen to be in good agreement with the theory. Both the calculation and experiment results show that the proposed devices under the circumstances of forward operation will have the higher threshold voltage and drain current, larger voltage gain(approximately 1.31 times larger) and transconductance(approximately 1.47 times larger), smaller parasitic capacitance(approximately two third smaller), and much better frequency performance(approximately 1.67 times faster), compare with the conventional MOSFET.
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4

Srivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. https://etd.iisc.ac.in/handle/2005/2346.

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For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.
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5

Srivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2346.

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Abstract:
For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.
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Conference papers on the topic "Gate Oxide Asymmetry"

1

Kumar, Chethan, Neha Sharan, and Santanu Mahapatra. "indDG: A new compact model for common double gate MOSFET adapted to gate oxide thickness asymmetry." In 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2015. http://dx.doi.org/10.1109/conecct.2015.7383874.

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2

Sharan, Neha, and Santanu Mahapatra. "Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry." In 2014 27th International Conference on VLSI Design. IEEE, 2014. http://dx.doi.org/10.1109/vlsid.2014.76.

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3

Yu, Zhonghua, Yunpeng Dong, Xinnan Lin, and Lining Zhang. "Current enhanced double-gate TFET with source pocket and asymmetric gate oxide." In 2016 IEEE International Nanoelectronics Conference (INEC). IEEE, 2016. http://dx.doi.org/10.1109/inec.2016.7589410.

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4

Masahara, M., R. Surdeanu, L. Witters, et al. "Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs." In 2006 IEEE international SOI. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284489.

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Jung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Oxide Thickness of Asymmetric Double Gate MOSFET." In Electrical Engineering 2013. Science & Engineering Research Support soCiety, 2013. http://dx.doi.org/10.14257/astl.2013.37.07.

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Narang, R., M. Saxena, R. S. Gupta, and M. Gupta. "Asymmetric gate oxide Tunnel Field Effect Transistor for improved circuit performance." In 2012 International Conference on Devices, Circuits and Systems (ICDCS 2012). IEEE, 2012. http://dx.doi.org/10.1109/icdcsyst.2012.6188721.

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7

Poorvasha, S., and B. Lakshmi. "Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs." In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-sata.2016.7593036.

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Malviya, Abhishek Kumar, and R. K. Chauhan. "Optimizing performance of dual metal gate modified source FDSOI using symmetric and asymmetric oxide spacers." In 2017 International Conference on Emerging Trends in Computing and Communication Technologies (ICETCCT). IEEE, 2017. http://dx.doi.org/10.1109/icetcct.2017.8280327.

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Islam, Md Shafiqul, Jannatul Afza, and Sanjida Tarannum. "Modelling and performance analysis of asymmetric double gate stack-oxide junctionless FET in subthreshold region." In 2017 IEEE Region 10 Humanitarian Technology Conference (R10-HTC). IEEE, 2017. http://dx.doi.org/10.1109/r10-htc.2017.8289017.

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Tahermaram, Mahsa, Mahdi Vadizadeh, Ali Eslamzadeh, and Morteza Fathipour. "Employing work function enginnering and asymmetric gate oxide in nano-scale source-heterojunction-MOS-transistor." In 2009 IEEE International Conference on Electro/Information Technology (eit '09). IEEE, 2009. http://dx.doi.org/10.1109/eit.2009.5189610.

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