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Journal articles on the topic 'Gate Oxide Asymmetry'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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1

Chang, Sheng, Gaofeng Wang, Qijun Huang, and Hao Wang. "Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 56, no. 10 (2009): 2297–301. http://dx.doi.org/10.1109/ted.2009.2028379.

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2

Sharan, Neha, and Santanu Mahapatra. "A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 61, no. 8 (2014): 2732–37. http://dx.doi.org/10.1109/ted.2014.2331191.

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3

Sharan, Neha, and Santanu Mahapatra. "Compact noise modelling for common double‐gate metal–oxide–semiconductor field‐effect transistor adapted to gate‐oxide‐thickness asymmetry." IET Circuits, Devices & Systems 10, no. 1 (2016): 62–67. http://dx.doi.org/10.1049/iet-cds.2015.0128.

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4

Jandhyala, Srivatsava, Rutwick Kashyap, Costin Anghel, and Santanu Mahapatra. "A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 59, no. 4 (2012): 1002–7. http://dx.doi.org/10.1109/ted.2012.2184543.

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5

Sharan, Neha, and Santanu Mahapatra. "Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 60, no. 7 (2013): 2419–22. http://dx.doi.org/10.1109/ted.2013.2262943.

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6

Baruah, R. K., and N. Bora. "Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry." Journal of Computational and Theoretical Nanoscience 8, no. 10 (2011): 2025–28. http://dx.doi.org/10.1166/jctn.2011.1920.

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7

Jandhyala, S., and S. Mahapatra. "Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry." Electronics Letters 48, no. 13 (2012): 794. http://dx.doi.org/10.1049/el.2012.1295.

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8

Pyo, Jooyoung, Akio Ihara, Wendi Zhang, Shuma Nishino, and Shun-ichiro Ohmi. "Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer." Japanese Journal of Applied Physics 61, SB (2022): SB1001. http://dx.doi.org/10.35848/1347-4065/ac340c.

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Abstract This paper investigated the multi-level 2-bit/cell operation utilizing a Hf-based metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile memory (NVM) device with a HfO2 and HfON tunneling layer (TL). The 2-bit/cell operation is realized by utilizing the localized charge injection method. It was found that drain-current–gate-voltage (I D–V G) characteristics of the programmed states were affected by asymmetry localized in a trapped location along the channel direction. Moreover, the amount of localized trapped charge is strongly affected by drain-source voltage (V DS) in the case of HfON TL. HfON TL shows distinguishable separated all programmed states compared to HfO2 TL. Finally, it was found that all programmed states of HfO2 and HfON TL show similar characteristics according to the channel length and width (L/W) of 2–10/15–90 μm.
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9

Popov, Vladimir P., Fedor V. Tikhonenko, Valentin A. Antonov, et al. "Diode-Like Current Leakage and Ferroelectric Switching in Silicon SIS Structures with Hafnia-Alumina Nanolaminates." Nanomaterials 11, no. 2 (2021): 291. http://dx.doi.org/10.3390/nano11020291.

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Silicon semiconductor-insulator-semiconductor (SIS) structures with high-k dielectrics are a promising new material for photonic and CMOS integrations. The “diode-like” currents through the symmetric atomic layer deposited (ALD) HfO2/Al2O3/HfO2… nanolayers with a highest rectification coefficient 103 are observed and explained by the asymmetry of the upper and lower heterointerfaces formed by bonding and ALD processes. As a result, different spatial charge regions (SCRs) are formed on both insulator sides. The lowest leakages are observed through the stacks, with total Al2O3 thickness values of 8–10 nm, which also provide a diffusive barrier for hydrogen. The dominant mechanism of electron transport through the built-in insulator at the weak field E < 1 MV/cm is thermionic emission. The Poole-Frenkel (PF) mechanism of emission from traps dominates at larger E values. The charge carriers mobility 100–120 cm2/(V s) and interface states (IFS) density 1.2 × 1011 cm−2 are obtained for the n-p SIS structures with insulator HfO2:Al2O3 (10:1) after rapid thermal annealing (RTA) at 800 °C. The drain current hysteresis of pseudo-metal-oxide-semiconductor field effect transistor (MOSFET) with the memory window 1.2–1.3 V at the gate voltage |Vg| < ±2.5 V is maintained in the RTA treatment at T = 800–900 °C for these transistors.
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10

Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.

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Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.
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11

Jung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.
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12

Wei, Zhaoxiang, Hao Fu, Xiaowen Yan, et al. "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example." Materials 15, no. 2 (2022): 457. http://dx.doi.org/10.3390/ma15020457.

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The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.
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13

Jia, Ze, Jianlong Xu, Xiao Wu, et al. "Metal-Semiconductor-Insulator-Metal Structure Field-Effect Transistors Based on Zinc Oxides and Doped Ferroelectric Thin Films." MRS Proceedings 1633 (2014): 131–37. http://dx.doi.org/10.1557/opl.2014.130.

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ABSTRACTDifferent ferroelectric thin films and their related Metal-Semiconductor-Insulator-Metal (MSIM) structures include zinc oxide (ZnO) are studied, which can be utilized in back-gated ferroelectric field-effect transistors (FETs). The most ideal zinc oxide (ZnO) thin film prepared by sol-gel method are obtained under the pyrolysis temperature of 400°C and the annealing temperature of 600°C. The asymmetric or symmetric current-voltage characteristics of the heterostructures with ZnO are exhibited depending on different ferroelectric materials in them. The curves of drain current versus gate voltage for MSIM-structure FETs are investigated, in which obvious counterclockwise loops and a drain current switching ratio up to two orders of magnitude ate observed due to the modulation effect of remnant polarization on the channel resistance. The results also indicate the positive influences of impurity atom substitution in bismuth ferrite thin film for the MSIM-structure FETs.
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14

Jung, Hakkee. "Analysis for Gate Oxide Dependent Subthreshold Swing of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 4 (2014): 885–90. http://dx.doi.org/10.6109/jkiice.2014.18.4.885.

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15

Cha, Kyuhyun, and Kwangsoo Kim. "Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications." Energies 14, no. 21 (2021): 7305. http://dx.doi.org/10.3390/en14217305.

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4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.
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16

Pratap, Surender, and Niladri Sarkar. "Application of the Density Matrix Formalism for Obtaining the Channel Density of a Dual Gate Nanoscale Ultra-Thin MOSFET and its Comparison with the Semi-Classical Approach." International Journal of Nanoscience 19, no. 06 (2020): 2050010. http://dx.doi.org/10.1142/s0219581x20500106.

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Density Matrix Formalism using quantum methods has been used for determining the channel density of dual gate ultra-thin MOSFETs. The results obtained from the quantum methods have been compared with the semi-classical methods. This paper discusses in detail the simulation methods using self-consistent schemes and the discretization procedures for constructing the Hamiltonian Matrix for a dual gate MOSFET consisting of oxide/semiconductor/oxide interface and the self-consistent procedure involving the discretization of Poisson’s equation for satisfying the charge neutrality condition in the channel of different thicknesses. Under quantum methods, the channel densities are determined from the diagonal elements of the density matrix. This successfully simulates the size quantization effect for thin channels. For semi-classical methods, the Fermi–Dirac Integral function is used for the determination of the channel density. For thin channels, the channel density strongly varies with the values of the effective masses. This variation is simulated when we use Quantum methods. The channel density also varies with the asymmetric gate bias and this variation is more for thicker channels where the electrons get accumulated near the oxide/semiconductor interface. All the calculations are performed at room temperature (300[Formula: see text]K).
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17

Jung, Hakkee. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 232. http://dx.doi.org/10.11591/ijece.v11i1.pp232-239.

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The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.
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18

Jung, Hakkee. "Relation of Oxide Thickness and DIBL for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 4 (2016): 799–804. http://dx.doi.org/10.6109/jkiice.2016.20.4.799.

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19

Assalti, Rafael, Rodrigo T. Doria, Denis Flandre, and Michelly De Souza. "Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs." Journal of Integrated Circuits and Systems 12, no. 2 (2017): 62–70. http://dx.doi.org/10.29292/jics.v12i2.452.

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In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.
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20

Gowthami, Y., B.Balaji, and K. Srinivasa Rao. "Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics." Journal of Integrated Circuits and Systems 18, no. 1 (2023): 1–8. http://dx.doi.org/10.29292/jics.v18i1.657.

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The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric material are layered one on another to overcome the conventional transistor draw backs like surface defects, scattering of the electron, and less mobility of electron. Hot electron effect is overcome by Pi type gate. Therefore, by optimizing the HEMT structure the abilities for certain devices are converted to abilities. The dependency on DC characteristics and RF characteristics due to GaN Cap Layers, Multi gate (FG &BG), and High K Dielectric material is established. Further Compared Single Gate (SG) Passivated HEMT, Double Gate (DG) Passivated HEMT, Double Gate Triple(DGT) Tooth Passivated HEMT, High K Dielectric Front Pi Gate (FG) and Back Pi Gate (BG) Nanowire HEMT. It is observed that there is an increased Drain Current (Ion) of 5.92(A/mm), low Leakage current(Ioff) 5.54E-13 (A) of Transconductance (Gm) of 3.71(S/mm), Drain Conductance (Gd) of 1.769(S/mm), Cutoff frequency(fT) of 743 GHz Maximum Oscillation frequency (Fmax) 765 GHz, Minimum Threshold Voltage (Vth) of -4.5V, On Resistance (Ron)of 0.40(Ohms) at Vgs =0V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation High-speed GHz frequency applications.
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21

Kang, Heebum, Hyun Wook Kim, Eun Ryeong Hong, and Jiyong Woo. "Analog synaptic behavior of mobile ion source-limited electrochemical RAM using CuOx oxide electrode for deep learning accelerator." Applied Physics Letters 120, no. 12 (2022): 122101. http://dx.doi.org/10.1063/5.0086164.

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We demonstrate the synaptic characteristics of analogously modulated channel currents in Cu-ion-actuated electrochemical RAM (ECRAM) based on an HfOx electrolyte and a WOx channel. Uncontrolled synaptic response is found as a function of the gate pulse when a Cu-rich gate electrode delivers mobile ions, presumably due to many ions injected from the infinite ion reservoir. As a result, we propose a CuOx oxide electrode to limit ion sources, which is indirectly validated by a physical examination of the degree of chemical bonding between Cu and oxygen, thereby boosting gate controllability over the channel. In addition, the HfOx electrolyte needs to be designed to facilitate the adequate migration of Cu ions, considering thickness and film quality. Using material stack engineering, the channel current of optimized CuOx/HfOx/WOx ECRAM can be steadily tuned via repeated identical gate pulses. The channel current and its change are proportional to the device area and the amount of migrated ions relevant to the gate pulse conditions, respectively. The homogeneous flow of ions across the entire area can, thus, be used to explain the obtained analog switching. The gate-controllable synaptic behavior of the ECRAM accelerates deep neural network training based on backpropagation algorithms. An improved pattern recognition accuracy of ∼88% for handwritten digits is achieved by linearly tuned multiple current states with more than 100 pulses and asymmetric gate voltage conditions in a three-layer neural network validated in simulation.
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22

Zun-Chao, Li. "Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Asymmetric Halo." Chinese Physics Letters 26, no. 1 (2009): 018502. http://dx.doi.org/10.1088/0256-307x/26/1/018502.

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23

Liu, Yongxun, Takashi Matsukawa, Kazuhiko Endo, et al. "Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs With Asymmetric Gate-Oxide Thicknesses." IEEE Electron Device Letters 28, no. 6 (2007): 517–19. http://dx.doi.org/10.1109/led.2007.896898.

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24

Jung, Hakkee. "Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness." Journal of the Korea Institute of Information and Communication Engineering 20, no. 5 (2016): 992–97. http://dx.doi.org/10.6109/jkiice.2016.20.5.992.

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25

Ma, Shuanhong, Jianxi Liu, Qian Ye, Daoai Wang, Yongmin Liang, and Feng Zhou. "A general approach for construction of asymmetric modification membranes for gated flow nanochannels." J. Mater. Chem. A 2, no. 23 (2014): 8804–14. http://dx.doi.org/10.1039/c4ta00126e.

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Double hydrophilic, double responsive, hydrophilic/hydrophobic polymer brushes asymmetrically-modified anodic aluminum oxide (AAO) nanochannel arrays were prepared by asymmetrical polymerization strategies.
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26

Jung, Hak Kee, and Sima Dimitrijev. "The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (2016): 2730. http://dx.doi.org/10.11591/ijece.v6i6.13265.

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>
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27

Jung, Hak Kee, and Sima Dimitrijev. "The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (2016): 2730. http://dx.doi.org/10.11591/ijece.v6i6.pp2730-2734.

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>
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28

Singh, Shradhya, Sangeeta Singh, and Alok Naugarhiya. "Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance." International Journal of Modern Physics B 34, no. 27 (2020): 2050242. http://dx.doi.org/10.1142/s0217979220502422.

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This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.
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29

Jung, Hakkee. "Analysis of Threshold Voltage for Symmetric and Asymmetric Oxide Structure of Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 12 (2014): 2939–45. http://dx.doi.org/10.6109/jkiice.2014.18.12.2939.

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30

Huang, W., T. Khan, and T. Paul Chow. "Asymmetric Interface Densities on n and p Type GaN MOS Capacitors." Materials Science Forum 527-529 (October 2006): 1525–28. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1525.

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Both n-type and p-type GaN MOS capacitors with plasma-enhanced CVD-SiO2 as the gate oxide were characterized using both capacitance and conductance techniques. From a n type MOS capacitor, an interface state density of 3.8×1010/cm2-eV was estimated at 0.19eV near the conduction band and decreases deeper into the bandgap while from a p type MOS capacitor, an interface state density of 1.4×1011/cm2-eV 0.61eV above the valence band was estimated and decreases deeper into the bandgap. Unlike the symmetric interface state density distribution in Si, an asymmetric interface state density distribution with lower density near the conduction band and higher density near the valence band has been determined.
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31

Drapatz, S., G. Georgakos, and D. Schmitt-Landsiedel. "Impact of negative and positive bias temperature stress on 6T-SRAM cells." Advances in Radio Science 7 (May 19, 2009): 191–96. http://dx.doi.org/10.5194/ars-7-191-2009.

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Abstract. With introduction of high-k gate oxide materials, the degradation effect Positive Bias Temperature Instability (PBTI) is starting to play an important role. Together with the still effective Negative Bias Temperature Instability (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event.
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32

Shin, Yong Hyeon, and Ilgu Yun. "Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region." Solid-State Electronics 120 (June 2016): 19–24. http://dx.doi.org/10.1016/j.sse.2016.03.002.

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33

Jung, Hakkee. "Influence of Ratio of Top and Bottom Oxide Thickness on Subthreshold Swing for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 3 (2016): 571–76. http://dx.doi.org/10.6109/jkiice.2016.20.3.571.

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34

Masahara, Meishoku, Radu Surdeanu, Liesbeth Witters, et al. "Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope." IEEE Electron Device Letters 28, no. 3 (2007): 217–19. http://dx.doi.org/10.1109/led.2007.891303.

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35

Masahara, Meishoku, Yongxun Liu, Kenichi Ishii, et al. "Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors." Applied Physics Letters 86, no. 12 (2005): 123512. http://dx.doi.org/10.1063/1.1891289.

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36

Huang, Hongtao, Qin Zhang, Chao Dai, and Zhijun Wang. "15.3: Asymmetric Conductance of Oxide Thin‐Film Transistors Induced by Top‐Gate Effect of Drain Overlap Capacitance." SID Symposium Digest of Technical Papers 50, S1 (2019): 153–56. http://dx.doi.org/10.1002/sdtp.13420.

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37

Liu, Yaxuan, Xin Zhang, Jingye Sun, Ling Tong, Lingbing Kong, and Tao Deng. "A Novel Terahertz Detector Based on Asymmetrical FET Array in 55-nm Standard CMOS Process." Materials 15, no. 19 (2022): 6578. http://dx.doi.org/10.3390/ma15196578.

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This paper reports a novel, one-dimensional dense array of asymmetrical metal-oxide-semiconductor field-effect-transistor (MOSFET) THz detector, which has been fabricated in GlobalFoundries 55-nm CMOS technology. Compared with other technologies, the Si-based complementary metal-oxide-semiconductor (CMOS) dominates in industrial applications, owing to its easier integration and lower cost. However, as the frequency increases, the return loss between the antenna and detector will increase. The proposed THz detector has a short-period grating structure formed by MOSFET fingers in the array, which can serve as an effective antenna to couple incident THz radiation into the FET channels. It not only solved the problem of return loss effectively, but also greatly reduced the detector area. Meanwhile, since the THz signal is rectified at both the source and drain electrodes to generate two current signals with equal amplitude but opposite directions, the source drain voltage is not provided to reduce the power consumption. This leads to a poor performance of the THz detector. Therefore, by using an asymmetric structure for the gate fingers position to replace the source drain voltage, the performance of the detector in the case of zero power consumption can be effectively improved. Compared with the symmetrical MOSFET THz detector, Rv is increased by 183.3% and NEP is decreased by 67.7%.
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Jung, Hakkee. "Conduction Path Dependent Threshold Voltage for the Ratio of Top and Bottom Oxide Thickness of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 11 (2014): 2709–14. http://dx.doi.org/10.6109/jkiice.2014.18.11.2709.

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39

Zhu, Zhaomin, Xing Zhou, Karthik Chandrasekaran, Subhash C. Rustagi, and Guan Huei See. "Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors." Japanese Journal of Applied Physics 46, no. 4B (2007): 2067–72. http://dx.doi.org/10.1143/jjap.46.2067.

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40

Kang, Miae, Kihyun Kim, Joona Bang, and Jihyun Kim. "Nano-Pattern Oxidation of WSe2 Via Block Copolymer Self-Assembly for Highly Responsive Homojunction Phototransistors." ECS Meeting Abstracts MA2022-02, no. 36 (2022): 1317. http://dx.doi.org/10.1149/ma2022-02361317mtgabs.

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Tungsten diselenide (WSe2), one of the two-dimensional (2D) materials, has emerged as a promising optoelectric candidate because of its thickness dependent bandgap, large optical absorption coefficient, good air stability and high carrier mobility. In addition, the electrical properties of the ambipolar WSe2 could be tuned through the electrostatic doping by the gate modulation. However, the low photo responsivity is a critical problem of WSe2-based optoelectric devices. To overcome this limitation, several approaches have been suggested such as stacking different 2D materials and coating with quantum dots. But these conventional methods were focused on the formation of heterojunctions, which requires complicated alignment process and leads to unavoidable defects and residues. Thus, the novel ways to build homojuction should be investigated for fabricating devices with a clean interface in a simple process. In this work, block copolymer (BCP) was used to prepare hexagonally packed cylinder nano-template as an oxidation mask for UV/ozone treatment, which resulted in numerous nanoscale homojunctions on WSe2. To fabricate the mask with hexagonally packed cylinders, asymmetric poly (styrene-block-methyl methacrylate) (PS-b-PMMA) was spin-coated. After thermal annealing for self-assembly, PMMA was selectively removed by reactive ion etching. UV/ozone treatment, one of the oxidation methods of the WSe2, leads to the formation of the the tungsten oxide (WOX) with high electron affinity and induces a p-doping effect. By using BCP as an oxidation mask, the only region of the WSe2 under the removed PMMA blocks could be converted into WOX. The responsivity of the nano-pattern oxidized WSe2 phototransistor manifests a dramatic change depending on the applied gate bias. The device exhibited a responsivity (532 nm, 8.515 mW/cm2) of 27.5 mA/W under applied gate bias of 0 V. However, under the gate bias of +60 V, the device showed an enhanced responsivity of 155.2 mA/W, as strong p-n junctions were induced. In conclusion, the nano-pattern oxidized WSe2 phototransistor presents increased responsivity (155.2 mA/W), external quantum efficiency (36.3%) and faster response time than the pristine WSe2. This work demonstrates that the responsivity of the WSe2 phototransistor can be improved though well-established perpendicular BCP and optimized by effective modulation of gate bias. By implementing homojunctions on the WSe2 via the nano-pattern oxidation method, this work greatly expands the potential applications of 2D TMDs materials for next-generation nanoscale optoelectronic devices.
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Wada, Akira, Kazuhiko Endo, Meishoku Masahara, Chi-Hsien Huang, and Seiji Samukawa. "Fabrication of Four-Terminal Fin Field-Effect Transistors with Asymmetric Gate-Oxide Thickness Using an Anisotropic Oxidation Process with a Neutral Beam." Applied Physics Express 3, no. 9 (2010): 096502. http://dx.doi.org/10.1143/apex.3.096502.

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42

Paul, Somnath, Subho Chatterjee, Saibal Mukhopadhyay, and Swarup Bhunia. "Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1, no. 3 (2011): 369–80. http://dx.doi.org/10.1109/jetcas.2011.2165232.

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Reconfigurable computing frameworks such as field programmable gate array (FPGA) provide flexibility to map arbitrary applications. However, their intrinsic flexibility comes at the cost of significantly worse performance and power dissipation than their custom counterparts. Existing design solutions such as voltage scaling and multi-threshold assignment typically trade off energy for performance or vise versa. In this paper, we show that an integrated circuit-architecture-software co-design approach can be extremely effective to simultaneously improve the power and performance of a reconfigurable hardware framework, leading to large improvement in energy-delay product (EDP). First, we select a spatio-temporal reconfigurable computing architecture based on 2-threshold assignment-D memory-array. Applications are mapped to memory as multiple-input multiple-output lookup tables (LUTs) and are evaluated in temporal manner inside a computing element. Multiple such computing elements communicate spatially through programmable interconnects. Next, we exploit the read-dominant memory access pattern in reconfigurable hardware to design an asymmetric memory cell, which provides higher read performance and lower read power leading to improvement in the overall EDP during operation. We note that the proposed memory cell is also asymmetric in terms of its content, providing better read power for one of the logic states (logic “0” or “1”). Based on this observation, next we propose a content-aware application mapping approach, which tries to maximize the logic “0” or logic “1” content in the lookup tables. A design flow is presented to incorporate the proposed architecture, asymmetric memory cell design and content-aware mapping. We show that for both nanoscale complementary metal-oxide-semiconductor (CMOS) [static random access memory (SRAM)] as well as emerging non-CMOS [spin torque transfer random access memory (- TTRAM)] memory technologies, such a co-design solution can achieve significant improvement in system EDP over a conventional FPGA framework.
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Zhao, Qing-Tai, Fengben Xi, Yi Han, Jin Hee Bae, and Detlev Gruetzmacher. "(Invited, Digital Presentation) Approach to Neuromorphic Computing with Ferroelectric Schottky Barrier FETs." ECS Meeting Abstracts MA2022-01, no. 29 (2022): 1298. http://dx.doi.org/10.1149/ma2022-01291298mtgabs.

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Neuromorphic computing inspired by neural network systems of the human brain enables energy efficient computing as a solution of the von Neumann bottleneck. A neural network consists of thousands or even millions of neurons which communicate with each other through connected synapses. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken its activity over time make it be capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbone of a neuromorphic computing system. Non-volatile memories with two-terminals, like resistive random-access memory (ReRAM), phase change memory (PCM), are attractive candidates for artificial synapses. However, signal processing and learning cannot be performed simultaneously in these two-terminal synapses. FeFET, similar to a MOSFET structure using CMOS compatible HfO2 based ferroelectrics as gate oxide forms three-terminal synapses offering high endurance, good performance and high energy efficiency. In contrast to two-terminal devices, three terminal FeFET based synapses can perform processing and learning at the same time. In order to maintain the ferroelectric properties of an HfO2 based ferroelectric film, high temperature annealing should be avoided after the ferroelectric layer deposition. In this paper, we present ferroelectric NiSi2 source/drain Schottky barrier (SB) MOSFET (FE-SBFET) structure (Fig.1a), which requires neither ion implantation nor thermal activation of source/drain contacts at high temperatures. FE-SBFETs were fabricated on SOI substrates with a boron-doped (1016 B/cm-3), 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer. Very thin (9 nm) single crystalline NiSi2 layers which offer superior properties of uniform and stable SB contacts on Si are used at source/drain regions. A gate stack consisting of 10 nm thick Hf0.5Zr0.5O2 (HZO) layer and a 40 nm thick TiN layer are deposited by ALD and sputtering, respectively. A rapid thermal annealing at 500 °C is performed to crystallize the HZO into a ferroelectric phase before the gate patterning. The fabricated device has a channel length of 10 µm and a gate width of 10 µm. The overlap between the top gate and NiSi2 is 6 µm along the channel and 10 µm wide on each side. The ferroelectric polarization modulates both the SB at the source/drain contacts as well as the potential in the channel, thus changing the carrier injection through the SB. The Id-Vg transfer characteristics of a p-type FE-SBFET shows a clockwise hysteresis which is caused by the ferroelectric polarization switch. The excitatory post-synaptic current (EPSC), one of the typical short-term synaptic plasticity features for biologic synapses, is characterized by measuring the transient drain currents for a voltage pulse on the gate of a FE-SBFET (Fig.1b). The amplitude of the pulse VAM changes from -0.2 to -1.2 V with a fixed pulse width tpw=1 μs. We found that the EPSC peak value increases linearly with VAM. It shows a very low energy/spike consumption of 2fJ/spike at VAM=-0.2 V, demonstrating a very high energy efficiency. From the EPSC measurements with repeated gate voltage pulses paired-pulse facilitation/depression (PPF/PPD) are characterized showing an exponential decay, similar to biological synapses. The long-term synaptic plasticity of FE-SBFET synapses is characterized by a series repeated identical or non-identical pulses. The later can improve the long-term potentiation/depression (LTP/LTD) symmetry and linearity. The measurements show a large Gmax/Gmin ratio, very high endurance and small cycle-to-cycle (CTC) variation (1.06%) due to the perfect contact of NiSi2 (Fig.1c). The biological neuron-like spike-timing-dependent plasticity (STDP) is characterized for the FE-SBFET synapse. The results show an asymmetric anti-Hebbian STDP, which is one of the biological STDP functionalities (Fig.1d). In conclusion, the fabricated FE-SBFET synapse exhibits multiple synaptic functions with high endurance and small variations. The ultra-low energy/spike consumption indicates a high potential for low power neuromorphic computing applications. Acknowledgement: This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (16ME0398K). Figure 1
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44

Kim, Jeongmin, and Jaewook Jeong. "Origin of performance improvement in solution-processed indium–gallium–zinc-oxide thin-film transistors having thin active layer and asymmetric dual gate structure." AIP Advances 10, no. 12 (2020): 125110. http://dx.doi.org/10.1063/5.0029185.

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45

Kumar, Ajit, and J. N. Roy. "Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs." Semiconductor Science and Technology 36, no. 1 (2020): 015007. http://dx.doi.org/10.1088/1361-6641/abc28d.

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46

Vadizadeh, Mahdi, Mohammad Fallahnejad, Pegah Sotoodeh, Reyhaneh Ejlali, and Mahdis Azadmanesh. "Improving subthreshold slope in Si/InAs/Ge junctionless tunneling FET-based biosensor by using asymmetric gate oxide thickness for low-power applications: A numerical simulation study." Materials Science and Engineering: B 292 (June 2023): 116445. http://dx.doi.org/10.1016/j.mseb.2023.116445.

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47

Jarwal, R. K., and D. Misra. "Effects of Reverse Biased Floating Voltage at Source and Drain During High-Field Electron Injection on the Performance of NMOSFETS." MRS Proceedings 592 (1999). http://dx.doi.org/10.1557/proc-592-123.

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ABSTRACTWe have examined the effects of reverse biased floating voltage at the source and drain junctions during constant current high-field electron injection on the performance of NMOSFETs. Device parameter degradation was studied when electrons were injected from both gate and substrate. Hole trapping and electron trapping (observed from threshold voltage degradation) were found to be enhanced with reverse biased floating voltage for devices subjected to substrate injection. On the other hand, damages in the devices subjected to gate injection were found to be minimal dependent on reverse biased voltage. Increase in current density due to reduction in effective channel length is believed to be the cause of modified device characteristics. Transconductance degradation for both substrate injection and gate injection was found to have minimal dependence on reverse biased voltage. An asymmetry in the distribution of electron traps at the gate-oxide and substrate-oxide interfaces was observed.
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48

Huang, Shijie, Jingrui Guo, lihua xu, Lingfei Wang, and Ling Li. "Physics-based 2-D analytical potential model with disorder effects for scaling a-IGZO TFT via dual material gate engineering." Japanese Journal of Applied Physics, August 12, 2022. http://dx.doi.org/10.35848/1347-4065/ac895d.

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Abstract A dual material gate (DMG) amorphous indium gallium zinc oxide(a-IGZO) thin-film transistor (TFT) is proposed, which has a gate structure of lateral-contact-metals with two working functions. In view of multiple gate materials and localized/delocalized states, the potential calculations using Poisson’s equation are complicated and without analytical solution, which complicates the gate controllability analysis and future compact modeling methodology. Therefore, we have developed an analytical 2-D potential model, that shows a great agreement with the numerical solution, taking into account asymmetry effects and scaling behavior. It can be used to tune potential or electric-field profiles by dual material gate engineering, increase the average channel electric field, reduce the electric-field at the Drain side, and thus improve the performance of short-channel a-IGZO TFT with immunity to Drain-Induced-Barrier-Lowing and hot carrier effect.
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49

Jiang, Kaizhe, Xiaodong Zhang, Chuan Tian, et al. "A SiC Asymmetric Cell Trench MOSFET with Split Gate and Integrated p+-polySi/SiC Heterojunction Freewheeling Diode." Chinese Physics B, February 20, 2023. http://dx.doi.org/10.1088/1674-1056/acbd2d.

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Abstract A new SiC asymmetric cell trench MOSFET with split gate (SG) and integrated p+-polySi/SiC heterojunction freewheeling diode (SGHJD-TMOS) is investigated in this article. SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gate oxide electric field. The integrated p+-polySi/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device. Numerical analysis results show that compared with the conventional asymmetric cell trench MOSFET (CA-TMOS), the high-frequency figure of merit (HF-FOM, R on,sp×Q gd,sp) is reduced by 92.5%, and the gate oxide electric field is reduced by 75%, respectively. In addition, forward conduction voltage drop (V f) and gate-drain charge (Q gd) are reduced from 2.90 V and 63.5 µC/cm2 for the CA-TMOS to 1.80 V and 26.1 µC/cm2 for the SGHJD-TMOS, respectively. Compared with the CA-TMOS, the turn-on loss (Eon) and turn-off loss (Eoff) of the SGHJD-TMOS are reduced by 21.1% and 12.2%, respectively.
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50

Johnson, M. A. L., D. W. Barlage, and Dave Braddock. "Prospect for III-Nitride Heterojunction MOSFET Structures and Devices." MRS Proceedings 829 (2004). http://dx.doi.org/10.1557/proc-829-b7.7.

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ABSTRACTHeterojunction field effect transistors (HFET) for high-frequency and high-power electronics have been an area of active research in recent years as a key enabling technology for applications ranging from wireless communications to power distribution. III-Nitride semiconductors are a leading candidate for fulfilling the material requirements of these devices based on the combination of large bandgap energy, high thermal conductivity, high electron mobility and saturated electron velocity. While III-Nitride HFETs have demonstrated remarkable advances, serious materials related limitations still exist, primarily related to charge states and trapping effects at the semiconductor surface. Several groups have investigated solutions such as the deposition of dielectric passivation layers and asymmetric field-plate gate geometries for controlling the influence of trap states near the metal/semiconductor FET interface. We have demonstrated a metal-oxide semiconductor FET (MOSFET) with a substantially unpinned interface which is capable of establishing substantial charge accumulation under the gate. These III-Nitride MOSFETs may be designed to operate in either depletion mode or enhancement mode. GaN/InGaN heterojunction MOSFETs exhibit enhancement mode peak transconductance at gate voltages Vg>+5V, corresponding to energy greater than the bandgap of the underlying semiconductor which provides strong evidence of an unpinned MOS interface. Additionally III-Nitride MOSFETs eliminate the need for field plate gate structures as the electric field geometry in the gate-drain region changes limiting the tunneling of charge to unfilled surface states. In depletion mode, low-rf dispersion InGaN/GaN MOSFETs exhibit excellent microwave with ft = 8GHz for optically defined gates dimensions.We review the history of compound semiconductor MOSFET development and overlaying these developments with recent advances in the III-Nitride materials and device research. Differences in chemistry of III-Nitrides relative to all other compound semiconductors and the epitaxial deposition of gate-oxides such as Gadolinium Gallium Oxide (GGO), opens the possibility for dramatically improved devices at microwave and mm-wave frequencies as well as power MOSFET rectifiers. Initial III-Nitride MOSFETs results are presented as well as a quaternary thermodynamic framework for the stability of gate-oxide on nitride semiconductors. We also identify key materials related research challenges expected to impact the ongoing development of III-Nitride MOSFETs.
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