Academic literature on the topic 'Gate Oxide Thickness Asymmetry'
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Journal articles on the topic "Gate Oxide Thickness Asymmetry"
Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.
Full textChang, Sheng, Gaofeng Wang, Qijun Huang, and Hao Wang. "Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 56, no. 10 (October 2009): 2297–301. http://dx.doi.org/10.1109/ted.2009.2028379.
Full textSharan, Neha, and Santanu Mahapatra. "A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 61, no. 8 (August 2014): 2732–37. http://dx.doi.org/10.1109/ted.2014.2331191.
Full textBaruah, R. K., and N. Bora. "Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry." Journal of Computational and Theoretical Nanoscience 8, no. 10 (October 1, 2011): 2025–28. http://dx.doi.org/10.1166/jctn.2011.1920.
Full textJandhyala, Srivatsava, Rutwick Kashyap, Costin Anghel, and Santanu Mahapatra. "A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 59, no. 4 (April 2012): 1002–7. http://dx.doi.org/10.1109/ted.2012.2184543.
Full textSharan, Neha, and Santanu Mahapatra. "Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 60, no. 7 (July 2013): 2419–22. http://dx.doi.org/10.1109/ted.2013.2262943.
Full textSharan, Neha, and Santanu Mahapatra. "Compact noise modelling for common double‐gate metal–oxide–semiconductor field‐effect transistor adapted to gate‐oxide‐thickness asymmetry." IET Circuits, Devices & Systems 10, no. 1 (January 2016): 62–67. http://dx.doi.org/10.1049/iet-cds.2015.0128.
Full textJung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.
Full textJung, Hakkee. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 232. http://dx.doi.org/10.11591/ijece.v11i1.pp232-239.
Full textJandhyala, S., and S. Mahapatra. "Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry." Electronics Letters 48, no. 13 (2012): 794. http://dx.doi.org/10.1049/el.2012.1295.
Full textDissertations / Theses on the topic "Gate Oxide Thickness Asymmetry"
Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3489.
Full textSharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.
Full textYen, Yuh-Ren, and 顏育仁. "Study on Thickness Uniformity of Rapid Thermal Thin Gate Oxide." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/49874845421521239969.
Full text國立臺灣大學
電機工程學研究所
89
Two main topics are discussed in this thesis. One is about the electrical characteristics of MOS capacitor with non-uniform gate oxide and the other is the uniformity improvement of gate oxide prepared by Rapid Thermal Processor(RTP). In order to investigate the influence of non-uniform gate oxide on the electrical characteristics of MOS capacitors, we intentionally grow a non-uniform thickness oxide by putting a quartz ring beneath the monitored wafer. A thinner oxide is grown on the regions contacted with the quartz ring since heat is conducted by the contact quartz. The result oxide is a hill-shape structure. The Si beneath the thinner and thicker oxide of this structure was found to sense a tensile stress while a compressive stress exists on the Si beneath the moderate thickness oxide. We adopt this oxide structure as the gate oxides of our MOS capacitors. The measured I-V curves of these MOS capacitors show that there is a relation between the stress on Si and the reverse-saturation current. The MOS capacitor with a tensile stress on Si will have a lower revers-saturation current. This is quite important to the thin gate oxide reliability in ULSI. The reason why tensile stress leads to lower reverse-saturation current is also given in this thesis. With the ability to perform heat cycles on a wafer rapidly and with low thermal budget, RTP has become a key technology in the fabrication of advanced semiconductor devices. However, the most common criticisms of RTP are about the thermal non-uniformity, and this problem becomes earnest as oxide thickness shrinks for the need of ULSI devices. A great deal of effort has been put into improvement of radiant uniformity. For high thermal uniformity systems, however, heat convection does play an important role. From simulation result of flow filed, we see that the cold gas flow toward the wafer surface where exhibits a lower pressure due to the flow away of gas by the buoyancy at the wafer center. Our work is to suppress the upward gas flow by putting a quartz cap above the monitored wafer. Since this setting prevents the cold gas drawn form wafer edge to wafer center gas, we suppose that the temperature uniformity can be improved. This supposition is proven to be true from both simulation and experimental results. Furthermore, since natural convection tends to balance the temperature variation, the non-uniform temperature is self-compensated by the gas flowing in the gap between the wafer and the cap.
Fan, Kung Ming, and 范恭鳴. "Multiple-gate-oxide-thickness Process Development by NH3 Plasma Nitridation." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/61329243704455919302.
Full text長庚大學
半導體研究所
90
Abstract According to the ITRS prediction, the equivalent oxide thickness (EOT) will be scale to 0.9-1.4nm in the 90nm technology node. As the oxide thickness less than 3nm, the gate leakage current and boron penetration through oxide are more seriously. Replace the SiO2 by High-k dielectric materials and nitrogen implant in the silicon surface or dielectrics are the most popular approaches to overcome these two issues. SOC is the current trend for the future CMOS processes, but it increases the process complexity, one of these challenges is the multiple gate oxide thickness, which in order to have lower power consumption, high speed and circuit stability. Oxidation growth rate can be reduced by nitrogen implant in the silicon substrate and have being widely employed. In this thesis, nitrogen incorporated in the silicon surface by NH3 plasma. We discussed its oxidation growth rate and electrical characteristics of MOS capacitors. The oxidation growth rate can be reduced maximum about 80﹪compare to the control sample. Besides, we improved its oxide quality by NH3 plasma treatment compared to the direct rapid thermal (RT) N2O oxidation. We find that the low charge trapping, low bulk trap densities, higher immunity to SILC and higher charge to soft-breakdown by NH3 plasma treatment before RT N2O oxidation. In this experiment, gate voltage shift has a minimum value of 10 mV in constant current stress and negligible hysteresis effects of C-V characteristic, the flatband voltage shift is 8.5 mV. This process could achieve both multiple gate oxide thickness and improve oxide reliability.
Kun, Huang Tao, and 黃道坤. "The impact of poly gate sidewall oxide thickness on MOSFET’s gate-induced drain leakage behavior." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/12981841264445016012.
Full text長庚大學
電子工程研究所
93
The leakage in the drain region is a crucial issue for scaling of the MOSFET. The off-state gate-induced drain leakage (GIDL) current is one of the major contributors to the overall MOSFET leakage. GIDL is induced by band-to-band tunneling (BTBT) effect in the depletion region and generated in the gate to drain overlap region with high electric field. GIDL leakage is a function of many process parameters such as spacer material, spacer width, gate oxide thickness, doped concentration; anneal temperature, and poly re-oxidation conditions etc. Devices used in this work consist of a gate oxide of 4nm or 6nm, and a spacer width of 25nm. Three different poly re-oxidation conditions result in 3 gate sidewall oxide thicknesses of 4nm, 6nm, and 8nm, measured on the shallow trench isolation processed wafers in the experiments. The impact of different gate sidewall oxide thicknesses (4nm, 6nm and 8nm) on device threshold voltage (Vt), overlap capacitance (Cgd), and off-state GIDL leakage current was investigated. This study shows that the use of thin sidewall oxidation thickness further increases GIDL leakage current, getting high overlap capacitance, and decrease threshold voltage (Vt). Finally, a comparison of GIDL behavior in n-poly gate surface-channel NMOS and n-poly gate buried channel PMOS is summarized.
Chen, Hui-Yen, and 陳慧燕. "Improved the uniformity of Gate Oxide Thickness of High Voltage Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/41002387735940640452.
Full text國立交通大學
工學院半導體材料與製程設備學程
101
The purpose of this study is to improve the uniformity of gate oxide thickness in 0.15μm high voltage device. Thermal oxidation process was used to fabricate this gate oxide. During oxidation process, gate oxide needs overcome the thermal stress distribution caused from the Si substrate. In this paper, the uniformity of gate oxide thickness was improved through investigation of the position of the wafer, oxidation method, annealing method and “sacrifice etching” of oxide layer. Change annealing method from RTA to furnace can improve this issue but the thermal budget concerned high voltage device. The sacrifice etching of oxide is the final solution.
Chen, Chi-Chih, and 陳吉智. "The characteristics of n-channel lateral diffused metal-oxide-semiconductor (LDMOS) field effect transistors with different gate oxide thickness." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/85234330301321003481.
Full text國立成功大學
微電子工程研究所碩博士班
92
In this thesis, the characteristics of Lateral Diffused Metal-Oxide-Semi- conductor (LDMOS) field effect transistors based on 1.0μm technology with different gate oxide thickness are investigated. The characteristics of LDMOS transistors with different gate oxide thicknesses are examined. The temperature dependence of device parameters is studied under elevated operating temperature. Constant voltage stress is performed on devices with different gate oxide thickness to see the impact of gate oxide thickness on parameter degradation. Different degradation behavior was found that the maximum degradation of thick gate oxide device increases with gate stress voltage. While in thin gate oxide device, the maximum degradation remains at peak substrate current condition.
Wu, Jiunn-Pey, and 吳俊沛. "Analysis on Gate-Oxide Thickness Dependence of Hot-Carrier- Induced Degradation in Submicrometer LDD nMOSFET's." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/44807502258254042698.
Full text國立交通大學
電子研究所
83
In this thesis, gate-oxide thickness dependecnce of hot- carrier-induced degradation is investigated for LDD nMOSFET' s. It is shown that a thinner gate oxide LDD nMOSFET's causes larger drain current degradation under the same bias stress condition. However, it has been reported that a thinner gate oxide conventional nMOSFET shows smaller degradation. Since the dominant degradation mechanism for the LDD device differ from the conventional device, due to the spacer-induced degradation, an improved drain linear-current degradation model is developed in order to investigate the degradation mechanism in LDD MOSFET. A new degradation mechanism is introduced to account for the increasing of resistance in the n- region due to the generation of interface states. Further, since the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent, the paired Vg method is used to extract the effective channel length and the series resistance. It can be found that this generalized drain current degradation model gives a good agreement to the measured data for different gate oxide thickness. Based on this model, the gate-oxide thickness dependence of degradation can be well analyzed.
Tan, Yu-De, and 談昱德. "Effect of Gate Metal Thickness on The 2-State Characteristics of MOS Structure with Ultrathin Oxide." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/59894679539440376075.
Full text國立臺灣大學
電機工程學研究所
103
In this work, we study the effect of the thickness of gate metal on the characteristics of Metal-Oxide-Semiconductor capacitor (MOSCAP) device with ultrathin oxide layer. The embedded Dynamic Random Access Memory (eDRAM) becomes more and more important in semiconductor industry with application of System on Chip (SoC) and Application Specific Integrated Circuit (ASIC). The pattern of the device is a long strap connected to a square contact pad in this work, which is designed for higher gate resistance with ultrathin gate metal. The device has two operation modes, i.e., current mode and capacitance mode. For current mode operation, the device exhibits 2-state characteristic with opposite readout current sign, which we define as ‘1’-state and ‘-1’-state. The device has retention time constant of about 210ms, which matches the specification of ITRS. And it has endurance of at last one million cycle of write operation. For capacitance mode operation, the device shows CV hysteresis with thinner gate metal and thin oxide layer. The level of CV hysteresis is sensitive to sweeping range and stress holding time. And the two factors are tradeoff for high sensitivity. The capacitance 2-state characteristic of the MOSCAP device has the potential to evolve into transistor memory. The device discussed in this work has advantage of simple structure, smaller feature size, CMOS process compatible, and low operation power consumption.
Chang, Po-Kai, and 張博凱. "Determination of Ultrathin Gate Oxide Thickness (＜2.0 nm) Using Low Dissipation Factor Regions of C－V Measurements." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/97235682268489213225.
Full text臺灣大學
電子工程學研究所
95
With the expeditious development of modern CMOS technology, the equivalent oxide thickness (EOT) of gate dielectric is systematically downscaled into the ultrathin range (＜2.0 nm) and becomes a key factor in the precise determination of many device parameters, such as electron/hole mobility, oxide charge density, interface trap density, breakdown field strength, etc. However, C－V curves of ultrathin oxides near the accumulation region show a disposition to roll off abruptly due to exponentially-increasing leakage current and series resistance; hence the two-frequency correction method was proposed to work out an empirical solution based on three-element circuit model. Once the oxide thickness shrank down below 2.0 nm, the error of measured capacitance could be dreadfully large, unless the two frequencies were chosen with caution. In this work, a new approach to the estimation of ultrathin oxide thickness from C－V measurement has been demonstrated. By choosing an adequate interval on the C－V curve where the dissipation factor is low enough, we can perform a simple linear regression, then comparing the experimental slope with theoretical values to find out the actual oxide thickness. This technique is valid for a 1.6 nm SiO2 capacitor, while the two-frequency correction method can hardly determine the correct value.
Book chapters on the topic "Gate Oxide Thickness Asymmetry"
Hiruta, Y., H. Oyamatsu, H. S. Momose, H. Iwai, and K. Maeguchi. "Gate Oxide Thickness Dependence of Hot Carrier Induced Degradation on PMOSFETs." In ESSDERC ’89, 732–35. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_154.
Full textJamwal, Deepika, Devi Dass, Rakesh Prasher, and Rakesh Vaid. "Impact of Scaling Gate Oxide Thickness on the Performance of Silicon Based Triple Gate Rectangular Nwfet." In Physics of Semiconductor Devices, 581–84. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03002-9_146.
Full textJethwa, Mayank Kumar, Hardiki Mukesh Devre, Yash Agrawal, and Rutu Parekh. "A Comparative Study of MOSFET (Single and Double Gate), Silicon Nanowire FET, and CNTFET by Varying the Oxide Thickness." In Lecture Notes in Electrical Engineering, 205–16. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0275-7_17.
Full textConference papers on the topic "Gate Oxide Thickness Asymmetry"
Kumar, Chethan, Neha Sharan, and Santanu Mahapatra. "indDG: A new compact model for common double gate MOSFET adapted to gate oxide thickness asymmetry." In 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2015. http://dx.doi.org/10.1109/conecct.2015.7383874.
Full textSharan, Neha, and Santanu Mahapatra. "Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry." In 2014 27th International Conference on VLSI Design. IEEE, 2014. http://dx.doi.org/10.1109/vlsid.2014.76.
Full textMasahara, M., R. Surdeanu, L. Witters, G. Doornbos, V. Nguyen, G. Den Bosch, C. Vrancken, et al. "Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs." In 2006 IEEE international SOI. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284489.
Full textJung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Oxide Thickness of Asymmetric Double Gate MOSFET." In Electrical Engineering 2013. Science & Engineering Research Support soCiety, 2013. http://dx.doi.org/10.14257/astl.2013.37.07.
Full textWada, A., K. Endo, M. Masahara, and S. Samukawa. "Asymmetric Gate-oxide Thickness Four-terminal FinFETs Fabricated using Low-Temperature and Atomically Flat interface Neutral-Beam Oxidation Process." In 2010 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2010. http://dx.doi.org/10.7567/ssdm.2010.b-5-1.
Full text"Scalability Of Plasma Damage With Gate Oxide Thickness." In 2nd International Symposium on Plasma Process-Induced Damage. IEEE, 1997. http://dx.doi.org/10.1109/ppid.1997.596669.
Full textMorimoto, T., H. S. Momose, M. Tsuchiaki, Y. Ozawa, K. Yamabe, and H. Iwai. "Limits on Gate Insulator Thickness for MISFET Operation in Pure-Oxide and Nitrided-Oxide Gate Cases." In 1991 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1991. http://dx.doi.org/10.7567/ssdm.1991.a-2-1.
Full textCheng, B., S. Roy, A. Martinez, S. Markov, and A. Asenov. "Impact of Oxide Thickness Fluctuation on MOSFETs Gate Tunnelling." In 2005 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2005. http://dx.doi.org/10.7567/ssdm.2005.p3-10.
Full textTyaginov, S. E., I. A. Starkov, O. Triebl, M. Karner, Ch Kernstock, C. Jungemann, H. Enichlmair, J. M. Park, and T. Grasser. "Impact of gate oxide thickness variations on hot-carrier degradation." In 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2012). IEEE, 2012. http://dx.doi.org/10.1109/ipfa.2012.6306265.
Full text"Effect Of Gate Oxide Thickness On Charging Damage In PIII." In 2nd International Symposium on Plasma Process-Induced Damage. IEEE, 1997. http://dx.doi.org/10.1109/ppid.1997.596729.
Full textReports on the topic "Gate Oxide Thickness Asymmetry"
Kim, J. S. The effect of the gate oxide thickness on the speed of MOS integrated circuits. Gaithersburg, MD: National Bureau of Standards, 1987. http://dx.doi.org/10.6028/nbs.ir.87-3668.
Full text