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Journal articles on the topic 'Gate Oxide Thickness Asymmetry'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.

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Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

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2

Chang, Sheng, Gaofeng Wang, Qijun Huang, and Hao Wang. "Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 56, no. 10 (October 2009): 2297–301. http://dx.doi.org/10.1109/ted.2009.2028379.

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3

Sharan, Neha, and Santanu Mahapatra. "A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 61, no. 8 (August 2014): 2732–37. http://dx.doi.org/10.1109/ted.2014.2331191.

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4

Baruah, R. K., and N. Bora. "Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry." Journal of Computational and Theoretical Nanoscience 8, no. 10 (October 1, 2011): 2025–28. http://dx.doi.org/10.1166/jctn.2011.1920.

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5

Jandhyala, Srivatsava, Rutwick Kashyap, Costin Anghel, and Santanu Mahapatra. "A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry." IEEE Transactions on Electron Devices 59, no. 4 (April 2012): 1002–7. http://dx.doi.org/10.1109/ted.2012.2184543.

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6

Sharan, Neha, and Santanu Mahapatra. "Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry." IEEE Transactions on Electron Devices 60, no. 7 (July 2013): 2419–22. http://dx.doi.org/10.1109/ted.2013.2262943.

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7

Sharan, Neha, and Santanu Mahapatra. "Compact noise modelling for common double‐gate metal–oxide–semiconductor field‐effect transistor adapted to gate‐oxide‐thickness asymmetry." IET Circuits, Devices & Systems 10, no. 1 (January 2016): 62–67. http://dx.doi.org/10.1049/iet-cds.2015.0128.

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8

Jung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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9

Jung, Hakkee. "Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 232. http://dx.doi.org/10.11591/ijece.v11i1.pp232-239.

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The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

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10

Jandhyala, S., and S. Mahapatra. "Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry." Electronics Letters 48, no. 13 (2012): 794. http://dx.doi.org/10.1049/el.2012.1295.

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11

Jung, Hakkee. "Relation of Oxide Thickness and DIBL for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 4 (April 30, 2016): 799–804. http://dx.doi.org/10.6109/jkiice.2016.20.4.799.

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12

Jung, Hakkee. "Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness." Journal of the Korea Institute of Information and Communication Engineering 20, no. 5 (May 31, 2016): 992–97. http://dx.doi.org/10.6109/jkiice.2016.20.5.992.

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13

Jung, Hak Kee, and Sima Dimitrijev. "The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (December 1, 2016): 2730. http://dx.doi.org/10.11591/ijece.v6i6.13265.

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

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14

Jung, Hak Kee, and Sima Dimitrijev. "The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 6 (December 1, 2016): 2730. http://dx.doi.org/10.11591/ijece.v6i6.pp2730-2734.

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<p>This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses.</p>

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15

Shin, Yong Hyeon, and Ilgu Yun. "Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region." Solid-State Electronics 120 (June 2016): 19–24. http://dx.doi.org/10.1016/j.sse.2016.03.002.

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16

Kang, Heebum, Hyun Wook Kim, Eun Ryeong Hong, and Jiyong Woo. "Analog synaptic behavior of mobile ion source-limited electrochemical RAM using CuO_x oxide electrode for deep learning accelerator." Applied Physics Letters 120, no. 12 (March 21, 2022): 122101. http://dx.doi.org/10.1063/5.0086164.

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We demonstrate the synaptic characteristics of analogously modulated channel currents in Cu-ion-actuated electrochemical RAM (ECRAM) based on an HfOx electrolyte and a WOx channel. Uncontrolled synaptic response is found as a function of the gate pulse when a Cu-rich gate electrode delivers mobile ions, presumably due to many ions injected from the infinite ion reservoir. As a result, we propose a CuOx oxide electrode to limit ion sources, which is indirectly validated by a physical examination of the degree of chemical bonding between Cu and oxygen, thereby boosting gate controllability over the channel. In addition, the HfOx electrolyte needs to be designed to facilitate the adequate migration of Cu ions, considering thickness and film quality. Using material stack engineering, the channel current of optimized CuOx/HfOx/WOx ECRAM can be steadily tuned via repeated identical gate pulses. The channel current and its change are proportional to the device area and the amount of migrated ions relevant to the gate pulse conditions, respectively. The homogeneous flow of ions across the entire area can, thus, be used to explain the obtained analog switching. The gate-controllable synaptic behavior of the ECRAM accelerates deep neural network training based on backpropagation algorithms. An improved pattern recognition accuracy of ∼88% for handwritten digits is achieved by linearly tuned multiple current states with more than 100 pulses and asymmetric gate voltage conditions in a three-layer neural network validated in simulation.

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17

Jung, Hakkee. "Influence of Ratio of Top and Bottom Oxide Thickness on Subthreshold Swing for Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 20, no. 3 (March 31, 2016): 571–76. http://dx.doi.org/10.6109/jkiice.2016.20.3.571.

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18

Masahara, Meishoku, Radu Surdeanu, Liesbeth Witters, Gerben Doornbos, Viet H. Nguyen, Geert Van den bosch, Christa Vrancken, et al. "Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope." IEEE Electron Device Letters 28, no. 3 (March 2007): 217–19. http://dx.doi.org/10.1109/led.2007.891303.

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19

Jung, Hakkee. "Conduction Path Dependent Threshold Voltage for the Ratio of Top and Bottom Oxide Thickness of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 11 (November 30, 2014): 2709–14. http://dx.doi.org/10.6109/jkiice.2014.18.11.2709.

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20

Popov, Vladimir P., Fedor V. Tikhonenko, Valentin A. Antonov, Ida E. Tyschenko, Andrey V. Miakonkikh, Sergey G. Simakin, and Konstantin V. Rudenko. "Diode-Like Current Leakage and Ferroelectric Switching in Silicon SIS Structures with Hafnia-Alumina Nanolaminates." Nanomaterials 11, no. 2 (January 22, 2021): 291. http://dx.doi.org/10.3390/nano11020291.

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Silicon semiconductor-insulator-semiconductor (SIS) structures with high-k dielectrics are a promising new material for photonic and CMOS integrations. The “diode-like” currents through the symmetric atomic layer deposited (ALD) HfO2/Al2O3/HfO2… nanolayers with a highest rectification coefficient 103 are observed and explained by the asymmetry of the upper and lower heterointerfaces formed by bonding and ALD processes. As a result, different spatial charge regions (SCRs) are formed on both insulator sides. The lowest leakages are observed through the stacks, with total Al2O3 thickness values of 8–10 nm, which also provide a diffusive barrier for hydrogen. The dominant mechanism of electron transport through the built-in insulator at the weak field E < 1 MV/cm is thermionic emission. The Poole-Frenkel (PF) mechanism of emission from traps dominates at larger E values. The charge carriers mobility 100–120 cm2/(V s) and interface states (IFS) density 1.2 × 1011 cm−2 are obtained for the n-p SIS structures with insulator HfO2:Al2O3 (10:1) after rapid thermal annealing (RTA) at 800 °C. The drain current hysteresis of pseudo-metal-oxide-semiconductor field effect transistor (MOSFET) with the memory window 1.2–1.3 V at the gate voltage |Vg| < ±2.5 V is maintained in the RTA treatment at T = 800–900 °C for these transistors.

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21

Singh, Shradhya, Sangeeta Singh, and Alok Naugarhiya. "Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance." International Journal of Modern Physics B 34, no. 27 (October 6, 2020): 2050242. http://dx.doi.org/10.1142/s0217979220502422.

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This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.

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22

Wada, Akira, Kazuhiko Endo, Meishoku Masahara, Chi-Hsien Huang, and Seiji Samukawa. "Fabrication of Four-Terminal Fin Field-Effect Transistors with Asymmetric Gate-Oxide Thickness Using an Anisotropic Oxidation Process with a Neutral Beam." Applied Physics Express 3, no. 9 (September 3, 2010): 096502. http://dx.doi.org/10.1143/apex.3.096502.

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23

Kumar, Ajit, and J. N. Roy. "Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs." Semiconductor Science and Technology 36, no. 1 (November 12, 2020): 015007. http://dx.doi.org/10.1088/1361-6641/abc28d.

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24

Kang, Miae, Kihyun Kim, Joona Bang, and Jihyun Kim. "Nano-Pattern Oxidation of WSe₂ Via Block Copolymer Self-Assembly for Highly Responsive Homojunction Phototransistors." ECS Meeting Abstracts MA2022-02, no. 36 (October 9, 2022): 1317. http://dx.doi.org/10.1149/ma2022-02361317mtgabs.

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Tungsten diselenide (WSe2), one of the two-dimensional (2D) materials, has emerged as a promising optoelectric candidate because of its thickness dependent bandgap, large optical absorption coefficient, good air stability and high carrier mobility. In addition, the electrical properties of the ambipolar WSe2 could be tuned through the electrostatic doping by the gate modulation. However, the low photo responsivity is a critical problem of WSe2-based optoelectric devices. To overcome this limitation, several approaches have been suggested such as stacking different 2D materials and coating with quantum dots. But these conventional methods were focused on the formation of heterojunctions, which requires complicated alignment process and leads to unavoidable defects and residues. Thus, the novel ways to build homojuction should be investigated for fabricating devices with a clean interface in a simple process. In this work, block copolymer (BCP) was used to prepare hexagonally packed cylinder nano-template as an oxidation mask for UV/ozone treatment, which resulted in numerous nanoscale homojunctions on WSe2. To fabricate the mask with hexagonally packed cylinders, asymmetric poly (styrene-block-methyl methacrylate) (PS-b-PMMA) was spin-coated. After thermal annealing for self-assembly, PMMA was selectively removed by reactive ion etching. UV/ozone treatment, one of the oxidation methods of the WSe2, leads to the formation of the the tungsten oxide (WOX) with high electron affinity and induces a p-doping effect. By using BCP as an oxidation mask, the only region of the WSe2 under the removed PMMA blocks could be converted into WOX. The responsivity of the nano-pattern oxidized WSe2 phototransistor manifests a dramatic change depending on the applied gate bias. The device exhibited a responsivity (532 nm, 8.515 mW/cm2) of 27.5 mA/W under applied gate bias of 0 V. However, under the gate bias of +60 V, the device showed an enhanced responsivity of 155.2 mA/W, as strong p-n junctions were induced. In conclusion, the nano-pattern oxidized WSe2 phototransistor presents increased responsivity (155.2 mA/W), external quantum efficiency (36.3%) and faster response time than the pristine WSe2. This work demonstrates that the responsivity of the WSe2 phototransistor can be improved though well-established perpendicular BCP and optimized by effective modulation of gate bias. By implementing homojunctions on the WSe2 via the nano-pattern oxidation method, this work greatly expands the potential applications of 2D TMDs materials for next-generation nanoscale optoelectronic devices.

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25

Vadizadeh, Mahdi, Mohammad Fallahnejad, Pegah Sotoodeh, Reyhaneh Ejlali, and Mahdis Azadmanesh. "Improving subthreshold slope in Si/InAs/Ge junctionless tunneling FET-based biosensor by using asymmetric gate oxide thickness for low-power applications: A numerical simulation study." Materials Science and Engineering: B 292 (June 2023): 116445. http://dx.doi.org/10.1016/j.mseb.2023.116445.

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26

Osburn, C. M., A. Reisman, M. Stinson, L. Lipkin, H. Berger, and C. Tollin. "Silicon Gate Oxide Thickness Uniformity during HCl Oxidation." Journal of The Electrochemical Society 138, no. 1 (January 1, 1991): 268–77. http://dx.doi.org/10.1149/1.2085554.

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27

Hassan, Md R., J. J. Liou, and A. Ortiz-Conde. "Gate-oxide thickness dependence of LDD MOSFET parameters." Solid-State Electronics 41, no. 8 (August 1997): 1199–201. http://dx.doi.org/10.1016/s0038-1101(97)00046-4.

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28

Tsujiuchi, Mikio, Toshiaki Iwamatsu, Hideki Naruoka, Hiroshi Umeda, Takashi Ipposhi, Shigeto Maegawa, and Yasuo Inoue. "Thickness dependent integrity of gate oxide on SOI." Applied Surface Science 216, no. 1-4 (June 2003): 329–33. http://dx.doi.org/10.1016/s0169-4332(03)00419-7.

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29

Yamada, Keiichi, Junji Senzaki, Kazutoshi Kojima, and Hajime Okumura. "A Novel Approach to Analysis of F-N Tunneling Characteristics in MOS Capacitor Having Oxide Thickness Fluctuation." Materials Science Forum 858 (May 2016): 433–36. http://dx.doi.org/10.4028/www.scientific.net/msf.858.433.

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The new indicators, effective gate oxide thickness tc and effective gate electrode area D, and their combination are applied for a new analysis method of Fowler-Nordheim (F-N) tunneling characteristics in MOS capacitor having oxide thickness fluctuation. This method considering the conduction properties of F-N tunneling characteristics correlates its characteristics to the oxide reliability. These indicators quantified with the influence of the oxide thickness fluctuation can provide the net values of the electric field and the current density on the gate oxide. This new analysis method will lead to reducing the evaluation time for the reliability assessment.

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30

Reddy, Morupuri Satish Kumar. "Simulation of Carbon Nanotube based Field Effect Transistor by Varying Gate Oxide Thickness to Explore its Electrical Property and Compare it with Standard Mosfet." Revista Gestão Inovação e Tecnologias 11, no. 2 (June 5, 2021): 1549–66. http://dx.doi.org/10.47059/revistageintec.v11i2.1780.

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Aim: The current and voltage characteristics of CNTFET and MOSFET are simulated by varying their gate oxide thickness ranging from 3.5nm to 11.5nm. Materials and Methods: The electrical conductance of CNTFET (n = 320) was compared with MOSFET (n = 320) by varying gate oxide thickness ranging from 3.5nm to 11.5nm in the NanoHUB© tool simulation environment. Results: CNTFET has significantly higher conductance (12.52 mho) than MOSFET (12.07 mho). The optimal thickness for maximum conductivity was 4nm for CNTFET and 3.5 nm for MOSFET. Conclusion: Within the limits of this study, CNTFET with the gate oxide thickness of 4 nm offers the best conductivity.

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31

Agopian, Paula G. D., João Antonio Martino, Eddy Simoen, and Cor Claeys. "Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology." Journal of Integrated Circuits and Systems 3, no. 2 (November 18, 2008): 91–95. http://dx.doi.org/10.29292/jics.v3i2.287.

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In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reduction and an overlap tendency of the first and the second transconductance peaks is observed.

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32

Taylor, Seth T., John Mardinly, and Michael A. O'Keefe. "HRTEM Image Simulations for the Study of Ultrathin Gate Oxides." Microscopy and Microanalysis 8, no. 5 (October 2002): 412–21. http://dx.doi.org/10.1017/s1431927602020123.

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We have performed high resolution transmission electron microscope (HRTEM) image simulations to qualitatively assess the visibility of various structural defects in ultrathin gate oxides of MOSFET devices, and to quantitatively examine the accuracy of HRTEM in performing gate oxide metrology. Structural models contained crystalline defects embedded in an amorphous 16-Å-thick gate oxide. Simulated images were calculated for structures viewed in cross section. Defect visibility was assessed as a function of specimen thickness and defect morphology, composition, size, and orientation. Defect morphologies included asperities lying on the substrate surface, as well as “bridging” defects connecting the substrate to the gate electrode. Measurements of gate oxide thickness extracted from simulated images were compared to actual dimensions in the model structure to assess TEM accuracy for metrology. The effects of specimen tilt, specimen thickness, objective lens defocus, and coefficient of spherical aberration (Cs) on measurement accuracy were explored for nominal 10-Å gate oxide thickness. Results from this work suggest that accurate metrology of ultrathin gate oxides (i.e., limited to several percent error) is feasible on a consistent basis only by using a Cs-corrected microscope. However, fundamental limitations remain for characterizing defects in gate oxides using HRTEM, even with the new generation of Cs-corrected microscopes.

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33

Chien, Nguyen Dang, Dao Thi Kim Anh, and Chun-Hsing Shih. "Roles of Gate-Oxide Thickness Reduction in Scaling Bulk and Thin-Body Tunnel Field-Effect Transistors." Vietnam Journal of Science and Technology 55, no. 3 (June 16, 2017): 316. http://dx.doi.org/10.15625/2525-2518/55/3/8362.

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Tunnel field-effect transistor (TFET) has recently been considered as a promising candidate for low-power integrated circuits. In this paper, we present an adequate examination on the roles of gate-oxide thickness reduction in scaling bulk and thin-body TFETs. It is shown that the short-channel performance of TFETs has to be characterized by both the off-current and the subthreshold swing because their physical origins are completely different. The reduction of gate-oxide thickness plays an important role in maintaining low subthreshold swing whereas it shows a less role in suppressing off-state leakage in short-channel TFETs with bulk and thin-body structures. When scaling the gate-oxide thickness, the short-channel effect is suppressed more effectively in thin-body TFETs than in bulk devices. Clearly understanding the roles of scaling gate-oxide thickness is necessary in designing advanced scaled TFET devices.

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34

Pratap, Surender, and Niladri Sarkar. "Application of the Density Matrix Formalism for Obtaining the Channel Density of a Dual Gate Nanoscale Ultra-Thin MOSFET and its Comparison with the Semi-Classical Approach." International Journal of Nanoscience 19, no. 06 (November 27, 2020): 2050010. http://dx.doi.org/10.1142/s0219581x20500106.

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Density Matrix Formalism using quantum methods has been used for determining the channel density of dual gate ultra-thin MOSFETs. The results obtained from the quantum methods have been compared with the semi-classical methods. This paper discusses in detail the simulation methods using self-consistent schemes and the discretization procedures for constructing the Hamiltonian Matrix for a dual gate MOSFET consisting of oxide/semiconductor/oxide interface and the self-consistent procedure involving the discretization of Poisson’s equation for satisfying the charge neutrality condition in the channel of different thicknesses. Under quantum methods, the channel densities are determined from the diagonal elements of the density matrix. This successfully simulates the size quantization effect for thin channels. For semi-classical methods, the Fermi–Dirac Integral function is used for the determination of the channel density. For thin channels, the channel density strongly varies with the values of the effective masses. This variation is simulated when we use Quantum methods. The channel density also varies with the asymmetric gate bias and this variation is more for thicker channels where the electrons get accumulated near the oxide/semiconductor interface. All the calculations are performed at room temperature (300[Formula: see text]K).

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35

Taylor, S., J. Mardinly, M. A. O'Keefe, and R. Gronsky. "HRTEM Image Simulations for Gate Oxide Metrology." Microscopy and Microanalysis 6, S2 (August 2000): 1080–81. http://dx.doi.org/10.1017/s1431927600037892.

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High resolution transmission electron microscopy (HRTEM) has found extensive use in the semiconductor industry for performing device metrology and characterization. However, shrinking device dimensions (gate oxides are rapidly approaching 10Å) present challenges to the use of HRTEM for many applications, including gate oxide metrology. In this study, we performed HRTEM image simulations of a MOSFET device to examine the accuracy of HRTEM in measuring gate oxide thickness. Length measurements extracted from simulated images were compared to actual dimensions in the model structure to assess TEM accuracy. The effects of specimen tilt, specimen thickness, objective lens defocus and coefficient of spherical aberration (CS) on measurement accuracy were explored for nominal 10Å and 16Å gate oxide thicknesses.The gate oxide was modeled as an amorphous silicon oxide situated between a gate electrode and substrate, both modeled as single crystal Si(100). Image simulations of the sandwich structure were performed in cross-section (with Si[110] parallel to beam direction) using the multislice approximation for a 200 kV microscope with Cs=0.5mm.

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Toyoshima, Y., H. Iwai, F. Matsuoka, H. Hayashida, K. Maeguchi, and K. Kanzaki. "Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's." IEEE Transactions on Electron Devices 37, no. 6 (June 1990): 1496–503. http://dx.doi.org/10.1109/16.106245.

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Harris, H., K. Choi, N. Mehta, A. Chandolu, N. Biswas, G. Kipshidze, S. Nikishin, S. Gangopadhyay, and H. Temkin. "HfO2 gate dielectric with 0.5 nm equivalent oxide thickness." Applied Physics Letters 81, no. 6 (August 5, 2002): 1065–67. http://dx.doi.org/10.1063/1.1495882.

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Hiraiwa, Atsushi, Satoshi Sakai, Dai Ishikawa, and Masatoshi Nakazawa. "Experimental determination of equivalent oxide thickness of gate insulators." Journal of Applied Physics 91, no. 10 (2002): 6571. http://dx.doi.org/10.1063/1.1469694.

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Vuong, H. H., J. Bude, F. H. Baumann, K. Evans-Lutterodt, J. Ning, Y. Ma, J. Mcmacken, et al. "Effect of implant damage on the gate oxide thickness." Solid-State Electronics 43, no. 5 (May 1999): 985–88. http://dx.doi.org/10.1016/s0038-1101(99)00050-7.

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Cho, Hyun, K. P. Lee, B. P. Gila, C. R. Abernathy, S. J. Pearton, and F. Ren. "Influence of gate oxide thickness on Sc2O3/GaN MOSFETs." Solid-State Electronics 47, no. 10 (October 2003): 1757–61. http://dx.doi.org/10.1016/s0038-1101(03)00128-x.

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Widdershoven, Frans P. "Extraction of gate oxide thickness from C–V measurements." Microelectronic Engineering 59, no. 1-4 (November 2001): 271–75. http://dx.doi.org/10.1016/s0167-9317(01)00609-8.

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Lombardo, S., J. H. Stathis, and B. P. Linder. "Dependence of Post-Breakdown Conduction on Gate Oxide Thickness." Microelectronics Reliability 42, no. 9-11 (September 2002): 1481–84. http://dx.doi.org/10.1016/s0026-2714(02)00174-9.

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Ortega, Richard, Scott Baumann, R. S. Hockett, H. Murakami, and V. Ramakrishnan. "Hf-related Gate Oxide Thickness Mapping Using XRR/XRF." ECS Transactions 11, no. 3 (December 19, 2019): 281–92. http://dx.doi.org/10.1149/1.2778671.

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Jiunn-Yann Tsai, Ying Shi, S. Prasad, S. W. C. Yeh, and R. Rakkhit. "Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate." IEEE Electron Device Letters 19, no. 9 (September 1998): 348–50. http://dx.doi.org/10.1109/55.709640.

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Chen, Kai, H. Clement Wann, Jon Dunster, Ping K. Ko, Chenming Hu, and Makoto Yoshida. "MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages." Solid-State Electronics 39, no. 10 (October 1996): 1515–18. http://dx.doi.org/10.1016/0038-1101(96)00059-7.

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Nam, Kab-Jin, Kee-Won Kwon, and Byoungdeog Choi. "Reliability Analysis on TiN Gated NMOS Transistors." Science of Advanced Materials 13, no. 6 (June 1, 2021): 1178–85. http://dx.doi.org/10.1166/sam.2021.3986.

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Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

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Valentina. "Adaptive Complementary Metal-Oxide-Semiconductor Device by Externally Controlled Gate Oxide Thickness." Journal of Computer Science 8, no. 4 (October 1, 2012): 515–22. http://dx.doi.org/10.3844/jcssp.2012.515.522.

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Bearda, Twan, Michel Houssa, Paul W. Mertens, Jan Vanhellemont, and Marc Heyns. "Observation of critical gate oxide thickness for substrate-defect related oxide failure." Applied Physics Letters 75, no. 9 (August 30, 1999): 1255–57. http://dx.doi.org/10.1063/1.124659.

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Kojima, Takahito, Shinsuke Harada, Keiko Ariyoshi, Junji Senzaki, Manabu Takei, Yoshiyuki Yonezawa, Yasunori Tanaka, and Hajime Okumura. "Reliability Improvement and Optimization of Trench Orientation of 4H-SiC Trench-Gate Oxide." Materials Science Forum 778-780 (February 2014): 537–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.537.

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Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.

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Patel, Dax, Soham Sojitra, Jay Kadia, Bhavik Chaudhary, and Rutu Parekh. "Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters." Trends in Sciences 19, no. 7 (March 14, 2022): 3216. http://dx.doi.org/10.48048/tis.2022.3216.

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A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively. HIGHLIGHTS Comparative study of Double Gate and Silicon on Insulator MOSFET Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET Contour plot for electron concentration and potential GRAPHICAL ABSTRACT

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