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Relevant bibliographies by topics / Gated Continuous Logic Networks

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Journal articles

Academic literature on the topic 'Gated Continuous Logic Networks'

Author: Grafiati

Published: 6 September 2023

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Journal articles on the topic "Gated Continuous Logic Networks"

1

Boukadida, Souha, Soufien Gdaim, and Abdellatif Mtiba. "Sensor Fault Detection and Isolation Based on Artificial Neural Networks and Fuzzy Logic Applicated on Induction Motor for Electrical Vehicle." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 2 (2017): 601. http://dx.doi.org/10.11591/ijpeds.v8.i2.pp601-611.

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<p>Recently, research has picked up a fervent pace in the area of fault diagnosis of electrical vehicle. Like failures of a position sensor, a voltage sensor, and current sensors. Three-phase induction motors are the “workhorses” of industry and are the most widely used electrical machines. This paper presents a scheme for Fault Detection and Isolation (FDI). The proposed approach is a sensor-based technique using the mains current measurement. Current sensors are widespread in power converters control and in electrical drives. Thus, to ensure continuous operation with reconfiguration control, a fast sensor fault detection and isolation is required. In this paper, a new and fast faulty current sensor detection and isolation is presented. It is derived from intelligent techniques. The main interest of field programmable gate array is the extremely fast computation capabilities. That allows a fast residual generation when a sensor fault occurs. Using of Xilinx System Generator in Matlab / Simulink allows the real-time simulation and implemented on a field programmable gate array chip without any VHSIC Hardware Description Language coding. The sensor fault detection and isolation algorithm was implemented targeting a Virtex5. Simulation results are given to demonstrate the efficiency of this FDI approach.</p>

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2

Tran, Duc M., Kyungah Kim, and Joon-Young Choi. "CLB-Based Development of BiSS-C Interface Master for Motor Encoders." Electronics 12, no. 4 (2023): 886. http://dx.doi.org/10.3390/electronics12040886.

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Encoder interfaces should be operated in real time with high precision and fast processing for industrial motor control systems. The continuous bidirectional serial synchronous (BiSS-C) interface is an open-source serial communication protocol designed for motor encoders and is suitable for industrial purposes because of its fast serial communication speed. In this study, we propose a method for developing a BiSS-C interface master for a motor encoder slave, using only the configurable logic block (CLB) peripheral integrated into TI microcontroller units. By analyzing the detailed operation protocol of the BiSS-C interface, we create the truth and state tables for logic circuits and finite state machines, which are required for the BiSS-C interface master. Then, by programming the CLB based on the created truth and state tables, we implement the master clock, serial peripheral interface (SPI) clock, and operational process for the master. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are not required for the master implementations. The developed method can be immediately applied to developing the masters for other BiSS-C encoders with different specifications, which is certainly necessary for a motor drive development and test. By building an AC motor control system with the developed master and performing various experiments, we verify the performance and practical usefulness of the developed BiSS-C interface master. The maximum master clock frequency without any CRC errors is achieved by 6.25 MHz, which can cope with more than 20 kHz motor control cycle frequency. The usefulness is demonstrated by showing the motor speed and position control performance that are acceptable in real applications.

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3

KIROLOS, SAMI, and YEHIA MASSOUD. "DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE." Journal of Circuits, Systems and Computers 17, no. 05 (2008): 871–83. http://dx.doi.org/10.1142/s0218126608004630.

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In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

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4

Plyusnin, Nikolay. "Tunable logic of complex variables and quantum networks on its basis." Robotics and Technical Cybernetics 10, no. 4 (2022): 267–74. http://dx.doi.org/10.31776/rtcj.10404.

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Continuous - additive-multiplicative (AM) logic is considered, in which logical operations are replaced by algebraic operations («×» and «+») or operations with vectors, and binary variables «0» and «1» are replaced by continuous scalar ones («0- 1») or complex variables. To build this logic, a continuous analogue of the canonical form of Boolean logic is used in the form of a perfect disjunctive or conjunctive normal form (KAM logic). A feature of KAM logic is a continuous dependence on input variables and a potential variety of continuous logic functions. Based on the previously proposed «fuzzy» (distributed) continuous function, in the form of a superposition of «clear» functions, and the tunable QAM element circuit that implements it, this element is generalized to a network QAM element with several tunable outputs. The multiplication functions in this QAM element can be performed using a known memristor, which can be replaced by a memtransistor based on a field effect transistor. In quantum QAM networks, these elements are, respectively: «k-memristor» and «k-memtransistor». One of the options for a k-memtransistor is a composite hybrid spin-field-effect transistor based on a planar spin valve with magnetic memory and a field-effect transistor with a ferroelectric memory. It is noted that the main technological problem of quantum QAM networks based on such a hybrid spin transistor is the creation of planar conducting and ferromagnetic elements based on ultrathin metallic and ferromagnetic films on silicon.

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5

Li, Zhitao, Yuqian Guo, and Weihua Gui. "Asymptotical feedback controllability of continuous-time probabilistic logic control networks." Nonlinear Analysis: Hybrid Systems 47 (February 2023): 101265. http://dx.doi.org/10.1016/j.nahs.2022.101265.

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6

Yadav, Neetika, Neeta Pandey, and Deva Nand. "Leakage reduction in dual mode logic through gated leakage transistors." Microprocessors and Microsystems 84 (July 2021): 104269. http://dx.doi.org/10.1016/j.micpro.2021.104269.

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7

Chen, Lanlan. "Secure Data Sequence Recognition of All-Optical High-Speed Network Using Semiconductor Optical Amplifier." Journal of Nanoelectronics and Optoelectronics 16, no. 10 (2021): 1667–74. http://dx.doi.org/10.1166/jno.2021.3124.

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Semiconductor optical amplifier (SOA) has nonlinear optical effect and integration advantages, and is widely used in all-optical logic gates. Hence, it is used in the identification of all-optical high-speed network security data sequences. First, the SOA model is established and then simplified based on the existing model. On this basis, the identification model of all-optical high-speed network security data sequence is established, and the concept of integrated turbo-switch is introduced. The structure of the turbo-switch is analyzed. Then, an integrated turbo-switch architecture based on SOA-Mach Zehnder interferometer (MZI) is proposed, and its performance is verified by simulation. A data sequence recognition method for all-optical high-speed network security is proposed based on the integrated acceleration switch, and the difficulty of result recognition is analyzed. The simulation results of integrated turbo-switch show that when 1550 nm light passes through MZI, the interference can be almost completely cancelled, and the corresponding phase difference of 1538 nm light is less than 3 radians, that is, some light can pass through MZI. After the bias current of SOA of upper and lower arms of SOA-MZI is properly adjusted, MZI can play the function of tunable filter. Adjusting the bias current of SOA1 and SOA2 in the turbo-switch can control the “overshoot” program in the gain recovery curve, make SOA2 in a saturated working state, optimize the gain recovery curve, and improve the SOArelated mode effect, so that the turbo-switch can also output a more stable waveform under continuous “1” input. The recognition difficulty test shows that the target sequence after the cycle and the data sequence to be recognized are used for the “Exclusive NOR” operation, and the “AND gate” is added to realize the data sequence recognition and reduce the recognition difficulty.

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8

Buckley, J. J., and Yoichi Hayashi. "Numerical relationships between neural networks, continuous functions, and fuzzy systems." Fuzzy Sets and Systems 60, no. 1 (1993): 1–8. http://dx.doi.org/10.1016/0165-0114(93)90283-n.

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9

Csiszár, Orsolya, Gábor Csiszár, and József Dombi. "Interpretable neural networks based on continuous-valued logic and multicriteria decision operators." Knowledge-Based Systems 199 (July 2020): 105972. http://dx.doi.org/10.1016/j.knosys.2020.105972.

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10

Sturlaugson, Liessman, Logan Perreault, and John W. Sheppard. "Factored performance functions and decision making in continuous time Bayesian networks." Journal of Applied Logic 22 (July 2017): 28–45. http://dx.doi.org/10.1016/j.jal.2016.11.030.

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