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Journal articles on the topic 'GDI TECHNIQUE'

Author: Grafiati

Published: 11 September 2023

Last updated: 25 July 2025

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1

Laxmi, Kumre1 Ajay Somkuwar2 and Ganga Agnihotri3. "POWER EFFICIENT CARRY PROPAGATE ADDER." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–10. https://doi.org/10.5281/zenodo.3364247.

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Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and simulated using

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Mathiyazhagan, Deepika, Dhanasekar Subramaniyam, and Thiyagarajan Nallusamy. "DESIGN OF AREA & POWER EFFICIENT MGDI FULL ADDER USING POWER GATING TECHNIQUE." Suranaree Journal of Science and Technology 31, no. 4 (2024): 0010311(1–11). http://dx.doi.org/10.55766/sujst-2024-04-e01061.

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Full adders are utilized in many different appeals, in digital signal processors, microprocessors & microcontrollers, and are an essential component of the design of many digital systems. Great control is needed in electronic devices and circuits, which necessitates low power and rapid processing. The power gated MGDI complete full adder style analysis and design are displayed. Some low power complexity is retained in this entire adder. The presentation and appeal of MGDI full adder with existing adders, such as GDI and M-GDI. The solution of the power gated- MGDI full-adder demonstrated b

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Saxena, Rimjhim, and Kiran Sharma. "Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique." SMART MOVES JOURNAL IJOSCIENCE 6, no. 2 (2020): 1–12. http://dx.doi.org/10.24113/ijoscience.v6i2.264.

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In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and

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Shankar, M., and K. Rajesh Kumar. "AREA PLANNING & EFFECTIVE MGDI COMPLETE ACCESSORIES WITH POWERFUL TECHNOLOGY." Journal of Innovations in Business and Industry 2, no. 2 (2024): 55–62. http://dx.doi.org/10.61552/jibi.2024.02.001.

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Full adders are utilized in many different appeals, in digital signal processors, microprocessors & microcontrollers, and are an essential component of the design of many digital systems. Great control is needed in electronic devices and circuits, which necessitates low power and rapid processing. The power gated MGDI complete full adder style analysis and design are displayed. Some low power complexity is retained in this entire adder. The presentation and appeal of MGDI full adder with existing adders, such as GDI and M-GDI. The solution of the power gated- MGDI full-adder demonstrated b

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Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

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Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to r

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Mangalam, Dr H. "Design and Implementation of Low Power 4:2 Compressor using GDI Technique." International Journal for Research in Applied Science and Engineering Technology 13, no. 5 (2025): 656–60. https://doi.org/10.22214/ijraset.2025.70208.

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Abstract: The objective is to develop a 4:2 compressor with GDI technique (Gate Diffusion Input). This is specifically aimed at reducing power consumption and digital circuit delays. The proposed GDI-based 4:2 compressor is compared to two existing designs: traditional CMOS design and 8T XOR-XNOR design. The results show that the GDI design saves 75.34% of the power consumptioncompared to traditional CMOS designs and 48.81% compared to the 8T XOR- XNOR designs. One of the main applications of this compressor is the design of multipliers, which is essentially important for efficient arithmetic

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Gurwinder, Singh, and Singh Ramanjeet. "COMPARISON OF GDI BASED D FLIP FLOP CIRCUITS USING 90NM AND 180NM TECHNOLOGY." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 3 (2016): 689–94. https://doi.org/10.5281/zenodo.48337.

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Energy performance requirements are forcing designers of next-generation systems to explore approaches to lease possible power consumption. Power consumption is majorly affected by power supply voltage. Scaling of power supply voltage is major factor to reduce power consumption. The technique to achieve ultra-low power is to operate the circuit with supply voltage less than threshold voltage. The region where supply voltage is less than threshold voltage is called sub threshold region. Ultra-low power consumption can be achieved by operating digital circuits at sub threshold region. Here propo

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B Sangeeth Kumar,, Pyasa Dileep and A. Satyanarayana. "Design of Low Power & Area Efficient of 8-Bit Comparator using GDI Technique." International Journal for Modern Trends in Science and Technology, no. 8 (August 7, 2020): 62–65. http://dx.doi.org/10.46501/ijmtst060812.

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In this paper we are design a circuit based on data selector and distributor networks in which we will not realize the circuit based upon the expressions but off course the circuit which have designed will have internally some expression. In the recent trends the need for low power and less on-chip area is on high note for the portable devices. In this project we want to focus on the design constraints of VLSI. Innovative design of 8-Bit GDI based Comparator will be proposed and implemented. Optimization depends on selection of GDI Cell as well as selection of primary inputs to the terminals o

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A.S., Prabhu, Naveena B, Parimaladevi K, Samundeswari M, and Thilagavathy P. "Serial Divider Using Modified GDI Technique." IJIREEICE 3, no. 10 (2015): 73–76. http://dx.doi.org/10.17148/ijireeice.2015.31017.

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Solomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.

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Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the

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Merrin, Mary Solomon, Gupta Neeraj, and Gupta Rashmi. "HIGH SPEED ADDER USING GDI TECHNIQUE." INTERNATIONAL JOURNAL OF ENGINEERING TECHNOLOGIES AND MANAGEMENT RESEARCH 5, no. 2 :SE (2018): 130–36. https://doi.org/10.5281/zenodo.1202072.

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Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the

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Sehrawat, Arjun, Vandana Khanna, and Kushal Jindal. "Comparative Study of CMOS Logic and Modified GDI Technique for Basic Logic Gates and Code Convertor." International Journal of Advance Research and Innovation 9, no. 3 (2021): 70–85. http://dx.doi.org/10.51976/ijari.932111.

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For designing low power digital circuits with better reliability and performance along with less propagation delay, Gate Diffusion Input (GDI) is one such technique. It also significantly reduces the area and delay of a circuit. It is a low power technique which requires a smaller number of transistors to achieve desired outputs with lower design complexity as compared to CMOS logic or Pass Transistor Logic. In a basic GDI cell, 3 terminals namely Gate, Source and Drain are treated as inputs. In this work, circuits like logic gates, and Binary to Gray code convertor have been designed using CM

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Tyagi, Priyanka, Sanjay Kumar Singh, and Piyush Dua. "Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (2021): 415–27. http://dx.doi.org/10.2174/2352096514666210106094136.

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Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advanta

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R., Manjunath. "LOW POWER OPTIMIZATION OF FULL ADDER CIRCUIT BASED ON GDI LOGIC FOR BIOMEDICAL APPLICATIONS." International Journal of Advanced Research 10, no. 10 (2022): 457–67. http://dx.doi.org/10.21474/ijar01/15511.

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Advanced Electronic Devices have recently become more prevalent, designers have opted for low power, quick speed, and compact designs and processes. Even though there are numerous design methodologies currently in use for VLSI system design optimization, very few design techniques produce solutions that are optimally optimal. GDI-based circuits are becoming increasingly important since they use less space, power, and energy. The GDI technique ensures minimal propagation delay, power, and area in low-power design strategies. For 45nm technology, the Cadence Virtuoso EDA tool is utilised to dete

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Vinod Kumar, Nayakallu, and Dr F. Vincy Lloyd. "Review on Low Power Alu Design Using Various Techniques." International Journal of Communication Networks and Information Security 15, no. 04 (2023): 352–59. http://dx.doi.org/10.36893/ijcnis.2023.v15i4.7147.

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VLSI technology has advanced significantly, and there arenumerous effective methods for creating VLSI circuits. PTL, GDI(Gate Diffusion Input) methods, and CMOS are a few of the styles.The weaknesses of CMOS and PTL approaches can be eliminatedby using the GDI technique to create low-power digitalcombinatorial circuits. This method maintains a low level of logicdesign complexity while lowering the amount of power consumed,propagation latency, and size of digital circuits. This paper discussesthe benefits and limitations of GDI compared to CMOS design bycomparing the various approaches with res

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Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

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Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick res

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Teoh Yong Keong, Siti Fatimah Abd Rahman, Mohamad Faris Mohamad Fathil, Mohamed Fauzi Packeer Mohamed, Adilah Ayoib, and Thikra S. Dhahi. "High Efficiency Carry Save Adder using Modified–gate Diffusion Input Technique." International Journal of Nanoelectronics and Materials (IJNeaM) 17, June (2024): 53–59. http://dx.doi.org/10.58915/ijneam.v17ijune.835.

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Addition is a fundamental function in the design of a digital system, necessary for applications such as signal processing, arithmetic operations, multiplexers, and control systems. Hence, the digital system’s performance is considerably reliant on the efficiency of the adders. Therefore, designing a 4-bit carry save adder (CSA) that consumes less power, occupies a smaller area, and operates at a higher speed is proposed using the modified–gate diffusion input (MOD–GDI) technique. The primary focus is to reduce the area occupied by decreasing the transistor count as compared with other logic s

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O. Homa Kesav and N. Sai Prasanna. "Implementation of a Static Contention Free Characteristics Differential Flip Flop Using GDI in Clock Gating Technique." International Research Journal on Advanced Engineering Hub (IRJAEH) 2, no. 09 (2024): 2303–7. http://dx.doi.org/10.47392/irjaeh.2024.0315.

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This paper introduces the design of a differential flip-flop featuring static contention- free characteristics, achieved through the implementation of a GDI-AND arrangement within a clock gating technique. The proposed approach aims to enhance the reliability and performance of flip-flops in digital circuits, particularly in applications demanding low-voltage and low-power operation. By incorporating a GDI-AND structure in the clock gating technique, contention issues are minimized, ensuring stable and efficient operation. The abstract outlines the design methodology, emphasizing the integrati

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Gupta, Shashank, and Subodh Wairya. "Hybrid Code Converters using Modified GDI Technique." International Journal of Computer Applications 143, no. 7 (2016): 12–19. http://dx.doi.org/10.5120/ijca2016910248.

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Ponnian, Jebashini, Senthil Pari, Uma Ramadass, and Chee Pun Ooi. "A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm." Emerging Science Journal 7, no. 4 (2023): 1364–94. http://dx.doi.org/10.28991/esj-2023-07-04-022.

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The challenges of innovative IC technology typically come with various new design constraints in terms of circuit implementation, behaviour, scaling, and an accurate power-delay model to evaluate the circuit's performance. The circuit realization technique using GDI is gaining popularity because of its power and transistor utilization factors. Considering the core advantage of the GDI technique, this research presents the creation of new GDI library cells implemented using the MUX-based algorithm and its delay-power model. This research defines two goals; the former goal depicts the proposal o

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N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.

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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary pe

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Kumre, Laxmi, Ajay Somkuwar, and Ganga Agnihotri. "Analysis of GDI Technique for Digital Circuit Design." International Journal of Computer Applications 76, no. 16 (2013): 41–48. http://dx.doi.org/10.5120/13335-0934.

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Durga, Gaddam Naga, and D. V. A. N. Ravi Kumar. "Gdi Technique Based Carry Look Ahead Adder Design." IOSR Journal of VLSI and Signal Processing 4, no. 6 (2014): 01–09. http://dx.doi.org/10.9790/4200-04610109.

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Anand, Krishnan S., and B. Ramesh K. "4-BIT Arithmetic Logic Unit (ALU) using Full Swing GDI Technique." Journal of Advancement in Electronics Design 4, no. 3 (2022): 1–8. https://doi.org/10.5281/zenodo.6344301.

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<em>This paper presents a layout of a 4-bit mathematic logic unit (ALU) via taking vantage of the idea of gate diffusion input (GDI) technique. ALU is the maximum crucial and middle element of vital processing unit as well as of numbers of embedded machine and microprocessors. In this, ALU consists of 4x1 multiplexer, 2x1 multiplexer and occasional power complete adder designed to implements logic operations. Complete swing GDI cells are used inside the design of multiplexers and full adder that are the related to comprehend ALU. The simulation is carried out DSCH3.5 and mircowind3.five simula

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Reissing, J., H. Peters, J. M. Kech, and U. Spicher. "Experimental and numerical analyses of the combustion process in a direct injection gasoline engine." International Journal of Engine Research 1, no. 2 (2000): 147–61. http://dx.doi.org/10.1243/1468087001545100.

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Gasoline direct injection (GDI) spark ignition engine technology is advancing at a rapid rate. The development and optimization of GDI engines requires new experimental methods and numerical models to analyse the in-cylinder processes. Therefore the objective of this paper is to present numerical and experimental methods to analyse the combustion process in GDI engines. The numerical investigation of a four-stroke three-valve GDI engine was performed with the code KIVA-3V [1]. For the calculation of the turbulent combustion a model for partially premixed combustion, developed and implemented b

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Mohammadreza, Fadaei. "Designing ALU using GDI method." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 3 (2019): 151–61. https://doi.org/10.11591/ijres.v8.i3.pp151-161.

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As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need

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Suresh, N., K. Subba Rao, and R. Vassoudevan. "Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1595–99. http://dx.doi.org/10.1166/jctn.2020.8407.

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Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce th

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Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of

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Pokhriyal, Nidhi, and Neelam Rup Prakash. "Area Efficient Low Power Compressor Design Using GDI Technique." International Journal of Engineering Trends and Technology 12, no. 3 (2014): 132–35. http://dx.doi.org/10.14445/22315381/ijett-v12p224.

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Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.

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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and ot

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Panarelli, Joseph F., and Anna T. Do. "Bleb Management Following Trabeculectomy and Glaucoma Drainage Device Implantation." US Ophthalmic Review 16, no. 2 (2022): 76. http://dx.doi.org/10.17925/usor.2022.16.2.76.

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While treatment options available to patients with glaucoma are expanding, trabeculectomy and glaucoma drainage device implantation (GDI) remain a mainstay in glaucoma surgical care. This article reviews key aspects of bleb management following trabeculectomy and GDI surgery. Basics of postoperative management of trabeculectomy and GDIs are reviewed, as well as how to manage complications such as early and late bleb leaks, fibrosis, bleb dysesthesia and the hypertensive phase. In general, careful surgical technique, close postoperative monitoring and appropriate intervention can help patients

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Pokhriyal, Nidhi, and Neelam Rup Prakash. "Area Efficient Low Power Vedic Multiplier Design Using GDI Technique." International Journal of Engineering Trends and Technology 15, no. 4 (2014): 196–99. http://dx.doi.org/10.14445/22315381/ijett-v15p238.

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Kaur, Ranbirjeet, and Rajesh Mehra. "Power and Area Efficient CMOS Half Adder using GDI Technique." International Journal of Engineering Trends and Technology 36, no. 8 (2016): 401–5. http://dx.doi.org/10.14445/22315381/ijett-v36p274.

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Dabhade, Priyanka, and Amol Boke. "Design and Analyse Low Power Wallace Multiplier Using GDI Technique." IOSR Journal of Electronics and Communication Engineering 12, no. 02 (2017): 49–54. http://dx.doi.org/10.9790/2834-1202034954.

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Nagarajan, Manikandan, Rajappa Muthaiah, Yuvaraja Teekaraman, Ramya Kuppusamy, and Arun Radhakrishnan. "Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model." Computational Intelligence and Neuroscience 2022 (March 19, 2022): 1–15. http://dx.doi.org/10.1155/2022/3505439.

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Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (G

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Naveena, C., and S. Purushothaman. "Design of Self Calibrated DLL Based Clock Generator Using Modified GDI Technique." International Journal of Scientific Engineering and Research 5, no. 3 (2017): 67–70. https://doi.org/10.70729/ijser151290.

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Saranya, R., B. Paulchamy, K. Kalpana, V. V. Teresa, and P. Logamurthy. "Area-Delay-Power-Efficient GDI Architecture Select Adder to Carry." E3S Web of Conferences 616 (2025): 02005. https://doi.org/10.1051/e3sconf/202561602005.

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The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select A

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Et. al., J. Nageswara Reddy ,. "Power Efficient Two Transistor Exclusiveor Gate for Full Adder Usinggdi in 45NM." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (2021): 1342–47. http://dx.doi.org/10.17762/turcomat.v12i2.1230.

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The principle part of ALU (Arithmetic rationale unit) is the Full Adder. This paper tells the best way to perform quick arithmetic activities created utilizing GDI. The fundamental point of this paper is to plan the full adder of two semiconductor utilizing Gate diffusion input (GDI) strategy. The plan of full adder is appropriate for the two semiconductor EX-OR gate. The primary intension of novel technique is fully founded on Full adder plan of 2TEX OR gate which is utilized to decrease power and improve the speed with an advanced territory of number of semiconductor check which is less simi

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Khalkho, Rekha, and Souvik Ghosh. "Crafting a Gender Disparity Index to Unveiling the Tea Garden Workers’ Gender Dynamics." Indian Journal of Extension Education 59, no. 4 (2023): 145–49. http://dx.doi.org/10.48165/ijee.2023.59429.

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Gender dynamics significantly impact tea garden workers’ performance. A Gender Disparity Index (GDI) was developed for assessing gender differences within the tea plantation sector during 2022-23. The construction of GDI commenced with item analysis, employing the Likert’s Technique. A total of seven dimensions were included following the Harvard analytical and Moser frameworks of gender analysis. Based on the relevancy, t statistics, and content validity, five dimensions were kept in the index, namely, activity profile, influencing factors for differential roles, gender role identification, g

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Anitha, M., J. Princy joice, and Mrs Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select adder Using Modified GDI Technique." International Journal of Engineering Research 4, no. 3 (2015): 127–29. http://dx.doi.org/10.17950/ijer/v4s3/309.

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Sharma, Priyanka. "High Performance Sense Amplifier based Flip Flop Design using GDI Technique." International Journal of Advanced engineering, Management and Science 3, no. 4 (2017): 350–54. http://dx.doi.org/10.24001/ijaems.3.4.11.

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Murthy, CRavindra. "Low Power Design Bi – Directional Shift Register By using GDI Technique." International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 4 (2015): 2367–73. http://dx.doi.org/10.17762/ijritcc2321-8169.1504128.

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Sivathanu, Yudaya, Jongmook Lim, Ariel Muliadi, Oana Nitulescu, and Tom Shieh. "Estimating velocity in Gasoline Direct Injection sprays using statistical pattern imaging velocimetry." International Journal of Spray and Combustion Dynamics 11 (June 28, 2018): 175682771877828. http://dx.doi.org/10.1177/1756827718778289.

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Statistical pattern imaging velocimetry (SPIV) is a new technique for the estimation of the planar velocity field from the high-speed videos. SPIV utilizes an ensemble of either backlit or side lit videos to obtain full planar velocities in sprays and flames. Unlike conventional particle imaging velocimetry, statistical pattern imaging velocimetry does not require well-resolved images of particles within turbulent flows. Instead, the technique relies of patterns formed by coherent structures in the flow. Therefore, SPIV is well suited for the estimating planar velocities in sprays and turbulen

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Di Ilio, Giovanni, Vesselin K. Krastev, and Giacomo Falcucci. "Evaluation of a Scale-Resolving Methodology for the Multidimensional Simulation of GDI Sprays." Energies 12, no. 14 (2019): 2699. http://dx.doi.org/10.3390/en12142699.

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The introduction of new emissions tests in real driving conditions (Real Driving Emissions—RDE) as well as of improved harmonized laboratory tests (World Harmonised Light Vehicle Test Procedure—WLTP) is going to dramatically cut down NOx and particulate matter emissions for new car models that are intended to be fully Euro 6d compliant from 2020 onwards. Due to the technical challenges related to exhaust gases’ aftertreatment in small-size diesel engines, the current powertrain development trend for light passenger cars is shifted towards the application of different degrees of electrification

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Naveenkumar, Majety. "Novel Design of Reversible MUX and DEMUX using GDI Techinque." International Journal of Advances in Applied Sciences 4, no. 3 (2015): 103. http://dx.doi.org/10.11591/ijaas.v4.i3.pp103-108.

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Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type

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Dr.Tammisetti, Ashok, Dileepkumar Kunchala, Suresh Kumar Kornipati, Amareswari Pradyumna Mediga, Praveen Kumar Mallikeswarapu, and Avinash Kuvvarapu. "Design and analysis of GDI based kogge stone adder for low power applications." International Journal for Modern Trends in Science and Technology 11, no. 04 (2025): 131–37. https://doi.org/10.5281/zenodo.15121134.

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In modern VLSI design, the demand for highspeed and energy-efficient arithmetic circuits isever-growing, particularly in low-power computing applications. The KoggeStone Adder(KSA) is widely recognized for its parallel-prefix architecture, offering reduced delaycompared to conventional adders. However, traditional KSA implementations suffer fromhigh power consumption and increased transistor count. To address this, we propose aGDI-based Kogge-Stone Adder, leveraging the Gate Diffusion Input (GDI) technique tooptimize power efficiency while maintaining computational accuracy. The proposed desig

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Sharma, Satish, Shyam Babu Singh, and Shyam Akashe. "A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies." International Journal of Computer Applications 73, no. 14 (2013): 8–14. http://dx.doi.org/10.5120/12807-9900.

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Ramya . S, Sri Phani, and Nimmy Maria Jose. "A Low Power Binary to Excess-1 Code Converter Using GDI Technique." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 01 (2015): 209–14. http://dx.doi.org/10.15662/ijareeie.2015.0401031.

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kaur, Simran, Balwinder Singh, and Jain D.K. "Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique." International Journal of VLSI Design & Communication Systems 6, no. 5 (2015): 45–56. http://dx.doi.org/10.5121/vlsic.2015.6504.

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Ganesh, Racha, K. Lal Kishore, and P. Srinivasa Rao. "Performance Analysis of Hybrid Comparator using 45nm Technology." CVR Journal of Science and Technology 25, no. 1 (2024): 15–23. http://dx.doi.org/10.32377/cvrjst2503.

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In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor leve

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