Relevant bibliographies by topics / GDSII

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'GDSII'

Author: Grafiati
Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "GDSII"

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Obert, James, and Tom J. Mannos. "ASIC STA Path Verification Using Semi-Supervised Learning." International Journal of Semantic Computing 13, no. 02 (2019): 229–44. http://dx.doi.org/10.1142/s1793351x19400105.

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To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) format are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-supervised learning techniques are powerful tools in characterizing variations within STA path data and have much potential for identifying anomalies in ASIC RTL and GDSII design data.
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Kulkarni, Rakshan. "Hardware Accelerated AES: RTL to GDS." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 06 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem35738.

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This paper presents a hardware-accelerated Advanced Encryption Standard (AES) implementation featuring an 11-stage pipelined architecture and an optimized subkey generation scheme for enhanced performance. This design is implemented in Verilog and verified through waveform analysis. Operating at a maximum clock frequency of 100 MHz, our implementation achieves significant efficiency. The final design occupies an area of 1.44 mm2 and consists of 32,424 standard cells, with a power consumption of 32 mW at the typical corner. Furthermore, the entire design flow, from synthesis to layout (GDSII), is achieved using OpenLane, an open-source Electronic Design Automation (EDA) tool. This democratization of hardware design empowers a wider range of participants, particularly students and researchers, to efficiently implement their designs and gain hands-on experience without the constraints of expensive commercial tools. This fosters innovation and accelerates progress by allowing a broader community to contribute to technological advancements. Index Terms—OpenLane, Open-source , EDA, Pipelined AES, RTL to GDSII
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NAKURA, Toru, Tetsuya IIZUKA, and Kunihiro ASADA. "A PLL Compiler from Specification to GDSII." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A, no. 12 (2017): 2741–49. http://dx.doi.org/10.1587/transfun.e100.a.2741.

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Mohsin, Syed, Rahul J. Gowda, Asha CN, and Sumalatha S. "Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder." Journal of Electrical Engineering and Electronics Design 1, no. 1 (2023): 5–9. http://dx.doi.org/10.48001/joeeed.2023.115-9.

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In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.
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Mushtaq, Ahmed, V. Kiran, and Nandy Subrata. "Debug Utility for Validation of OASIS Parser." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 5 (2020): 914–17. https://doi.org/10.35940/ijeat.E9912.069520.

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In EDA industry, GDSII format is the IC industry de facto standard for IC layout data exchange. The designs developed may require up to 1 Billion Byte (1TByte) of disk data. This huge amount of Big Data not only slows down the runtimes from design to physical verification but also increases the time to get a design to market. On the other hand, OASIS stream format which is replacement to GDSII is relatively new and is emerging in the industry. The OASIS stream format significantly reduces the data and thereby the tool is much likely to run faster. There hasn’t been significant development in enhancing the robustness of its usage due to lack of in-house test cases. This paper presents an approach to develop a debug utility for OASIS parser validation to increase its robustness. The debug utility is implemented using a Singleton design pattern. The utility essentially enables us to compare the data associated with both the stream formats and highlights the differences. The effective memory utilization of the proposed design is zero since all the structure are dynamically created and destroyed after its use. Iterative and unit testing were performed on the utility and the proposed design was tested with real time test cases to verify its robustness.
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Dharmavarapu, Raghu, Soon Hock Ng, Fatima Eftekhari, Saulius Juodkazis, and Shanti Bhattacharya. "MetaOptics: opensource software for designing metasurface optical element GDSII layouts." Optics Express 28, no. 3 (2020): 3505. http://dx.doi.org/10.1364/oe.384057.

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Md Nor, Mohammad Nuzaihan, Uda Hashim, Siti Fatimah Abdul Rahman, and Tijjani Adam. "Negative Pattern Scheme (NPS) Design for Nanowire Formation Using Scanning Electron Microscope Based Electron Beam Lithography Technique." Advanced Materials Research 832 (November 2013): 419–22. http://dx.doi.org/10.4028/www.scientific.net/amr.832.419.

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In this work, we report the used of Negative Pattern Scheme (NPS) by Electron Microscope Based Electron Beam Lithography (EBL) Technique in connection with scanning electron microscope (SEM) for creating extremely fine nanowires. These patterns have been designed using GDSII Editor and directly transferred on the sample coated with ma-N 2400 Series as the negative tone e-beam resist. The NPS designs having line width of approximately 100 nm are successfully fabricated at our lab. The profile of the nanowire can be precisely controlled by this technique. The optical characterization that is applied to check the nanowires structure using SEM and Atomic Force Microscopy (AFM).
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Ige, Afolabi, Linhao Yang, Hang Yang, Jennifer Hasler, and Cong Hao. "Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing." Journal of Low Power Electronics and Applications 13, no. 4 (2023): 58. http://dx.doi.org/10.3390/jlpea13040058.

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The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.
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Hill, D., and A. B. Kahng. "Guest editors' introduction: RTL to GDSII - from foilware to standard practice." IEEE Design & Test of Computers 21, no. 1 (2004): 9–12. http://dx.doi.org/10.1109/mdt.2004.1261845.

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B, Prof Manjula B., Agniva Ghosh, Gowtham S, Manoj K. S, and Pushkar D. "ASIC Design and Implementation of Automated Coffee and Tea Brewing System with FPGA Validation." International Journal for Research in Applied Science and Engineering Technology 12, no. 4 (2024): 3497–504. http://dx.doi.org/10.22214/ijraset.2024.60585.

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Abstract: This paper presents a pioneering approach to enhance the efficiency of automated coffee and tea brewing systems through the integration of an ASIC-GDSII and FPGA validation. Leveraging the power of 45nm CMOS Technology, the design achieves substantial reductions in area, power consumption, and delay. The Verilog HDL code undergoes meticulous verification using Cadence tools like Genus and Innovus, ensuring optimal design performance. Innovus validates timing constraints, ensuring adherence to acceptable delay parameters. The resulting compact design not only minimizes power consumption but also effectively addresses leakage issues. These comprehensive optimizations meet stringent performance, area, and power requirements, elevating the operational efficiency of automated brewing systems. Furthermore, the control algorithm is synthesized and implemented using Xilinx's ISE Design Suite, followed by validation on SPARTAN 6 FPGA, providing invaluable insights for future synthesis and implementation endeavors.
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Dissertations / Theses on the topic "GDSII"

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Nasso, Isabelle. "Complexes d'ions Lanthanide(III) dérivés de ligands à motifs polyaminocarboxylique : synthèse, propriétés luminescentes (EuIII, TbIII) et relaxométriques (GdIII." Toulouse 3, 2006. http://www.theses.fr/2006TOU30277.

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L'intérêt des complexes organiques de gadolinium(III) comme agents de contraste en Imagerie par Résonance Magnétique (IRM) n'est plus à démontrer. D'autre part, la longue durée de vie de luminescence de certains complexes de lanthanides (Eu(III) et Tb(III)) peut être exploitée dans de nombreux domaines (biologie, diagnostic médical, microscopie, imagerie de fluorescence). Dans ce contexte et en tenant compte des paramètres requis pour ces deux applications, nous avons conçu et synthétisé des ligands bivalents, c'est-à-dire des ligands dont le complexe de Gd(III) est actif en IRM et dont les complexes Eu(III) et Tb(III) sont luminescents. Ces ligands hepta ou octadentés présentent une structure acyclique ou macrocyclique et intégrant un chromophore dérivé de la pyridine. L'étude des propriétés de luminescence des complexes Eu3+ et Tb3+ révèle pour certains des rendements quantiques particulièrement élevés (jusqu'à 49%) et des durées de vie de luminescence supérieures à 0,56 ms. Les propriétés relaxométriques (relaxivité, temps d'échange de la molécule d'eau) de certains de nos complexes de gadolinium(III) sont comparables à celles du Gd-DTPA, le composé utilisé en clinique<br>The interest of Gd(III) organic complexes as contrast agents in Resonance Magnetic Imaging (MRI) has been prouved for a long time. Moreover, the long luminescence lifetime of some lanthanide complexes (Eu(III) and Tb(III)) can be used in many scopes (biology, medical diagnosis, microscopy, fluorescence imaging). In this context and taking into account the parameters required for these two fields, we designed and synthesised bimodal ligands, whose Gd(III) complex is MRI active and Eu(III) and Tb(III) complexes are luminescent. These hepta or nonadentate ligands have an acyclic or macrocyclic structure and integrate a pyridine derivative chromophore. The luminescent properties study of the Eu3+ and Tb3+ complexes showed for some of them very high quantum yields (upper than 49%) and luminescence lifetimes higher than 0. 56 ms. The relaxometric properties (relaxivity, water exchange rate) of some of our Gd(III) complexes are comparable to that of Gd-DTPA which is clinically used
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Chen, Hsiung-Kai, and 陳雄凱. "Post-Layout Redundant Via Insertion Considering GDSII File Sizes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/28407672930125127755.

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碩士<br>國立清華大學<br>資訊工程學系<br>95<br>When the manufacturing processes of integrated circuits shrink to deep submicron technologies, loss of yield caused by via defects becomes more significant. In order to improve via yield and reliability, redundant via insertion is highly recommend by foundries. In this thesis, we study the post-layout redundant via insertion problem while considering the resultant GDSII file size. We formulate this problem as a maximum weighted independent set (MWIS) problem, and present a heuristic to solve the MWIS problem. Moreover, since the cells described in the GDSII file format can be instantiated by reflecting and rotating, for efficiently identifying the directions where some redundant vias can be inserted simultaneously, we propose the idea of direction sequence to quickly query the relationship between the direction relative to an original single via in a structure and the direction relative to a corresponding flattened single via. Experimental results show that for almost all test cases, our algorithm can insert the maximum numbers of redundant vias while keeping the resultant GDSII file sizes to have small increases. On average the size of a resultant GDSII file generated by our algorithm is one fifth of the size of the GDSII file which is flattened.
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Book chapters on the topic "GDSII"

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Bartolf, Holger. "Nanoscale-Precise Coordinate System: Scalable, GDSII-Design." In Fluctuation Mechanisms in Superconductors. Springer Fachmedien Wiesbaden, 2015. http://dx.doi.org/10.1007/978-3-658-12246-1_4.

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Suthar, Het, Shubham Tomar, and Rutu Parekh. "RTL to GDSII: Fully Digital Indirect Time of Flight SoC." In Sustainable Technology and Advanced Computing in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4364-5_63.

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Srikanth, B., J. V. R. Ravindra, G. A. E. Satish Kumar, and Fahimuddin Shaik. "Implementation of Improved High Speed SHA-256 Algorithm from RTL to GDSII Using Verilog HDL." In Studies in Computational Intelligence. Springer International Publishing, 2024. http://dx.doi.org/10.1007/978-3-031-43009-1_1.

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Moujoud, Youssef, Hafida Bouloiz, and Maryam Gallab. "Green and Digital Supply Chain Innovation (GDSCI): a Systematic Mapping Study." In Sustainable Civil Infrastructures. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-70992-0_13.

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Pardasani, R. T., and P. Pardasani. "Magnetic properties of tetranuclear bimetallic (FeIII-GdIII)2 complex with 1,2-bis-(3-methoxysalicylidene)aminoethane." In Magnetic Properties of Paramagnetic Compounds, Magnetic Susceptibility Data, Volume 3. Springer Berlin Heidelberg, 2021. http://dx.doi.org/10.1007/978-3-662-62470-8_390.

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"RTL to GDSII, or Synthesis, Place, and Route." In Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. CRC Press, 2016. http://dx.doi.org/10.1201/b19714-2.

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"Layout of Microfluidic Chips." In Microfluidics and Lab-on-a-Chip. The Royal Society of Chemistry, 2020. http://dx.doi.org/10.1039/9781782628330-00044.

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This chapter introduces the layout design tools for microfluidic devices and presents a new script-based method to generate complex layouts of microfluidic devices using Nanolithography Toolbox (NT) software. Compared with other computer-aided design or integrated circuits-based software, NT software is based on an extensive set of parameterized blocks and features, formulated into a simple text file, which is converted into a GDSII format to fabricate lithography masks. The utilization of NT software for structures such as capillary electrophoresis chips, microfluidic emulsion generator array chips using centrifugal forces, chambers, splitters and mixers, etc., is demonstrated. This NT software is a powerful yet easy-to-use tool to generate the layout of microfluidic devices.
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Kumar, Veena Sanath, Abhishek L S, Chandu H M, Chirag A, and Rohan S. "Design of Low Power Configurable Multiclock Digital System from RTL to GDSII." In Innovative Solutions: A Systematic Approach Towards Sustainable Future, Edition 1. BP International, 2025. https://doi.org/10.9734/bpi/mono/978-93-49238-47-3/ch18.

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Conference papers on the topic "GDSII"

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Padhy, Satyanarayan, Lugalapu Mounika, Palavalasa Manikanta Varaprasad, and Yernagula Roshit. "Physical Design (RTL-GDSII) Implementation of State Transition Graph-Based Sequential Multiplier." In 2024 2nd International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES). IEEE, 2024. https://doi.org/10.1109/scopes64467.2024.10990534.

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Sharma, Lokesh, Piyush Kudiwal, and Gufran Ahmad. "Performance Analysis and RTL to GDSII Flow of Memory Registers Using Qflow Opensource EDA Design Suit." In 2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT). IEEE, 2024. http://dx.doi.org/10.1109/icccnt61001.2024.10724919.

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Reich, Alfred J., Robert E. Boone, Warren D. Grobman, and Clyde Browning. "GDSII considered harmful." In Photomask 2001, edited by Giang T. Dao and Brian J. Grenon. SPIE, 2002. http://dx.doi.org/10.1117/12.458289.

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Pereira, Mark, and Barsha Baruah. "A novel GDSII compression technique." In Photomask Technology 2005, edited by J. Tracy Weed and Patrick M. Martin. SPIE, 2005. http://dx.doi.org/10.1117/12.632068.

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Wang Xing-yu and Zhao Ying-ding. "Design of GDSII pattern conversion system." In 2010 2nd International Conference on Information Science and Engineering (ICISE). IEEE, 2010. http://dx.doi.org/10.1109/icise.2010.5690218.

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Reich, Alfred J., Kent H. Nakagawa, and Robert E. Boone. "OASIS vs. GDSII stream format efficiency." In Photomask Technology, edited by Kurt R. Kimmel and Wolfgang Staud. SPIE, 2003. http://dx.doi.org/10.1117/12.518271.

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Liu, Pao-Lo. "Design mask patterns of photonic devices using a personal computer." In OSA Annual Meeting. Optica Publishing Group, 1989. http://dx.doi.org/10.1364/oam.1989.thy3.

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We have developed programs which run on personal computers such as IBM PC. Using these programs along with a computer aided design (CAD) program such as, Autocad, one can completely design and layout mask patterns of photonic devices on a personal computer. Two additional features are needed to make a CAD program useful for designing mask patterns. One is the handling of shapes with arbitrary angle such as a waveguide bend. We have pattern fracturing programs which can break up any shape into rectangles. The output of the fracturing program is a script file. Autocad can read in the script file and compose the shape. The other feature needed is the conversion between the Autocad database and the mask description format, Calma GDSII. We have written a set of utility programs to convert an Autocad database in the DXF format to the Calma GDSII format. We can also backconvert from the GDSII to the script files. This procedure can be used to verify that the conversion process is error-free. The entire procedure is automated by running programs in the batch mode. We have designed waveguide devices consisting of Y- branch, S-shaped bend, directional coupler, etc., and electrode patterns. By using different magnification factors for the x and y axes, all details of a waveguide device can be viewed on the graphics screen.
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Cobb, Nicolas B., and Emile Y. Sahouria. "Hierarchical GDSII-based fracturing and job deck system." In Photomask 2001, edited by Giang T. Dao and Brian J. Grenon. SPIE, 2002. http://dx.doi.org/10.1117/12.458356.

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Ravish Aradhya, H. V., Gopal Kanase, and Vinayakgouda Y. "RTL to GDSII of Harvard Structure RISC Processor." In 2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2021. http://dx.doi.org/10.1109/conecct52877.2021.9622735.

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Singla, Aayush, Bernhard Lippmann, and Helmut Graeb. "Verification of Physical Chip Layouts Using GDSII Design Data." In 2019 IEEE 4th International Verification and Security Workshop (IVSW). IEEE, 2019. http://dx.doi.org/10.1109/ivsw.2019.8854432.

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