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Journal articles on the topic 'Gem5'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Qureshi, Yasir Mahmood, William Andrew Simon, Marina Zapater, Katzalin Olcoz, and David Atienza. "Gem5-X." ACM Transactions on Architecture and Code Optimization 18, no. 4 (2021): 1–27. http://dx.doi.org/10.1145/3461662.

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The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this article, we present gem5-X, a system-level simulation framework, based on gem-5, for architectural exploration of heterogeneous many-core systems. To demonstrate the capabilities of gem5-X, real-time video analytics is used as a case-study. It is composed of two kernels, namely, video encoding and image classification using convolutional neural netw

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2

Nikounia, Seyed Hossein, and Siamak Mohammadi. "Gem5v: a modified gem5 for simulating virtualized systems." Journal of Supercomputing 71, no. 4 (2015): 1484–504. http://dx.doi.org/10.1007/s11227-014-1375-7.

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3

Chen, Xianmin, and Niraj K. Jha. "gem5-PVT." ACM Journal on Emerging Technologies in Computing Systems 12, no. 3 (2015): 1–19. http://dx.doi.org/10.1145/2755564.

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Binkert, Nathan, Bradford Beckmann, Gabriel Black, et al. "The gem5 simulator." ACM SIGARCH Computer Architecture News 39, no. 2 (2011): 1–7. http://dx.doi.org/10.1145/2024716.2024718.

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Yassin, Yahya H., Magnus Jahre, Per Gunnar Kjeldsberg, Snorre Aunet, and Francky Catthoor. "Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode." Journal of Signal Processing Systems 93, no. 1 (2020): 33–48. http://dx.doi.org/10.1007/s11265-020-01544-z.

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AbstractStringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions

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Power, Jason, Joel Hestness, Marc S. Orr, Mark D. Hill, and David A. Wood. "gem5-gpu: A Heterogeneous CPU-GPU Simulator." IEEE Computer Architecture Letters 14, no. 1 (2015): 34–36. http://dx.doi.org/10.1109/lca.2014.2299539.

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Rogers, Samuel, Joshua Slycord, Ronak Raheja, and Hamed Tabkhi. "Scalable LLVM-Based Accelerator Modeling in gem5." IEEE Computer Architecture Letters 18, no. 1 (2019): 18–21. http://dx.doi.org/10.1109/lca.2019.2893932.

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8

Semakin, A. N. "GEM5: DEVELOPMENT OF COMPUTER SYSTEM MODELS WITH PURPOSE TO EVALUATE THE EFFICIENCY OF PARALLEL CODE." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 227 (May 2023): 49–56. http://dx.doi.org/10.14489/vkit.2023.05.pp.049-056.

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In this paper we consider the possibility of using the gem5 computer system simulator to determine such metrics of parallel program code as its acceleration and the average workload of cpu cores on computer systems with shared memory. The working process in gem5 consists of three stages: building a model of a computer system, loading a software environment into the built model and executing a user program within this environment. The considered approach is used to evaluate the efficiency of a parallel program for modeling the transport of pollutants in the atmosphere. The program assumes both

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Dave, Hetal, and Nirali Kotak. "An analysis of cache configuration’s impacts on the miss rate of big data applications using gem5." Serbian Journal of Electrical Engineering 21, no. 2 (2024): 217–34. http://dx.doi.org/10.2298/sjee2402217d.

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This work aims to analyze the impacts of cache configurations on miss rates of big data benchmarks with varying level 1 instruction (L1I) and data (L1D) caches using the gem5 simulator. The cache miss rate of nine big data applications from four benchmark suits is analyzed with different cache configurations, such as increasing the cache size, varying the associativity, and altering the line size. The gem5 provides a versatile platform for conducting detailed experiments. The study sheds light on the relationship between cache and big data workloads, thus offering insights into optimizing cach

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P, Karunamurthy. "Integration of Gem5 And Dramsim2 For DDR4 Simulation." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 1 (2020): 698–793. http://dx.doi.org/10.30534/ijatcse/2020/99912020.

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11

Alian, Mohammad, Daehoon Kim, and Nam Sung Kim. "pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems." IEEE Computer Architecture Letters 15, no. 1 (2016): 41–44. http://dx.doi.org/10.1109/lca.2015.2438295.

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12

Rigotto, Pedro Corrêa, and Henrique Cota de Freitas. "Approach to Learning the gem5 Simulator for Beginning Researchers." Journal of Engineering Research 4, no. 2 (2024): 2–7. http://dx.doi.org/10.22533/at.ed.1317412415013.

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Županek, Bernarda, and Alenka Miškec. "Od prevoza do politike:." Keria: Studia Latina et Graeca 21, no. 2 (2020): 7–19. http://dx.doi.org/10.4312/keria.21.2.7-19.

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Novembra 2015 so pri arheoloških raziskavah ob prenovi Slovenske ceste na prostoru emonske insule XIII med drugim odkrili železen prstan z vdelano gemo. Na njej je upodobljena bojna galeja. Razločno so vidna vesla, krma, kljun in oven (rostrum). Na ladji oziroma nad njo sta upodobljena signa militaria, vojaška znaka centurij. Prstan glede na obliko datiramo v 1. stoletje, gemo pa glede na stil izvedbe postavljamo v 1.–2. stoletje. Gema je bila izdelana v različici kalcedona, imenovanega nikolo. Prstani z gemami so služili za pečatenje različnih dokumentov, motivi na njih pa so odražali okus in

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14

So, Hwisoo, Yohan Ko, Jinhyo Jung, Kyoungwoo Lee, and Aviral Shrivastava. "gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration." Electronics 12, no. 22 (2023): 4573. http://dx.doi.org/10.3390/electronics12224573.

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With aggressive technology scaling, soft errors have become a major threat in modern computing systems. Several techniques have been proposed in the literature and implemented in actual devices as countermeasures to this problem. However, their effectiveness in ensuring error-free computing cannot be ascertained without an accurate reliability estimation methodology. This can be achieved by using the vulnerability metric: the probability of system failure as a function of the time the program data are exposed to transient faults. In this work, we present a gemV-tool, a comprehensive toolset fo

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15

Nocua, Alejandro, Florent Bruguier, Gilles Sassatelli, and Abdoulaye Gamatié. "A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads." Microprocessors and Microsystems 67 (June 2019): 42–55. http://dx.doi.org/10.1016/j.micpro.2019.01.008.

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16

Semakin, Artem Nikolaevich. "Evaluation of the scalability property of the program for the simulation of atmospheric chemical transport by means of the simulator gem5." Computer Research and Modeling 12, no. 4 (2020): 773–94. http://dx.doi.org/10.20537/2076-7633-2020-12-4-773-794.

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17

Wang, Irene, Prasenjit Chakraborty, Zi Yu Xue, and Yen Fu Lin. "Evaluation of gem5 for performance modeling of ARM Cortex-R based embedded SoCs." Microprocessors and Microsystems 93 (September 2022): 104599. http://dx.doi.org/10.1016/j.micpro.2022.104599.

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18

Cebrian, Juan M., Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, and Mateo Valero. "Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86." Future Generation Computer Systems 112 (November 2020): 832–47. http://dx.doi.org/10.1016/j.future.2020.06.035.

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19

Gu, Chen. "A study on impacts of hardware changes on performance of different multithreading libraries based on Gem5." Journal of Physics: Conference Series 2646, no. 1 (2023): 012026. http://dx.doi.org/10.1088/1742-6596/2646/1/012026.

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Abstract This paper presents a thorough investigation into the performance of various multithreading libraries on different hardware configurations utilizing gem5. The study compares the performance of commonly-used multithreading libraries, including OpenMP, Pthread, TBB, and Dlib, through several benchmarks representing distinct types of workloads. Key hardware factors that directly affect the performance of each library are identified and analyzed. The research findings provide valuable insights and recommendations for selecting an appropriate multithreading library for a given application

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20

Zhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (2021): 176. http://dx.doi.org/10.3390/a14060176.

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Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the pr

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Bick, Konstantin, Duy Nguyen, Hyuk-Jae Lee, and Hyun Kim. "Fast and Accurate Memory Simulation by Integrating DRAMSim2 into McSimA+." Electronics 7, no. 8 (2018): 152. http://dx.doi.org/10.3390/electronics7080152.

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Computer architecture simulators play a crucial role in the verification of a new system’s design. However, a single simulator may not be sufficient in covering detailed modeling of the entire system, thereby lacking in the simulation of a specific functionality under investigation. In this case, combining two simulators is necessary to compensate for the drawbacks of a single simulator. This paper proposes the integration of DRAMSim2, a simulator that thoroughly models DDR-SDRAM main memory architecture, into the application-level+ simulator McSimA+. The challenges of achieving an efficient i

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Hendarin, Hendarin, Jan Everhard Riwurohi, and Setyo Arief Arachman. "The Role of Cache Memory In Enhancing Microprocessor Performance in PT. Srikandi Sinergi Sakti." Eduvest - Journal of Universal Studies 4, no. 12 (2024): 11824–29. https://doi.org/10.59188/eduvest.v4i12.43139.

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Cache memory in microprocessors has an important role in improving computer system performance by reducing data access time. This research aims to test the hypothesis that increasing the size and level of cache memory can significantly improve microprocessor performance. The research methodology involves a literature study on the concept of cache memory and experimental simulations using computer architecture simulators, such as Gem5, to model scenarios with varying cache sizes and levels. In these simulations, performance parameters such as memory access latency, throughput, and Instructions

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M L Sharma, Neelam Sharma, Sunil Kumar, et al. "Breaking bottlenecks: CPU optimization through architectural and neuromorphic techniques." World Journal of Advanced Research and Reviews 26, no. 2 (2025): 190–204. https://doi.org/10.30574/wjarr.2025.26.2.1463.

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This research explores two different approaches to improving how computers process information efficiently. The first part uses the Gem5 simulator to test and compare three types of CPU designs—Timing Simple CPU, Minor CPU, and O3CPU—by running a basic program. We looked at how features like pipelining, caching, and branch prediction affect how fast the program runs and how efficiently the CPU works. The second part focuses on recognizing handwritten digits from the MNIST dataset using two types of AI models. One model is a traditional neural network (MLP) that runs on a standard computer setu

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Zhao, Huatao, Xiao Luo, Chen Zhu, Takahiro Watanabe, and Tianbo Zhu. "Behavior-aware cache hierarchy optimization for low-power multi-core embedded systems." Modern Physics Letters B 31, no. 19-21 (2017): 1740067. http://dx.doi.org/10.1142/s021798491740067x.

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In modern embedded systems, the increasing number of cores requires efficient cache hierarchies to ensure data throughput, but such cache hierarchies are restricted by their tumid size and interference accesses which leads to both performance degradation and wasted energy. In this paper, we firstly propose a behavior-aware cache hierarchy (BACH) which can optimally allocate the multi-level cache resources to many cores and highly improved the efficiency of cache hierarchy, resulting in low energy consumption. The BACH takes full advantage of the explored application behaviors and runtime cache

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Vasconcelos, Leonardo B. A., Max V. Machado, and Henrique C. Freitas. "Ambiente para Estudo de Computação Paralela Baseado no Simulador Completo GEM5 e em Algoritmos de Ordenação Escritos com OpenMP." International Journal of Computer Architecture Education 3, no. 1 (2014): 1–4. https://doi.org/10.5753/ijcae.2014.4932.

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Com o surgimento e disseminação de arquiteturas paralelas para computadores pessoais (e.g. processadores multi-core), a discussão sobre o ensino de programação paralela ganhou força e importância para uma melhor formação dos egressos em cursos de computação. Nesse contexto, em disciplinas de Arquitetura de Computadores, há também a necessidade de correlacionar programação e arquiteturas paralelas. Dessa forma, é possível explicar com mais clareza os impactos decorrentes de decisões de programação e escolhas arquiteturais no desempenho final de um sistema computacional. O principal problema é e

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Priya, Bhukya Krishna, and N. Ramasubramanian. "Enhancing the Lifetime of a Phase Change Memory with Bit-Flip Reversal." Journal of Circuits, Systems and Computers 29, no. 14 (2020): 2050219. http://dx.doi.org/10.1142/s0218126620502199.

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Phase Change Memory (PCM) has evolved as a promising alternative over Dynamic Random Access Memory (DRAM) in terms of cell density and leakage power. While non-volatility is a desirable feature, it gives rise to the possibility of the data being present even after the power is switched off. To secure the data, encryption is normally done by using the standard Advanced Encryption Standard (AES) algorithm. Encrypting the data results in huge number of bit-flips, which reduces the lifetime of a PCM. The proposed method increases the lifetime of PCM by reducing the number of bit-flips occurred due

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Rumelili Köksal, Cagla Irmak, and Sıddıka Berna Örs Yalçın. "Efficient Modeling and Usage of Scratchpad Memory for Artificial Intelligence Accelerators." Electronics 14, no. 5 (2025): 1032. https://doi.org/10.3390/electronics14051032.

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Deep learning accelerators play a crucial role in enhancing computation-intensive AI applications. Optimizing system resources—such as shared caches, on-chip SRAM, and data movement mechanisms—is essential for achieving peak performance and energy efficiency. This paper explores the trade-off between last-level cache (LLC) and scratchpad memory (SPM) usage in accelerator-based SoCs. To evaluate this trade-off, we introduce a high-speed simulator for estimating the timing performance of complex SoCs and demonstrate the benefits of SPM utilization. Our work shows that dynamic reconfiguration of

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Kim, Haechan, Jinmoo Heo, Seongjoo Lee, and Yunho Jung. "SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging." Applied Sciences 14, no. 17 (2024): 7601. http://dx.doi.org/10.3390/app14177601.

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The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing m

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Zhuang, Yuzhi, Ming Zhang, and Binghao Wang. "A Generalized Optimization Scheme for Memory-Side Prefetching to Enhance System Performance." Electronics 14, no. 14 (2025): 2811. https://doi.org/10.3390/electronics14142811.

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In modern multi-core processors, memory request latency critically constrains overall performance. Prefetching, a promising technique, mitigates memory access latency by pre-loading data into faster cache structures. However, existing core-side prefetchers lack visibility to the DRAM state and may issue suboptimal requests, while conventional memory-side prefetchers often default to simple next-line policies that miss complex access patterns. We propose a comprehensive memory-side prefetch optimization scheme, which includes a prefetcher that utilizes advanced prefetching algorithms and an opt

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30

Thomas, Pat. "Mining for Gems: The Making of Readers and Writers." Voices from the Middle 8, no. 2 (2000): 26–33. http://dx.doi.org/10.58680/vm20002323.

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Considers how to develop students’ passion for language and how to get them to stop and look at word choice. Defines a “gem” as a word, phrase, or sentence that is particularly remarkable or moving. Describes working with students to notice the gems, design gem journals, write their own gems, and to create future gems.

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Hou, Yumin, Hu He, Xu Yang, et al. "FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW." VLSI Design 2016 (December 15, 2016): 1–12. http://dx.doi.org/10.1155/2016/8787919.

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This paper proposes FuMicro, a fused microarchitecture integrating both in-order superscalar and Very Long Instruction Word (VLIW) in a single core. A processor with FuMicro microarchitecture can work under alternative in-order superscalar and VLIW mode, using the same pipeline and the same Instruction Set Architecture (ISA). Small modification to the compiler is made to expand the register file in VLIW mode. The decision of mode switch is made by software, and this does not need extra hardware. VLIW code can be exploited in the form of library function and the users will be exposed under only

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Mohammed, Jwan, and Diary R. Sulaiman. "Performance analysis of multicore processors using multi-scaling techniques." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 3079. http://dx.doi.org/10.11591/ijece.v13i3.pp3079-3087.

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Integrating more cores per chip enables more programs to run simultaneously, and more easily switch from one program to another, and the system performance will be improved significantly. However, this current trend of central processing unit (CPU) performance cannot be maintained since the budget of power per chip has not risen while the consumption of power per core has slowly reduced. Generally, the processor’s maximum performance is proportional to the product of the number of their cores and the frequency they are running at. However, this is usually limited by constraints of power. In th

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33

Srivastava, Smriti, Minal Moharir, and Shivaneetha Gunisetty. "Performance analysis of congestion-aware Q-routing algorithm for network on chip." IAES International Journal of Artificial Intelligence (IJ-AI) 13, no. 1 (2024): 798. http://dx.doi.org/10.11591/ijai.v13.i1.pp798-806.

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<p>A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcement-based congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lb

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Srivastava, Smriti, Minal Moharir, and Shivaneetha Gunisetty. "Performance analysis of congestion-aware Q-routing algorithm for network on chip." IAES International Journal of Artificial Intelligence (IJ-AI) 13, no. 1 (2024): 798–806. https://doi.org/10.11591/ijai.v13.i1.pp798-806.

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A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcementbased congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lbm, l

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35

Seremak, Juliette R., Sunilkanth Bonigala, Kunj B. Gupta, Siva S. Panda, and Bal L. Lokeshwar. "Abstract 1678: Overcoming treatment resistance in advanced bladder cancers using a neo-adjuvant combination with a natural product analog." Cancer Research 83, no. 7_Supplement (2023): 1678. http://dx.doi.org/10.1158/1538-7445.am2023-1678.

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Abstract Urinary bladder cancer (BC) is a common cancer worldwide, with approximately 573,278 new cases and 212,536 deaths arising annually. Tumors detected beyond the transitional zone of the bladder (advanced BC) account for most deaths. In advanced BC, tumor heterogeneity and resistance to successive chemotherapy regimens are major contributors to morbidity and mortality. Toxicity associated with the combination of Gemcitabine and Cisplatin (G+C) treatment limits the efficacy of chemotherapy. We tested the potential antitumor activity of a novel combination therapy involving a semisynthetic

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36

Bi, Xinyu, Yanfeng Liu, Jianghua Li, Guocheng Du, Xueqin Lv, and Long Liu. "Construction of Multiscale Genome-Scale Metabolic Models: Frameworks and Challenges." Biomolecules 12, no. 5 (2022): 721. http://dx.doi.org/10.3390/biom12050721.

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Genome-scale metabolic models (GEMs) are effective tools for metabolic engineering and have been widely used to guide cell metabolic regulation. However, the single gene–protein-reaction data type in GEMs limits the understanding of biological complexity. As a result, multiscale models that add constraints or integrate omics data based on GEMs have been developed to more accurately predict phenotype from genotype. This review summarized the recent advances in the development of multiscale GEMs, including multiconstraint, multiomic, and whole-cell models, and outlined machine learning applicati

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Dzwiza, Kirsten. "Rekonstruktion des Ursprungs und Neudatierung zweier magischer Gemmen mit Hilfe einer Zauberzeichensequenz." Zeitschrift für Ägyptische Sprache und Altertumskunde 147, no. 2 (2020): 153–63. http://dx.doi.org/10.1515/zaes-2020-0033.

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SummaryThere are only a few sequences of ancient magic signs known to us today that have been preserved on multiple artefacts. A previously unnoticed sequence of 17 signs on a gem in the Museum of Fine Arts in Vienna occurs with minor but significant variations on two other gems in the State Museum of Egyptian Art in Munich. The Viennese gem is dated to the 16th century and is documented as a drawing in a 17th century publication. The first Munich gem has been assigned to the Graeco-Roman period. The second gem, which, according to the inventory card of the museum, also belongs to the Graeco-R

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Yang, Xu, Yumin Hou, and Hu He. "A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications." Sensors 19, no. 1 (2019): 140. http://dx.doi.org/10.3390/s19010140.

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The widespread applications of the wireless Internet of Things (IoT) is one of the leading factors in the emerging of Big Data. Huge amounts of data need to be transferred and processed. The bandwidth and latency of data transfers have posed a new challenge for traditional computing systems. Under Big Data application scenarios, the movement of large scales of data would influence performance, power efficiency, and reliability, which are the three fundamental attributes of a computing system. Thus, changes in the computing paradigm are demanding. Processing-in- Memory (PIM), aiming at placing

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Jwan, Mohammed, and R. Sulaiman Diary. "Performance analysis of multicore processors using multi-scaling techniques." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 3079–87. https://doi.org/10.11591/ijece.v13i3.pp3079-3087.

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Integrating more cores per chip enables more programs to run simultaneously, and more easily switch from one program to another, and the system performance will be improved significantly. However, this current trend of central processing unit (CPU) performance cannot be maintained since the budget of power per chip has not risen while the consumption of power per core has slowly reduced. Generally, the processor’s maximum performance is proportional to the product of the number of their cores and the frequency they are running at. However, this is usually limited by constraints of power.

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40

Li Peng-Fei, Zhang Yan-Ge, Lei Xue-Ling, and Pan Bi-Cai. "Stable structures of Ge65, Ge70, Ge75 and their electronic properties." Acta Physica Sinica 62, no. 14 (2013): 143602. http://dx.doi.org/10.7498/aps.62.143602.

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Zhao, Jing, Zixuan Li, Changzhong Li, et al. "Regulation of GeCu/Zn-SOD, GeMn-SOD, GeHsp90, and GeMT in Gymnocypris eckloni in Response to Copper and Lead Ion Challenges." Journal of Applied Ichthyology 2024 (March 7, 2024): 1–13. http://dx.doi.org/10.1155/2024/5716920.

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The contamination of aquatic environments by heavy metals can have detrimental effects on fish, impacting their growth and overall health, including the regulation of antioxidant genes. An investigation was carried out to assess the distribution and habitat of Gymnocypris eckloni in the Yellow River basin. Simultaneously, heavy metal concentrations in its habitat and in selected locations within the upper Yellow River were measured. In an effort to explore the potential roles of specific genes in antioxidant responses, G. eckloni was exposed to low concentrations of copper (Cu2+) and lead (Pb2

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CONLAN, MICHAEL, and BRUCE JAMIESON. "Naturally triggered persistent deep slab avalanches in western Canada Part II: weather trends from model forecasts." Journal of Glaciology 62, no. 232 (2016): 256–69. http://dx.doi.org/10.1017/jog.2016.2.

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ABSTRACTFor 175 difficult-to-forecast persistent deep slab avalanches, weather data were obtained from Global Environmental Multiscale (GEM) models produced by Environment Canada. The focus was to determine critical parameters and thresholds for avalanche forecasting from GEM and compare them with weather station data analyzed in Part I (Conlan and Jamieson, this issue). The high-resolution GEM-limited-area model (2.5 km resolution) forecasted higher median precipitation amounts than both the lower-resolution GEM15 (15 km resolution) and weather stations within a small dataset. Air temperature

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Radenković, Uroš, Marko Mićović, and Zaharije Radivojević. "Evaluation and Benefit of Imprecise Value Prediction for Certain Types of Instructions." Electronics 12, no. 17 (2023): 3568. http://dx.doi.org/10.3390/electronics12173568.

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Based on branch prediction, value prediction has emerged as a solution for problems caused by true data dependencies in pipelined processors. While branch predictors have binary outcomes (taken/not taken), value predictors face a challenging task as their outcomes can take any value. Because of that, coverage is reduced to enhance high accuracy and minimise costly recovery from misprediction. This paper evaluates value prediction, focusing on instruction execution with imprecisely predicted operands whose result can still be correct. Two analytical models are introduced to represent instructio

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Jiang, Jiechen, Weichun Jiang, Yang Jiao, et al. "Simulation studies of charging-up effect for single GEMs." Journal of Instrumentation 19, no. 10 (2024): T10008. http://dx.doi.org/10.1088/1748-0221/19/10/t10008.

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Abstract Many experiments revealed a charging-up effect inside the Gas Electron Multipliers (GEMs) holes, resulting in variation of GEM effective gain. Charge accumulation on the insulator surface inside the GEM hole (charge process) is involved in the present simulation models. With only the charge process in the simulation, a longer and larger gain stability of GEM was observed while comparing the charging-up curves to references, even distinct in the relatively high conductivity of GEM insulator. This observation indicates that charge transportation within the GEM insulator (discharge proce

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Hermann, T. W., W. Yen, P. Tooker, S. Ng, A. Negro-Vilar, and W. W. Lamph. "Bexarotene prevents and reverses gemcitabine resistance in non-small-cell lung cancer cells by affecting gene amplification." Journal of Clinical Oncology 24, no. 18_suppl (2006): 2057. http://dx.doi.org/10.1200/jco.2006.24.18_suppl.2057.

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2057 Background: Bexarotene (BEX) is a retinoid X receptor selective drug approved for treatment of CTCL and has activity in various cancers. Here we evaluate its effect on acquired drug resistance towards gemcitabine (GEM) in Calu3 NSCLC models. Methods: Parental or GEM-resistant Calu3 NSCLC cells were treated with BEX and GEM as single agents or in combination. Over the treatment course the cells were evaluated for molecular changes (RNA expression and DNA amplification), which were associated with resistance status. Results: Calu3 cells treated with repeated cycles of GEM alone gradually de

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LINS, SÓSTENES, and MICHELE MULAZZANI. "BLOBS AND FLIPS ON GEMS." Journal of Knot Theory and Its Ramifications 15, no. 08 (2006): 1001–35. http://dx.doi.org/10.1142/s0218216506004907.

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In this paper we prove that two n-gems induce the same manifold if and only if they are linked by a finite sequence of gem moves. A gem move is either a blob move, consisting in the creation or cancellation of an n-dipole, or a clean flip, which is a switch of a pair of edges of the same color that thickens an h-dipole, 1 ≤ h ≤ n - 1, or the inverse operation, which slims an h-dipole, 2 ≤ h ≤ n. Moreover we prove that we can reorder the gem moves, so that all the blob creations precede all clean flips which then precede all the blob cancellations. This reordering is of interest because it is a

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Avani, Dave, and Dave Krunal. "Safety-Eye: On Road Safety for Self-driving Vehicles using Reinforcement Learning." European Journal of Advances in Engineering and Technology 11, no. 3 (2024): 131–35. https://doi.org/10.5281/zenodo.13325786.

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With technological advancements automotive industry is witnessing new era of transition to self-driving vehicle for everything. Self-driving cars for personal and commercial use are right across the corner to become full reality. Along with self-driving drone and robots for delivery of food and merchandise have become reality.  With these advancements the safety and security of the self-driving vehicles have emerged as major concern for current times. To this end, this work proposes SafeEye a reinforcement learning based policy aware and optimized approach with federated learning to provi

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Friman, Tomas, Benjamin M. Fontaine, Alexey Chernobrovkin, et al. "Abstract 5766: Fungal genomes in drug discovery: Application of CETSA to study the mechanism of action of brefeldin A." Cancer Research 84, no. 6_Supplement (2024): 5766. http://dx.doi.org/10.1158/1538-7445.am2024-5766.

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Abstract Fungal genomes encode a vast collection of chemical diversity that has evolved over millions of years to engage specific targets and modulate diverse biological processes. These Genetically Encoded small Molecules (GEMs) constitute a largely untapped source of potential therapeutics. Although fungal GEMs such as cyclosporine, lovastatin, and penicillin have revolutionized modern medicine, these GEMs were discovered serendipitously through bioactivity-guided fractionation of fungal extracts. LifeMine is redefining GEM discovery through the deployment of proprietary genomic search algor

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Ko, Yohan. "Characterizing System-Level Masking Effects against Soft Errors." Electronics 10, no. 18 (2021): 2286. http://dx.doi.org/10.3390/electronics10182286.

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From early design phases to final release, the reliability of modern embedded systems against soft errors should be carefully considered. Several schemes have been proposed to protect embedded systems against soft errors, but they are neither always functional nor robust, even with expensive overhead in terms of hardware area, performance, and power consumption. Thus, system designers need to estimate reliability quantitatively to apply appropriate protection techniques for resource-constrained embedded systems. Vulnerability modeling based on lifetime analysis is one of the most efficient way

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Fujiwara, T., C. Shimodan, P. A. Majewski, et al. "High-tolerance nickel metalized glass gas electron multiplier: development and performance evaluation." Journal of Instrumentation 18, no. 10 (2023): P10025. http://dx.doi.org/10.1088/1748-0221/18/10/p10025.

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Abstract Micro-patterned gas detectors (MPGDs) are an important type of gaseous detector that can amplify and detect a small amount of electric charge generated by the interaction between radiation and gas. These detectors have high gain and high spatial resolution, making them useful in various applications ranging from high energy physics to medical instrumentation. However, one of the most widely used MPGDs, Gaseous Electron Multipliers (GEMs), may often experiences electrical discharges due to excessive electric field in the small space, which reduces their durability. To address this issu

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