Relevant bibliographies by topics / Gigascale integration (GSI)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Gigascale integration (GSI)'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Gigascale integration (GSI)"

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Meindl, James D., and Jeffrey Davis. "Interconnect performance limits on gigascale integration (GSI)." Materials Chemistry and Physics 41, no. 3 (1995): 161–66. http://dx.doi.org/10.1016/0254-0584(95)01509-4.

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Joshi, A. J., and J. A. Davis. "Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 8 (2005): 899–910. http://dx.doi.org/10.1109/tvlsi.2005.853611.

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Davis, J. A., R. Venkatesan, A. Kaloyeros, et al. "Interconnect limits on gigascale integration (GSI) in the 21st century." Proceedings of the IEEE 89, no. 3 (2001): 305–24. http://dx.doi.org/10.1109/5.915376.

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Venkatesan, R., J. A. Davis, K. A. Bowman, and J. D. Meindl. "Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 6 (2001): 899–912. http://dx.doi.org/10.1109/92.974903.

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Naeemi, A., J. A. Davis, and J. D. Meindl. "Compact Physical Models for Multilevel Interconnect Crosstalk in Gigascale Integration (GSI)." IEEE Transactions on Electron Devices 51, no. 11 (2004): 1902–12. http://dx.doi.org/10.1109/ted.2004.837379.

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Naeemi, A., R. Sarvari, and J. D. Meindl. "Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)." IEEE Electron Device Letters 26, no. 2 (2005): 84–86. http://dx.doi.org/10.1109/led.2004.841440.

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Davis, J. A., V. K. De, and J. D. Meindl. "A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation." IEEE Transactions on Electron Devices 45, no. 3 (1998): 580–89. http://dx.doi.org/10.1109/16.661219.

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Shakeri, K., and J. D. Meindl. "Compact Physical IR-Drop Models for Chip/Package Co-Design of Gigascale Integration (GSI)." IEEE Transactions on Electron Devices 52, no. 6 (2005): 1087–96. http://dx.doi.org/10.1109/ted.2005.848125.

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Murarka, S. P., J. Steigerwald, and R. J. Gutmann. "Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing." MRS Bulletin 18, no. 6 (1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.

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Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.
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Bakir, M. S., H. A. Reed, H. D. Thacker, et al. "Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)." IEEE Transactions on Electron Devices 50, no. 10 (2003): 2039–48. http://dx.doi.org/10.1109/ted.2003.816528.

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Dissertations / Theses on the topic "Gigascale integration (GSI)"

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Shakeri, Kaveh. "Power Distribution in Gigascale Integration (GSI)." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/10576.

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The main objective of this thesis is to develop models for the power distribution network of high performance gigascale chips. The two main concerns in distributing power in a chip are voltage drop and electromigration-induced reliability failures. The voltage drop on the power distribution network is due to IR-drop and simultaneous switching noise. IR-drop is the voltage drop due to current passing through the resistances of the power distribution network. Simultaneous switching noise is due to varying current passing through the inductances of the power distribution network. Compact physical models are derived for the IR-drop and electromigration for different types of packages. These chip-package co-design models enable designers in the early stages of the design to estimate the on-chip interconnect resources, and also to choose type and size of the package required for power distribution. Modeling of the simultaneous switching noise requires the simulation of a large circuit with thousands of inductances. The main obstacle challenging the simulation of a simultaneous switching noise circuit model is the computing resources required to solve the dense inductance matrix. In this work, a new relative inductance matrix is introduced to solve massively coupled RLC interconnects. It is proven that the analysis using this method is accurate for a wide frequency range and all configurations. Using the new inductance matrix makes the circuit simulations significantly faster without losing accuracy.
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Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.

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Joshi, Ajay Jayant. "Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI)." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10549.

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The main objective of this research is to develop a pervasive wire sharing technique that can be easily applied across the entire range of on-chip interconnects in a very large scale integration (VLSI) system. A wave-pipelined multiplexed (WPM) routing technique that can be applied both intra-macrocell and inter-macrocell interconnects is proposed in this thesis. It is shown that an extensive application of the WPM routing technique can provide significant advantages in terms of area, power and performance. In order to study the WPM routing technique, a hierarchical approach is adopted. A circuit-level, system-level and physical-level analysis is completed to explore the limits and opportunities to apply WPM routing to current VLSI and future gigascale integration (GSI) systems. Design, verification and optimization of the WPM circuit and measurement of its tolerance to external noise constitute the circuit-level analysis. The physical-level study involves designing wire sharing-aware placement algorithms to maximize the advantages of WPM routing. A system-level simulator that designs the entire multilevel interconnect network is developed to perform the system-level analysis. The effect of WPM routing on a full-custom interconnect network and a semi-custom interconnect network is studied.
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Tang, Xinghai. "Intrinsic and extrinsic parameter fluctuation limits on gigascale integration (GSI)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13305.

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Naeemi, Azad. "Analysis and optimization for global interconnects for gigascale integration (GSI)." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180121/unrestricted/naeemi%5Fazad%5F200312%5Fphd.pdf.

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Davis, Jeffrey Alan. "A hierarchy of interconnect limits and opportunities for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15803.

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Bowman, Keith Alan. "A circuit-level perspective of opportunities and limitations for Gigascale Integration (GSI)." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15007.

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Huang, Gang. "Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional (3-D) integration systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26619.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Meindl, James D.; Committee Member: Bakir, Muhannad S.; Committee Member: Davis, Jeffrey A.; Committee Member: Gaylord, Thomas K.; Committee Member: Kohl, Paul A.; Committee Member: Naeemi, Azad. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Book chapters on the topic "Gigascale integration (GSI)"

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Meindl, J. D., J. A. Davis, P. Zarkesh-Ha, C. Patel, K. P. Martin, and P. A. Kohl. "Interconnect Opportunities for Gigascale Integration (GSI)." In Interconnect Technology and Design for Gigascale Integration. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0461-0_1.

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Conference papers on the topic "Gigascale integration (GSI)"

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Meindl, James D. "Gigascale integration (GSI) technology." In the 1991 ACM/IEEE conference. ACM Press, 1991. http://dx.doi.org/10.1145/125826.126094.

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Meindl, J. D., V. K. De, and B. Agrawal. "Prospects of gigascale integration (GSI) beyond 2003." In 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers. IEEE, 1993. http://dx.doi.org/10.1109/isscc.1993.280057.

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Meindl, J. D. "21st Century Opportunities For Gigascale Integration (GSI)." In IWSM. 1998 3rd International Workshop on Statistical Metrology. IEEE, 1998. http://dx.doi.org/10.1109/iwstm.1998.729752.

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Meindl, J. D. "XXI century gigascale integration (GSI): the interconnect problem." In Proceedings 20th Anniversary Conference on Advanced Research in VLSI. IEEE, 1999. http://dx.doi.org/10.1109/arvlsi.1999.756039.

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Wu, Y.-M., T. K. Gaylord, E. N. Glytsis, and J. D. Meindl. "Sensitivity analysis of grating couplers in gigascale integration (GSI)." In Frontiers in Optics. OSA, 2003. http://dx.doi.org/10.1364/fio.2003.wi5.

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Zarkesh-Ha, P., and J. D. Meindl. "Optimum on-chip power distribution networks for gigascale integration (GSI)." In Proceedings of the IEEE 2001 International Interconnect Technology Conference. IEEE, 2001. http://dx.doi.org/10.1109/iitc.2001.930036.

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Joshi, Ajay, and Jeff Davis. "A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)." In the 2004 international workshop. ACM Press, 2004. http://dx.doi.org/10.1145/966747.966761.

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Davis, Jeff A., Raguraman Venkatesan, Keith Bowman, and James D. Meindl. "Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session)." In the 2000 international workshop. ACM Press, 2000. http://dx.doi.org/10.1145/333032.333045.

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Gang Huang, Azad Naeemi, Tingdong Zhou, et al. "Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)." In 2008 58th Electronic Components and Technology Conference (ECTC 2008). IEEE, 2008. http://dx.doi.org/10.1109/ectc.2008.4550040.

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