Dissertations / Theses on the topic 'Globally Asynchronous Locally Synchronous'

<p>This thesis is investigating the new globally asynchronous locally synchronous (GALS) technology for integrated circuits. Different types of asynchronous wrappers are tested and a new wrapper design is presented. It also investigates the possibility to use VHDL for asynchronous simulation and synthesis. The conclusions are that the GALS technology is possible to use but that it needs new synthesis tools, because todays tools are designed for synchronous technology.</p>

Globally-Asynchronous, Locally-Synchronous (GALS) design techniques employ the finer points of synchronous and asynchronous design methods to eliminate problems arising due to clock distribution, power dissipation, and large area over head. With the recent rise in the demand for System-on-a-Chip (SoC) designs, global clock distribution and power dissipation due to clock distribution are inevitable. In order to reduce/eliminate the effects of the global clock in synchronous designs and large area overhead in asynchronous designs, an alternative approach would be to utilize GALS design techniques. Not only do GALS designs eliminate the issue of using a global clock, they also have smaller area overhead when compared to purely asynchronous designs. Among the various GALS design approaches proposed till date, this thesis focuses on the working and implementation of Asynchronous Wrapper designs proposed by Muttersbach et al., in [1, 2]. This thesis specifically addresses different approaches to incorporate the wrappers in VLSI circuits, rather than discussing the efficiency and viability of GALS design techniques over purely synchronous or asynchronous approaches. It has been proven by researchers [3] that GALS design approaches bring down power consumption due to the elimination of the global clock by small amounts, but there is also a drop in performance. Since the goal of this thesis is to introduce the reader to GALS design techniques and not prove their efficiency, it is out of the scope of this thesis to validate the results shown in [3]. In our aim to introduce the reader to GALS design techniques, we first provide a comparison of synchronous and asynchronous design approaches, and then discuss the need for GALS design approaches. We will then address issues affecting GALS such as metastability, latency, flow control, and local clock alteration. After familiarizing the reader with the issues affecting GALS, we will then discuss various GALS design techniques proposed till date. We show the use of asynchronous FIFOs and asynchronous wrappers to realize GALS modules. Two wrapper design approaches are discussed: one being the asynchronous wrapper design proposed by Carlsson et al., in [4], and the other being the asynchronous wrapper design proposed in [1, 2]. An in-depth discussion and analysis of the wrapper design approach proposed in [1, 2] is provided based on the state transition graphs (STGs) that characterize the port-controller AFSMs. Various data transfer channel configurations that incorporate the wrapper port-controllers are designed and realized through VHDL codes, with their functioning verified through simulation results. Design examples showing the working of asynchronous wrappers to achieve point-to-point, synchronous-synchronous and synchronous-asynchronous data communication are provided. Finally, a design example to achieve multi-point data communication is realized. This example incorporates a previously proposed idea. We provide a modification to this idea by designing an arbiter that arbitrates between two separate requests coming into a multi-input port. Through the above design examples, the functionality and working of GALS asynchronous wrappers are verified, and recommendations for modifications are made to achieve flexible multi-point data communication.<br>M.S.E.E.<br>Department of Electrical and Computer Engineering<br>Engineering and Computer Science<br>Electrical Engineering

Thesis (Ph. D.)--University of Cincinnati, 2006.<br>Title from electronic thesis title page (viewed Apr. 20, 2007). Includes abstract. Keywords: FPGA Architecture, Globally Asynchronous Locally Synchronous. Includes bibliographical references.

The research reported in this dissertation is motivated by two trends in the system-on-chip (SoC) design industry. First, due to the incessant technology scaling, the interconnect delays are getting larger compared to gate delays, leading to multi-cycle delays in communication between functional blocks on the chip, which makes implementing a synchronous global clock difficult, and power consuming. As a result, globally asynchronous and locally synchronous (GALS) designs have been proposed for future SoCs. Second, due to time-to-market pressure, and productivity gain, intellectual property (IP) block reuse is a rising trend in SoC design industry. Predesigned IPs may already be optimized and verified for timing for certain clock frequency, and hence when used in an SoC, GALS offers a good solution that avoids reoptimizing or redesigning the existing IPs. A special case of GALS, known as Latency-Insensitive Protocol (LIP) lets designers adopt the well-understood and developed design flow of synchronous design while solving the multi-cycle latency at the interconnects. The communication fabrics for LIP are synchronous pipelines with hand shaking. However, handshake based protocol has complex control logics and the unnecessary handshake brings down the system's throughput. That is why scheduling based LIP was proposed to avoid the hand-shakes by pre-calculated clock gating sequences for each block. It is shown to have better throughput and easier to implement. Unfortunately, static scheduling only exists for bounded systems. Therefore, this type of design in literatures restrict their discussions to systems whose graphic representation has a single strongly connected component (SCC), which by the theory is bounded. This dissertation provides an optimization design flow for LIP synthesis with respect to back pressure, throughput and buffer sizes. This is based on extending the scheduled LIP with minimum modifications to render it general enough to be applicable to most systems, especially those with multiple SCCs. In order to guarantee the design correctness, a formal framework that can analyze concurrency and prevent fallacious behaviors such as overflow, deadlock etc., is required. Among many formal models of concurrency used previously in asynchronous system design, marked graphs, periodic clock calculus and polychrony are chosen for the purpose of modeling, analyzing and verifying in this work. Polychrony, originally developed for embedded software modeling and synthesis, is able to specify multi-rate interfaces. Then a synchronous composition can be analyzed to avoid incompatibly and combinational loops which causes incorrect GALS distribution. The marked graph model is a good candidate to represent the interconnection network which is quite suitable for modeling the communication and synchronizations in LIP. The periodic clock calculus is useful in analyzing clock gating sequences because periodic clock calculus easily captures data dependencies, throughput constraints as well as buffer sizes required for synchronization. These formal methods help establish a formally based design flow for creating a synchronous design and then transforming it into a GALS implementation either using LIP or in a more general GALS mechanisms.<br>Ph. D.

Dissertação apresentada na Faculdade de Ciências e Tecnologias da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores<br>The main goal is to develop a solution for the interconnection of components constituent of a GALS - Globally Asynchronous, Locally Synchronous – system. The components are implemented in parallel obtained as a result of the partition of a model expressed a Petri net (PN), performed using the PNs editor SNOOPY-IOPT in conjunction with the Split tool and the tools to automatically generate the VHDL code from the representations of the PNML models resulting from the partition (these tools were developed under the project FORDESIGN and are available at http://www.uninova.pt/FORDESIGN). Typical solutions will be analyzed to ensure proper communication between components of the GALS system, as well as characterized and developed an appropriate solution for the interconnection of the components associated with the PN sub-models. The final goal (not attained with this thesis) would be to acquire a tool that allows generation of code for the interconnection solution from the associated components, considering a specific application. The solution proposed for componentes interconnection was coded in VHDL and the implementation platforms used for testing include the Xilinx FPGA Spartan-3 and Virtex-II.

Advanced VLSI/ULSI technologies have made it possible to realise parallelism and pipelining processing principles at affordable cost. One of the consequences is that more and more algorithms are now directly implemented in hardware. The configurable hardware algorithm approach has the potential to combine the performance of hardware algorithms and the flexibility of software algorithms at the user level. On the other hand, system timing design problems become one of the determining factors on design complexity, correct system function and high performance. This timing problem plays an even more important role in configurable systems. There are two typical system timing control design approaches, the synchronous timing design and the asynchronous timing design. This thesis investigates and demonstrates the idea and feasibility of applying asynchronous timing control at the system level and synchronous timing control to system composition modules, namely a Globally Asynchronous Locally Synchronous (GALS) design approach, for very large scale configurable hardware algorithms. A systematic approach has been adopted in this thesis to develop a configurable GALS array architecture. With the analysis of general algorithmic properties, a novel multiple threads computation model consisting of an architecture with a pool of programmable hardware operators having configurable interconnections and a GALS system timing control structure is first established. The multiple threads computation model bridges algorithms and the architecture for efficient algorithm embeddings. The GALS timing control makes this threads model practical. A novel and fast event-driven GALS data transfer interface is developed upon which a bit-serial configurable GALS array system for algorithm embeddings is designed. Some good average performance results are obtained with a polynomial evaluation algorithm embedded as a frame buffer. The work on the GALS system timing design principle can be easily extended to the design of general GALS systems.

Un système GALS (Globalement Asynchrone, Localement Synchrone) est un ensemble de composants synchrones qui évoluent en même temps, chacun à propre rythme, et qui communiquent de manière asynchrone. Cette thèse propose un environnement formel de modélisation et de vérification dédié aux systèmes GALS, en se focalisant sur le comportement asynchrone.Notre environnement s’appuie sur un langage formel que nous avons conçu nommé GRL (GALS Représentation Language). GRL permet la spécification comportementale des composants synchrones, de la communication asynchrone, et des contraintes sur les rythmes des composants ainsi que sur les valeurs que prennent les entrées des composants. Pour analyser les spécifications GRL, nous utilisons CADP, une boîte à outils logicielle permettant la vérification de processus concurrents asynchrones par des techniques d'exploration d’espaces d’états. Dans ce but, nous avons défini une traduction de GRL vers LNT, un langage de spécification supporté par CADP. La traduction est implémentée dans un outil appelé GRL2LNT, permettant ainsi la génération automatique d’espaces d'états à partir de spécifications GRL.Pour permettre la vérification formelle des spécifications GRL, nous avons conçu un langage de propriétés nommé muGRL, qui est interprété sur les espaces d’états de GRL. Le langage muGRL est basé sur un ensemble de patrons qui capturent les propriétés des systèmes concurrents et des systèmes GALS, réduisant ainsi la complexité d'utiliser les logiques temporelles classiques. La sémantique de muGRL est définie par traduction vers MCL, le langage de logique temporelle fourni par CADP. Enfin, nous illustrons l’usage de GRL, muGRL et CADP pour la modélisation et la vérification d’applications GALS concrètes, comprenant des études de cas industrielles<br>A GALS (Globally Asynchronous, Locally Synchronous) system consists of several synchronouscomponents that evolve concurrently, each with its own pace, and communicatealtogether asynchronously. This thesis proposes a formal modelling and verificationframework dedicated to GALS systems, with a focus on the asynchronous behaviour.As a cornerstone of our framework, we have designed a formal language, named GRL(GALS Representation Language). GRL enables the behavioural specification of synchronouscomponents, asynchronous communication, and constraints involving bothcomponent paces and the data carried by component inputs. To analyse GRL specifications,we took advantage of the CADP software toolbox for the verification of asynchronousconcurrent processes, using state space exploration techniques. For this purpose,we defined a translation from GRL to the LNT specification language supportedby CADP. The translation was implemented by a tool named GRL2LNT, thus enablingstate spaces to be automatically derived from GRL specifications.To enable the formal verification of GRL specifications, we designed a property specificationlanguage, named muGRL, which is interpreted on GRL state spaces. The muGRLlanguage is based on a set of patterns capturing properties of concurrent and GALSsystems, which reduces the complexity of using full-fledged temporal logics. The semanticsof muGRL are defined by a translation into the MCL temporal logic supported byCADP. Finally, we illustrated how GRL, muGRL, and CADP can be applied to modeland verify concrete GALS applications, including industrial case-studies

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores<br>A model-based development approach (MBDA) for Globally-Asynchronous Locally- Synchronous (GALS) Distributed Embedded Systems (DESs) is proposed. This approach relies on the GALS-DESs specification through (low- or high-level) Petri net classes, which ensure that the created models are GALS, locally deterministic, distributable, networkindependent, and platform-independent and support their simulation, verification, and implementation (using simulation, model-checking, and code generation tools). The use of network- and platform-independent models enable the use of heterogeneous communication networks to support the distributed components interaction and enable the use of heterogeneous platforms to support the components and the communication nodes implementation. To enable the proposed MBDA, Petri nets are extended with a set of the concepts, most notably time-domains and asynchronous-channels. Algorithms to support the verification of GALS-DES models and their decomposition into implementable sub-models are also proposed. A tool chain framework (IOPT-tools) was extended with this work proposals, supporting their validation and the GALS-DESs development.<br>Fundação para a Ciência e a Tecnologia - grant ref. SFRH/BD/62171/2009

AADL is dedicated to high-level design and evaluation of embedded systems. It allows describing both system structure and functional aspects via a component-based approach, e. G. , GALS system. The polychronous model of computation stands out from other synchronous specification models by the fact that it allows one specifying a system whose components can have their own activation clocks. It is well adapted to support a GALS design methodology. Its framework Polychrony provides models and methods for modeling, transformation and validation of embedded systems. This thesis proposes a methodology for modeling and validation of embedded systems specified in AADL via the multi-clock synchronous programming language Signal. This methodology includes system-level modeling via AADL, automatic transformations from the high-level AADL model to the polychronous model, code distribution, formal verification and simulation of the obtained polychronous model. Our transformation takes into account both the system architecture, particularly described in Integrated Modular Avionics (IMA), and functional aspects, e. G. , software components implemented in the polychronous language Signal. AADL components are modeled into the polychronous MoC within the IMA architecture using a library of ARINC services. The AADL Behavior Annex is interpreted into the multi-clocked MoC using SSA as an intermediate formalism. Distributed code generation is obtained with Polychrony. Formal verification and simulation are carried out on two case studies that illustrate our methodology for the reliable design of AADL applications<br>AADL est dédié à la conception de haut niveau et l’évaluation de systèmes embarqués. Il permet de décrire la structure d’un système et ses aspects fonctionnels par une approche à base de composants. Des processus localement synchrones sont alloués sur une architecture distribuée et communiquent de manière globalement asynchrone (système GALS). Une spécificité du modèle polychrone est qu’il permet de spécifier un système dont les composants peuvent avoir leur propre horloge d’activation : il est bien adapté à une méthodologie de conception GALS. Dans ce cadre, l’atelier Polychrony fournit des modèles et des méthodes pour la modélisation, la transformation et la validation de systèmes embarqués. Cette thèse propose une méthodologie pour la modélisation et la validation de systèmes embarqués spécifiés en AADL via le langage synchrone multi-horloge Signal. Cette méthodologie comprend la modélisation de niveau système en AADL, des transformations automatiques du modèle AADL vers le modèle polychrone, la distribution de code, la vérification formelle et la simulation du modèle polychrone. Notre transformation prend en compte l’architecture du système, décrite dans un cadre IMA, et les aspects fonctionnels, les composants logiciels pouvant être mis en oeuvre en Signal. Les composants AADL sont modélisés dans le modèle polychrone en utilisant une bibliothèque de services ARINC. L’annexe comportementale d’AADL est interprétée dans ce modèle via SSA. La génération de code distribué est obtenue avec Polychrony. La vérification formelle et la simulation sont eectuées sur deux études de cas qui illustrent notre méthodologie pour la conception fiable des applications AADL

Aujourd'hui, il existe plusieurs façons de développer des circuits microélectroniques adaptés aux applications spatiales qui répondent aux contraintes sévères de l'immunité contre les radiations, que ce soit en termes de technique de conception ou de processus de fabrication. Le but de ce doctorat est d'une part de combiner plusieurs techniques nouvelles de microélectronique pour concevoir des architectures adaptées à ce type d'application et d'autre part, d'incorporer des composants magnétiques non-volatiles intrinsèquement robustes aux rayonnements. Un tel couplage serait tout à fait novateur et profiterait sans précédent, en termes de surface, de consommation, de robustesse et de coût.Contrairement à la conception de circuits synchrones qui reposent sur un signal d'horloge, les circuits asynchrones ont l'avantage d'être plus ou moins insensibles aux variations temporel résultant par exemple des variations du processus de fabrication. En outre, en évitant l'utilisation d'une horloge, les circuits asynchrones ont une consommation d'énergie relativement faible. Les circuits asynchrones sont généralement conçus pour fonctionner en fonction des événements déterminés grâce à un protocole de "poignée de main" spécifique.Pour les applications avioniques et spatiales, il serait souhaitable de fournir un circuit asynchrone rendu robuste contre les effets des radiations. En effet, la présence de particules ionisantes à haute altitude ou dans l'espace peut induire des courants perturbateurs dans des circuits intégrés qui peuvent être suffisants pour provoquer un basculement à l'état binaire maintenu par une ou plusieurs grilles. Cela peut provoquer un dysfonctionnement du circuit, connu dans l'état de l'art en tant que single event upset (SEU). Il a été proposé de fournir un module redondant double (Dual Modular Redundency: DMR) ou un module redondant triple (Tripple Modular Redundcy: TMR) dans une conception de circuit asynchrone afin de fournir une protection contre les radiations. De telles techniques s'appuient sur la duplication du circuit dans le cas de DMR, ou en triplant le circuit dans le cas de TMR, et en détectant une discordance entre les sorties des circuits comme indication de l'apparition d'une SEU.L'intégration de composants non-volatils intrinsèquement robustes, tels que les jonctions de tunnel magnétique (JTM), l'élément principal de la mémoire MRAM, pourrait conduire à de nouvelles façons de retenir les données dans des environnements difficiles. Les dispositifs JTM sont constitués de matériaux ferromagnétiques avec des propriétés magnétiques qui ne sont pas sensibles aux rayonnements. Les données sont stockées sous la forme de la direction de l'aimantation et non sous la forme d'une charge électrique, qui est une propriété essentielle pour les applications spatiales. Il est également largement reconnu dans le domaine de la microélectronique que les circuits intégrés fabriqués sur les substrats SOI (Silicon On Insulator) sont plus robustes aux radiations.Il existe donc un besoin dans l'état de l'art pour un circuit ayant une surface et une consommation d'énergie relativement faibles, et qui permet une récupération après un SEU sans nécessiter de réinitialisation et qui présente des caractéristiques non-volatiles. L'objectif de ce doctorat est de combiner tous les avantages mentionnés ci-dessus en regroupant plusieurs méthodes de conception microélectronique répondant aux contraintes des applications spatiales dans une nouvelle architecture. Un Circuit complet a été imaginé, conçu, simulé et envoyé en fabrication. Ce circuit est composé d'un pipeline asynchrone d'additionneur et d'un test intégré complexe connu sous le nom de BIST (Built In Self Test). Apres fabrication, ce circuit sera testé. Premièrement des tests fonctionnels vont être réalisés, puis des tests sous laser pulsé seront menés ainsi que sous attaques aux ions lourds<br>Today, there are several ways to develop microelectronic circuits adapted for space applications that meet the harsh constraints of immunity towards radiation, whether in terms of technical design or manufacturing process. The aim of this doctorate is on the one hand to combine several novel techniques of microelectronics to design architectures adapted to this type of application, and on the other hand to incorporate non-volatile magnetic components inherently robust to radiation. Such an assembly would be quite innovative and would benefit without precedent, in terms of surface, consumption, robustness and cost.In contrast with synchronous circuit designs that rely on a clock signal, asynchronous circuits have the advantage of being more or less insensitive to delay variations resulting for example from variations in the manufacturing process. Furthermore, by avoiding the use of a clock, asynchronous circuits have relatively low power consumption. Asynchronous circuits are generally designed to operate based on events determined using a specific handshake protocol.For aviation and/or spatial applications, it would be desirable to provide an asynchronous circuit that is rendered robust against the effects of radiation. Indeed, the presence of ionising particles at high altitudes or in space can induce currents in integrated circuits that may be enough to cause a flip in the binary state held by one or more gates. This may cause the circuit to malfunction, known in the art as a single event upset (SEU). It has been proposed to provide dual modular redundancy (DMR) or triple modular redundancy (TMR) in an asynchronous circuit design in order to provide radiation protection. Such techniques rely on duplicating the circuit in the case of DMR, or triplicating the circuit in the case of TMR, and detecting a discordance between the outputs of the circuits as an indication of the occurrence of an SEU.The integration of inherently robust non-volatile components, such as Magnetic Tunnel Junctions (MTJ), the main element of MRAM memory, could lead to new ways of data retention in harsh environments. MTJ devices are constituted of ferromagnetic materials with magnetic properties that are not sensitive to radiation. Data is stored in the form of the direction of the magnetisation and not in the form of an electric charge, which is an essential property for space applications. It is also widely recognised in the field of microelectronics that integrated circuits manufactured on SOI (Silicon On Insulator) substrates are more robust to radiation.There is thus a need in the art for a circuit having relatively low surface area and power consumption, and that allows recovery following an SEU without requiring a reset and that has non-volatile characteristics. The objective of this doctorate is to combine all the above mentioned benefits by regrouping several methods of microelectronic design responding to the constraints of space applications into a novel architecture. A complete circuit has been created, designed, simulated, validated and sent to manufacturing in a 28nm FD-SOI process. This circuit is composed of an adder pipeline and a complex BIST (Build In Self Test). When fabricated, this circuit will be tested. First a functional test will be realised, then laser pules attacks will be performed and finally a heavy ions attack campaign

A significant part of the System-on-a-Chip (SoC) design problem is in the correct composition of intellectual property (IP) blocks. Ever increasing clock frequencies make it impossible for signals to reach from one end of the chip to the other end within a clock cycle; this invalidates the so-called synchrony assumption, where the timing of computation and communication are assumed to be negligible, and happen within a clock cycle. Missing the timing deadline causes this violation, and may have ramifications on the overall system reliability. Although latency insensitive protocols (LIPs) have been proposed as a solution to the problem of signal propagation over long interconnects, they have their own limitations. A more generic solution comes in the form of globally asynchronous locally synchronous (GALS) designs. However, composing synchronous IP blocks either over long multicycle delay interconnects or over asynchronous communication links for a GALS design is a challenging task, especially for ensuring the functional correctness of the overall design. In this thesis, we analyze various solutions for solving the synchronization problems related with IP composition. We present alternative LIPs, and provide a validation framework for ensuring their correctness. Our notion of correctness is that of latency equivalence between a latency insensitive design and its synchronous counterpart. We propose a trace-based framework for analyzing synchronous behaviors of different IPs, and provide a correct-by-construction protocol for their transformation to a GALS design. We also present a design framework for facilitating GALS designs. In the framework, Kahn process network specifications are refined into correct-by-construction GALS designs. We present formal definitions for the refinements towards different GALS architectures. For facilitating GALS in distributed embedded software, we analyze certain subclasses of synchronous designs using a Pomset-based semantic model that allows for desynchronization toward GALS.<br>Ph. D.

The forward-looking design trend in Very Large Scale Integrated (VLSI) is Systems-on-Chip (SoC). SoC aims to integrate multiple computation, communication and storage components into a single chip and targets high performance systems by elimination of most on-chip communication costs. It is agreed that running SoC components under control of a single clock is not feasible and clock distribution has been revealed as a critical obstacle. Asynchronous techniques can be exploited to relax strict timing constraints of traditional design methodologies. A less radical solution is Globally Asynchronous Locally Synchronous (GALS) systems which offer potential advantages in this respect, as it preserves system modularity and concentrates on communication aspects. The problem with GALS design is the relative lack of familiarity of traditional designers with this approach. To deal with this, a methodology is proposed to allow designers implement GALS systems at a higher abstraction level which is independent of technology, protocol, data encoding or any other details of circuit design. With the recent advances in concurrent programming, Communicating Sequential Processes (CSP) has gained popularity again. The CSP-based programming languages, like Go, have emerged to allow software designers to exploit the model toward implementing scalable softwares. CSP has a long history since 90's in the hardware domain, mainly utilised by the Asynchronous community. In this thesis, a novel high level synthesis framework is proposed, called eTeak, which enables the designers to implement GALS-like systems in a CSP-based language (Balsa) without concerning about the timing issues at system level. The proposed approach in this thesis takes advantage of synchronous elasticity to introduce a common timing discipline to the circuit which transforms it into a latency-insensitive system. A latency-insensitive system is able to tolerate dynamic changes in the computation and communication delays. This feature enables eTeak to raise the level of abstraction to the data-flow representation where functionality is separated from timing details. Therefore, it is possible for a designer to specify a large scale system by only concentrating on its functionality and postpone timing complexity to when synthesis takes place. Unlike many previous systems, the proposed design flow employs data-driven synthesis style to distribute controllers through the network which contributes to its modularity and enhanced concurrency. This facilitates partitioning into elastic blocks and is supposed to pave the road for further optimisations, such retiming and re-synthesis, using commercial EDA tools.

碩士<br>國立交通大學<br>資訊科學與工程研究所<br>96<br>GALS can be used in SoC design because GALS provide a reliable communication by asynchronous channel between different modules. The latency of GALS interface is a problem which could cause performance degradation because there is no throughput when the communication occurs. Thus how to reduce the latency of GALS interface is significant. A faster, smaller stretchable clock GALS interface is implemented with Verilog and synthesized with TSMC 0.13μm cell library. The area and speed of the new design are compared to other designs finally. Also a Muller-pipeline FIFO storage element can be added between the data transmission path to avoid long time waiting of sender. These schemes decrease the communication time of modules thus improve the performance of GALS system.

Globally Asynchronous Locally Synchronous design style has evolved as a solution to increasing problems of distributing clocks at high frequency and with lower power consumption in DSM technologies. In GALS designs, partitioning a system into more locally synchronous sub-blocks reduces the size of each sub-block and allows higher clock frequency. Also, smaller sub-blocks reduce the capacitance in the clock networks because they need less H-tree levels. However, this implies a large number of sub-blocks, which increases the asynchronous power overhead. The thesis considers a 16 x 16 array of identical processors to evaluate GALS tradeoffs with different partitioning scenarios. Three different configurations of the array have been studied. This is, to our knowledge, the first work to propose closed form models for the optimum number of sub-blocks that accomplish minimum power for GALS design with passive clock distribution networks. Experimental results verify the effectiveness of the models. The potential increase in the clock frequency with partitioning and its effect on total power consumption has also been investigated for one of the array configurations. For large VLSI designs, inserting repeaters in the clock network is an alternative to boost the clock frequency that often is limited by the interconnect bandwidth. The thesis also investigates the GALS tradeoffs for an array with active clock networks. An algorithm has been proposed to evaluate the optimum partitioning in this case. The Delay-Insensitive (DI) asynchronous protocols offer a promising solution to the timing closure problem with long global interconnects in synchronous designs. A novel asynchronous wrapper using 1-of-4 DI protocol has been introduced. Simulation results show that the scheme achieves 66% higher throughput than previous designs.

As advances in VLSI technology enable higher levels of integration in system-on-a-chip (SoC) designs, fully synchronous implementations are becoming less feasible. Globally asynchronous locally synchronous (GALS) clocking is a promising alternative. Each core in a GALS system is a synchronous block (SB) of logic whose locally generated clock has an independent frequency and phase, while communication between cores is asynchronous. However, the nondeterministic behavior of most GALS methodologies is problematic for silicon debug and functional test. Deterministic GALS methodologies make assumptions about the profile of the asynchronous data which are valid only in a very limited set of applications. This dissertation proposes a novel deterministic GALS methodology called “synchro-tokens” which adds parameterized wrapper logic to the interfaces of the SBs. The wrapper ensures that each transition on each asynchronous input is sensed by the SB during a deterministic cycle of the local clock. Token rings are used for handshaking and self-timed first-in first-out (FIFO) buffers for pipelined interconnect. Counters in each SB keep track of the number of local clock cycles between arrivals and departures of the token to ignore early tokens and to stop the local clock to wait for late tokens. Because no synchronizers are used, there is zero probability of metastability. The wrapper parameters, such as FIFO sizes, counter values, and clock frequencies, offer a great deal of flexibility for tuning the system performance, making the synchro-tokens methodology useful for a wide range of applications. While data flow assumptions may be made for the purpose of setting these parameters, deterministic behavior is maintained regardless of the actual profile of the asynchronous data. The synchro-tokens architecture supports debug and test methodologies commonly applied to fully synchronous chips. The boundary scan Standard 1149.1 can be implemented with a SB whose clock is supplied through a TCK pin. Any number of internal scan chains for ATPG, BIST, or P1500 core test can cross SB boundaries by virtue of a self-timed shifting design. By interrupting the flow of tokens, system clocks can be deterministically stopped at natural breakpoints and single-stepped for cycle-by-cycle debug.

碩士<br>國立交通大學<br>資訊科學與工程研究所<br>97<br>Most modern digital systems are based on synchronous circuit design nowadays. But as we know, with the increasing complexity of digital circuits, there are some problems such as clock skew and power consumption. In addition, system on chip (SoC) design is another trend today. To integrate several intellectual property (IP) modules in a SoC design is not an easy job. Globally asynchronous locally synchronous (GALS) design is a promising approach to solve these problems. Compared with traditional four-phase handshaking, stretchable clocking based GALS systems, we propose a two-phase handshaking interface for stretchable clocking based GALS systems. In our design, the local synchronous modules can operate at different clock frequencies independently and work correctly. The design is synthesized with Synopsys Design Compiler with TSMC 0.13μm cell library. The result shows that the new two-phase handshaking design has better latency than four-phase handshaking counterpart. But from the viewpoint of area, the new two-phase handshaking design is larger than four-phase handshaking counterpart.

Throughout the years, synchronous circuits have increased in size and com-plexity, consequently, distributing a global clock signal has become a laborious task. Globally-Asynchronous Locally-Synchronous (GALS) systems emerge as a possible solution; however, these new systems require new tools. The DS-Pnet language formalism and the IOPT-Flow framework aim to support and accelerate the development of cyber-physical systems. To do so it offers a tool chain that comprises a graphical editor, a simulator and code gener-ation tools capable of generating C, JavaScript and VHDL code. However, DS-Pnets and IOPT-Flow are not yet tuned to handle GALS systems, allowing for partial specification, but not a complete one. This dissertation proposes extensions to the DS-Pnet language and the IOPT-Flow framework in order to allow development of GALS systems. Addi-tionally, some asynchronous components were created, these form interfaces that allow synchronous blocks within a GALS system to communicate with each other.

碩士<br>國立交通大學<br>電子工程系所<br>93<br>The interface circuit designs using handshake protocols and asynchronous first-in-first-out (FIFO) for globally-asynchronous locally-synchronous (GALS) systems are realized and apply to the Fast Fourier Transform Architecture in this thesis. A new pausible clock controller, write-port and read-port in asynchronous wrappers are proposed and data items can be transferred safely through adjacent wrappers operating at different clock frequencies. To increase the efficiency of throughput at the sender’s module, the asynchronous FIFO is inserted between two adjacent modules. An asynchronous FIFO cell is proposed to reduce the complexity of the handshake circuits by using Muller C element with some modifications. It has the properties of being low power, low latency and reusable. The physical layouts for the FIFO sizes of four, eight and sixteen are implemented based on the TSMC 0.13um 1P8M CMOS technology. The GALS design combined with dual-supply systems is applied to the 16-point radix-22 single-path delay feedback FFT architecture. The architecture is divided into three wrappers and each wrapper has its own local clock frequency and supply voltage. The interfaces formed from wrappers are implemented by handshake circuits and asynchronous FIFO, which are modified with level converters. Simulation results in TSMC 0.13um technology shows that the 16-point GALS-based FFT architecture in dual supply voltages has 30% power savings and 25.5% latency reduction compared to the globally-synchronous one in single supply voltage. These techniques will be widely used in the future systems-on-a-chip (SOC) design.

The miniaturisation of electronic circuits allows the potential for new applications, such as smart-dust or the Internet of Things. However, the design of batteries has not improved at the same rate as CMOS technology, so circuits need to be designed for improved energy efficiency to enable new form factors and applications. To address these issues, the use of subthreshold and near-threshold supply voltages is proposed. Throughout this thesis, the nature of what makes a design suitable for subthreshold use is examined. This work starts at the gate level, where the effects of transistor geometry and valency are examined. The levels of abstraction are progressively increased until high level architectures are considered, where quasi- delay-insensitive and globally-asynchronous locally-synchronous designs are argued as suitable for designing reliable systems. To assist in this, a methodology for partitioning systems into separate timing domains is proposed, and applied to published designs. The underlying theme throughout the exploration of subthreshold technology is the effects and mitigation of process and environmental variation, to which designs are increasingly susceptible as the supply voltage is lowered. This vulnerability affects all levels of design, from the widths of individual transistor to the choice of overall architectures, where a fundamental issue is the ability to determine when a unit of work has been performed. Not all applications respond well to the scaling of supply voltage. To address this, an alternative approach is considered where the system spends much of its lifetime in a powered-down state, being woken at appropriate intervals by a wakeup timer. As power consumption is a function of frequency, this timer seeks to achieve energy efficiency by maximising the period of oscillation. Despite the higher supply voltages considered, the themes of environmental and process variation continue, as the wakeup timers examined share similarities to subthreshold designs. Two of the proposed timers have been fabricated and are compared to simulated results and other published work.<br>Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2015.