Relevant bibliographies by topics / Hardware accelerated

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Hardware accelerated'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Hardware accelerated"

1

Fang, Shiaofen, and Hongsheng Chen. "Hardware accelerated voxelization." Computers & Graphics 24, no. 3 (2000): 433–42. http://dx.doi.org/10.1016/s0097-8493(00)00038-8.

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Fobel, Christian, Gary Gréwal, and Andrew Morton. "Hardware accelerated FPGA placement." Microelectronics Journal 40, no. 11 (2009): 1667–71. http://dx.doi.org/10.1016/j.mejo.2008.09.008.

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Lin, Daqi, Elena Vasiou, Cem Yuksel, Daniel Kopta, and Erik Brunvand. "Hardware-Accelerated Dual-Split Trees." Proceedings of the ACM on Computer Graphics and Interactive Techniques 3, no. 2 (2020): 1–21. http://dx.doi.org/10.1145/3406185.

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Bounding volume hierarchies (BVH) are the most widely used acceleration structures for ray tracing due to their high construction and traversal performance. However, the bounding planes shared between parent and children bounding boxes is an inherent storage redundancy that limits further improvement in performance due to the memory cost of reading these redundant planes. Dual-split trees can create identical space partitioning as BVHs, but in a compact form using less memory by eliminating the redundancies of the BVH structure representation. This reduction in memory storage and data movement
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Lloyd, Scott, and Quinn O. Snell. "Hardware Accelerated Sequence Alignment with Traceback." International Journal of Reconfigurable Computing 2009 (2009): 1–10. http://dx.doi.org/10.1155/2009/762362.

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Biological sequence alignment is an essential tool used in molecular biology and biomedical applications. The growing volume of genetic data and the complexity of sequence alignment present a challenge in obtaining alignment results in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. W
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KIM, Shinwook, and Tae-Gyu CHANG. "Neuromorphic Hardware Accelerated Lane Detection System." IEICE Transactions on Information and Systems E100.D, no. 12 (2017): 2871–75. http://dx.doi.org/10.1587/transinf.2017pal0004.

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Moscola, James, Ron K. Cytron, and Young H. Cho. "Hardware-Accelerated RNA Secondary-Structure Alignment." ACM Transactions on Reconfigurable Technology and Systems 3, no. 3 (2010): 1–44. http://dx.doi.org/10.1145/1839480.1839484.

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Delling, Daniel, Andrew V. Goldberg, Andreas Nowatzyk, and Renato F. Werneck. "PHAST: Hardware-accelerated shortest path trees." Journal of Parallel and Distributed Computing 73, no. 7 (2013): 940–52. http://dx.doi.org/10.1016/j.jpdc.2012.02.007.

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Sohanghpurwala, Ali Asgar, Mohamed W. Hassan, and Peter Athanas. "Hardware accelerated SAT solvers—A survey." Journal of Parallel and Distributed Computing 106 (August 2017): 170–84. http://dx.doi.org/10.1016/j.jpdc.2016.12.014.

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Li, Ming, Marcus Magnor, and Hans-Peter Seidel. "Hardware-Accelerated Rendering of Photo Hulls." Computer Graphics Forum 23, no. 3 (2004): 635–42. http://dx.doi.org/10.1111/j.1467-8659.2004.00795.x.

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ZHANG, FAN, HANQIU SUN, LEILEI XU, and KITLUN LEE. "HARDWARE-ACCELERATED PARALLEL-SPLIT SHADOW MAPS." International Journal of Image and Graphics 08, no. 02 (2008): 223–41. http://dx.doi.org/10.1142/s0219467808003064.

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Shadow mapping is well known for its generality and efficiency, thus it has been extensively employed for real-time shadow rendering in diverse applications. However, it suffers from inherent aliasing problem due to its image-based nature. In this paper, we present the parallel-split shadow maps scheme which produces high-quality shadows especially in large-scale and complex scenes. Our scheme splits the view frustum into parts using planes parallel to the view plane, and then generates a shadow map for each part. A fast and robust splitting strategy based on the analysis of shadow-map aliasin
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Dissertations / Theses on the topic "Hardware accelerated"

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Miller, Christopher Michael. "Hardware accelerated volume texturing." Thesis, Swansea University, 2006. https://cronfa.swan.ac.uk/Record/cronfa42524.

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The emergence of volume graphics, a sub field in computer graphics, has been evident for the last 15 years. Growing from scientific visualization problems, volume graphics has established itself as an important field in general computer graphics. However, the general graphics fraternity still favour the established surface graphics techniques. This is due to well founded and established techniques and a complete pipeline through software onto display hardware. This enables real-time applications to be constructed with ease and used by a wide range of end users due to the readily available grap
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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3600206.

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<p> Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.</p><p> Many forms of hardware acceleration exist&mdash;attributes and trade-offs of each approach is discussed. Single-algorithm accelerators, which maximize efficiency gains through maximum specialization, are one such approach. By combining many of these into a many-accelerator system, high specialization is possible with fewer specialization limits.</p><p> The development of one such single-algorithm hardware accelerator for managing com
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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2013. http://dissertations.umi.com/gsas.harvard:11152.

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Rhodes, Daniel Thomas. "Hardware accelerated computer graphics algorithms." Thesis, Nottingham Trent University, 2008. http://irep.ntu.ac.uk/id/eprint/201/.

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The advent of shaders in the latest generations of graphics hardware, which has made consumer level graphics hardware partially programmable, makes now an ideal time to investigate new graphical techniques and algorithms as well as attempting to improve upon existing ones. This work looks at areas of current interest within the graphics community such as Texture Filtering, Bump Mapping and Depth of Field simulation. These are all areas which have enjoyed much interest over the history of computer graphics but which provide a great deal of scope for further investigation in the light of recent
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Cervin, Albert. "Adaptive Hardware-accelerated Terrain Tessellation." Thesis, Linköpings universitet, Medie- och Informationsteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91334.

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In this master thesis report, a scheme for adaptive hardware terrain tessellation is presented. The scheme uses an offline processing approach where a height map is analyzed in terms of curvature and the result is stored in a resource called density map. This density map is then bound as a resource to the hardware tessellation stage and used to bias the tessellation factor for a given edge. The scheme is implemented inside FrostbiteTM2 by EATM DICETM and produces good results while making the heightfield rendering more efficient. The performance gain can be used to increase the rendering detai
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Magallón, Gherardelli Marcelo Eduardo. "Hardware accelerated volume visualization on PC clusters." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11259558.

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Ryan, Christopher A. "Parallel hardware accelerated switch level fault simulation." Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-10022007-145318/.

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Lindau, Ludvig. "Hardware accelerated ray tracing of particle systems." Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-20231.

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Background. Particle systems are a staple feature of most modern renderers. There are several technical challenges when it comes to rendering transparent particles. Particle sorting along the view direction is required for proper blending and casting shadows from particles requires non-standard shadow algorithms. A recent technology that could be used to adress these technical challenges is hardware accelerated ray tracing. However there is a lack of performance data gathered from this type of hardware. Objectives. The objective of this thesis is to measure the performance of a prototype that
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Snøve, Jr Ola. "Hardware-accelerated analysis of non-protein-coding RNAs." Doctoral thesis, Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-713.

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<p>A tremendous amount of genomic sequence data of relatively high quality has become publicly available due to the human genome sequencing projects that were completed a few years ago. Despite considerable efforts, we do not yet know everything that is to know about the various parts of the genome, what all the regions code for, and how their gene products contribute in the myriad of biological processes that are performed within the cells. New high-performance methods are needed to extract knowledge from this vast amount of information.</p><p>Furthermore, the traditional view that DNA codes
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Irick, Charles Robert. "Enhancing GNU Radio for Hardware Accelerated Radio Design." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/33474.

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As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the convent
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Books on the topic "Hardware accelerated"

1

Alex, Anish. Hardware Accelerated protein identification. National Library of Canada, 2003.

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Hill, David. An efficient, hardware-accelerated, level-of-detail rendering technique for large terrains. National Library of Canada, 2002.

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Whitehead, P. A. Design considerations for a hardware accelerator for Kohonen unsupervised learning in artificial neural networks. UMIST, 1997.

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Baron, Gerard Sta Maria. Graphics hardware accelerated time-domain modeling of wireless channel geometries. 2006.

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Baron, Gerard Sta Maria. Graphics hardware accelerated time-domain modeling of wireless channel geometries. 2006.

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Hansen, Norman H. The hardware accelerator array for logic simulation. 1991.

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Kim, Shiho, and Ganesh Chandra Deka. Hardware Accelerator Systems for Artificial Intelligence and Machine Learning. Elsevier Science & Technology Books, 2021.

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Hardware Accelerator Systems for Artificial Intelligence and Machine Learning. Elsevier, 2021. http://dx.doi.org/10.1016/s0065-2458(21)x0004-6.

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Unger, Herwig, and Wolfgang A. Halang, eds. Autonomous Systems 2017. VDI Verlag, 2017. http://dx.doi.org/10.51202/9783186857101.

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Owing to the overwhelming amount of often sensitive data hitting contemporary users of networked devices almost everywhere, this volume’s two keynote addresses deal with the security and ethical problems of the increasingly intelligent and autonomously acting devices in our environment. Then, light is shed on theoretical, algorithmic, technical and security aspects of big data analytics, data mining, information retrieval and machine learning. As no other area of computer science and engineering, autonomous systems accelerate the development of new systems’ hardware and highly specialised appl
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Book chapters on the topic "Hardware accelerated"

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Fang, Shiaofen, and Hongsheng Chen. "Hardware Accelerated Voxelisation." In Volume Graphics. Springer London, 2000. http://dx.doi.org/10.1007/978-1-4471-0737-8_20.

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Cabido, Raúl, Antonio S. Montemayor, and Ángel Sánchez. "Hardware-Accelerated Template Matching." In Pattern Recognition and Image Analysis. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11492429_83.

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Hopf, Matthias, and Thomas Ertl. "Hardware Accelerated Wavelet Transformations." In Eurographics. Springer Vienna, 2000. http://dx.doi.org/10.1007/978-3-7091-6783-0_10.

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Alex, Anish, Jonathan Rose, Ruth Isserlin-Weinberger, and Christopher Hogue. "Hardware Accelerated Novel Protein Identification." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_4.

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Atahary, Tanvir, Scott Douglass, and Tarek M. Taha. "Hardware Accelerated Mining of Domain Knowledge." In Advances in Information Security. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-7597-2_16.

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Paul, John, Elena Guralnik, Anatoly Koyfman, Amir Nahir, and Subrat K. Panda. "Leveraging Accelerated Simulation for Floating-Point Regression." In Hardware and Software: Verification and Testing. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3_15.

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Xie, Mao-Jin, and Wei-Qun Cao. "A Hardware Accelerated Algorithm for Terrain Visualization." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-02713-0_29.

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Ashraf, Golam, and Junyu Zhou. "Hardware Accelerated Skin Deformation for Animated Crowds." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/978-3-540-69429-8_23.

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Dongarra, Jack, Jakub Kurzak, Piotr Luszczek, and Stanimire Tomov. "Dense Linear Algebra on Accelerated Multicore Hardware." In High-Performance Scientific Computing. Springer London, 2012. http://dx.doi.org/10.1007/978-1-4471-2437-5_5.

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McGraw, Tim, and Brian Sowers. "Hardware Accelerated Per-Texel Ambient Occlusion Mapping." In Advances in Visual Computing. Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89639-5_106.

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Conference papers on the topic "Hardware accelerated"

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McDonald, Eric J., Nathaniel W. Schlossberg, and Eugene Grayver. "Hardware accelerated multichannel receiver." In 2009 IEEE Aerospace conference. IEEE, 2009. http://dx.doi.org/10.1109/aero.2009.4839418.

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Wu, ZhongPan, Karim Hammad, Yunus Dawji, Ebrahim Ghafar-Zadeh, and Sebastian Magierowski. "Hardware Accelerated DNA Sequencing." In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018. http://dx.doi.org/10.1109/mwscas.2018.8623915.

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Polig, R., K. Atasu, C. Hagleitner, et al. "Hardware-accelerated text analytics." In 2014 IEEE Hot Chips 26 Symposium (HCS). IEEE, 2014. http://dx.doi.org/10.1109/hotchips.2014.7478822.

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Ritter, Daniel. "Hardware accelerated application integration." In Middleware '17: 18th International Middleware Conference. ACM, 2017. http://dx.doi.org/10.1145/3155889.3156048.

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Yuksel, Cem. "Hardware accelerated mesh colors." In I3D '16: Symposium on Interactive 3D Graphics and Games. ACM, 2016. http://dx.doi.org/10.1145/2856400.2876017.

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Kim, Seunghoe, and Woongki Baek. "HAPT: hardware-accelerated persistent transactions." In 2016 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2016. http://dx.doi.org/10.1109/nvmsa.2016.7547181.

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Vidanagamachchi, S. M., S. D. Dewasurendra, and R. G. Ragel. "Hardware accelerated protein inference framework." In 2013 IEEE 8th International Conference on Industrial and Information Systems (ICIIS). IEEE, 2013. http://dx.doi.org/10.1109/iciinfs.2013.6732061.

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Sarrar, Nadi, Anja Feldmann, Steve Uhlig, Rob Sherwood, and Xin Huang. "Towards hardware accelerated software routers." In the ACM CoNEXT Student Workshop. ACM Press, 2010. http://dx.doi.org/10.1145/1921206.1921209.

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Goddard, Luke, and Ian Stephenson. "Hardware accelerated shaders using FPGA's." In ACM SIGGRAPH 2008 posters. ACM Press, 2008. http://dx.doi.org/10.1145/1400885.1400942.

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Chua, Clint, and Ulrich Neumann. "Hardware-accelerated free-form deformation." In the ACM SIGGRAPH/EUROGRAPHICS workshop. ACM Press, 2000. http://dx.doi.org/10.1145/346876.346884.

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Reports on the topic "Hardware accelerated"

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Hansen, N. H. The hardware accelerator array for logic simulation. Office of Scientific and Technical Information (OSTI), 1991. http://dx.doi.org/10.2172/5569259.

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Welch, Kimo M. Acquisition of Reliable Vacuum Hardware for Large Accelerator Systems. Office of Scientific and Technical Information (OSTI), 1995. http://dx.doi.org/10.2172/1119389.

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Glesener, W. F., and E. L. Garwin. Projected Life of the SLAC Linac Braze Joints: Braze integrity and corrosion of cooling water hardware on accelerator sections. Office of Scientific and Technical Information (OSTI), 2006. http://dx.doi.org/10.2172/887074.

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Journal articles Dissertations / Theses
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