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Dissertations / Theses on the topic 'Hardware accelerated'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Miller, Christopher Michael. "Hardware accelerated volume texturing." Thesis, Swansea University, 2006. https://cronfa.swan.ac.uk/Record/cronfa42524.

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The emergence of volume graphics, a sub field in computer graphics, has been evident for the last 15 years. Growing from scientific visualization problems, volume graphics has established itself as an important field in general computer graphics. However, the general graphics fraternity still favour the established surface graphics techniques. This is due to well founded and established techniques and a complete pipeline through software onto display hardware. This enables real-time applications to be constructed with ease and used by a wide range of end users due to the readily available grap

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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3600206.

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<p> Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.</p><p> Many forms of hardware acceleration exist—attributes and trade-offs of each approach is discussed. Single-algorithm accelerators, which maximize efficiency gains through maximum specialization, are one such approach. By combining many of these into a many-accelerator system, high specialization is possible with fewer specialization limits.</p><p> The development of one such single-algorithm hardware accelerator for managing com

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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2013. http://dissertations.umi.com/gsas.harvard:11152.

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4

Rhodes, Daniel Thomas. "Hardware accelerated computer graphics algorithms." Thesis, Nottingham Trent University, 2008. http://irep.ntu.ac.uk/id/eprint/201/.

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The advent of shaders in the latest generations of graphics hardware, which has made consumer level graphics hardware partially programmable, makes now an ideal time to investigate new graphical techniques and algorithms as well as attempting to improve upon existing ones. This work looks at areas of current interest within the graphics community such as Texture Filtering, Bump Mapping and Depth of Field simulation. These are all areas which have enjoyed much interest over the history of computer graphics but which provide a great deal of scope for further investigation in the light of recent

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Cervin, Albert. "Adaptive Hardware-accelerated Terrain Tessellation." Thesis, Linköpings universitet, Medie- och Informationsteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91334.

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In this master thesis report, a scheme for adaptive hardware terrain tessellation is presented. The scheme uses an offline processing approach where a height map is analyzed in terms of curvature and the result is stored in a resource called density map. This density map is then bound as a resource to the hardware tessellation stage and used to bias the tessellation factor for a given edge. The scheme is implemented inside FrostbiteTM2 by EATM DICETM and produces good results while making the heightfield rendering more efficient. The performance gain can be used to increase the rendering detai

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Magallón, Gherardelli Marcelo Eduardo. "Hardware accelerated volume visualization on PC clusters." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11259558.

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7

Ryan, Christopher A. "Parallel hardware accelerated switch level fault simulation." Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-10022007-145318/.

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Lindau, Ludvig. "Hardware accelerated ray tracing of particle systems." Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-20231.

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Background. Particle systems are a staple feature of most modern renderers. There are several technical challenges when it comes to rendering transparent particles. Particle sorting along the view direction is required for proper blending and casting shadows from particles requires non-standard shadow algorithms. A recent technology that could be used to adress these technical challenges is hardware accelerated ray tracing. However there is a lack of performance data gathered from this type of hardware. Objectives. The objective of this thesis is to measure the performance of a prototype that

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Snøve, Jr Ola. "Hardware-accelerated analysis of non-protein-coding RNAs." Doctoral thesis, Norwegian University of Science and Technology, Faculty of Information Technology, Mathematics and Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-713.

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<p>A tremendous amount of genomic sequence data of relatively high quality has become publicly available due to the human genome sequencing projects that were completed a few years ago. Despite considerable efforts, we do not yet know everything that is to know about the various parts of the genome, what all the regions code for, and how their gene products contribute in the myriad of biological processes that are performed within the cells. New high-performance methods are needed to extract knowledge from this vast amount of information.</p><p>Furthermore, the traditional view that DNA codes

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Irick, Charles Robert. "Enhancing GNU Radio for Hardware Accelerated Radio Design." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/33474.

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As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the convent

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Andersson, Mikael, and Per Karlström. "Parallel JPEG Processing with a Hardware Accelerated DSP Processor." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2615.

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<p>This thesis describes the design of fast JPEG processing accelerators for a DSP processor. </p><p>Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. </p><p>First a decoder and an encoder were implemented in DSP assembler. Th

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Sætrom, Pål. "Hardware accelerated genetic programming for pattern mining in strings." Doctoral thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-1625.

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<p>This thesis considers the problem of mining patterns in strings. Informally, this is the problem of extracting information (patterns) that characterizes parts of, or even the complete, string. The thesis describes a high performance hardware for string searching, which together with genetic programming, forms the basis for the thesis’ pattern mining algorithms.</p><p>This work considers two different pattern mining problems and develops several different algorithms to solve different variants of these problems. Common to all algorithms is that they use genetic programming to evolve patterns

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Tasoulas, Zois Gerasimos. "Resource management and application customization for hardware accelerated systems." OpenSIUC, 2021. https://opensiuc.lib.siu.edu/dissertations/1907.

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Computational demands are continuously increasing, driven by the growing resource demands of applications. At the era of big-data, big-scale applications, and real-time applications, there is an enormous need for quick processing of big amounts of data. To meet these demands, computer systems have shifted towards multi-core solutions. Technology scaling has allowed the incorporation of even larger numbers of transistors and cores into chips. Nevertheless, area constrains, power consumption limitations, and thermal dissipation limit the ability to design and sustain ever increasing chips. To ov

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Pacura, Dávid. "Hardware Accelerated Digital Image Stabilization in a Video Stream." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255435.

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Cílem této práce je návrh nové techniky pro stabilizaci obrazu za pomoci hardwarové akcelerace prostřednictvím GPGPU. Využití této techniky umožnuje stabilizaci videosekvencí v reálném čase i pro video ve vysokém rozlišení. Toho je zapotřebí pro ulehčení dalšího zpracování v počítačovém vidění nebo v armádních aplikacích. Z důvodu existence vícerých programovacích modelů pro GPGPU je navrhnutý stabilizační algoritmus implementován ve třech nejpoužívanějších z nich. Jejich výkon a výsledky jsou následně porovnány a diskutovány.

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Yee, Wai Min. "Cache Design for a Hardware Accelerated Sparse Texture Storage System." Thesis, University of Waterloo, 2004. http://hdl.handle.net/10012/1197.

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Hardware texture mapping is essential for real-time rendering. Unfortunately the memory bandwidth and latency often bounds performance in current graphics architectures. Bandwidth consumption can be reduced by compressing the texture map or by using a cache. However, the way a texture map occupies memory and how it is accessed affects the pattern of memory accesses, which in turn affects cache performance. Thus texture compression schemes and cache architectures must be designed in conjunction with each other. We define a sparse texture to be a texture where a substanti

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Jun, Sang-Woo. "Big data analytics made affordable using hardware-accelerated flash storage." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/118088.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 175-192).<br>Vast amount of data is continuously being collected from sources including social networks, web pages, and sensor networks, and their economic value is dependent on our ability to analyze them in a timely and affordable manner. High performance analytics have traditionally required a machine or a cluster of machines with enough DRAM to accommodate the entire working set, due to

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Bankarusamy, Sudhangathan. "Towards hardware accelerated rectification of high speed stereo image streams." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-37522.

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The process of combining two views of a scene in order to obtain depth information is called stereo vision. When the same is done using a computer it is then called computer stereo vision. Stereo vision is used in robotic application where depth of an object plays a role. Two cameras mounted on a rig is called a stereo camera system. Such a system is able to capture two views and enable robotic application to use the depth information to complete tasks. Anomalies are bound to occur in such a stereo rig, when both the cameras are not parallel to each other. Mounting of the cameras on a rig accu

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Navrátil, Ladislav. "Accelerated Graphical User Interfaces." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236168.

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Tato práce je zaměřena na multiplatformní grafická uživatelské rozhraní a jejich hardwarovou akceleraci. Popisuje, co to uživatelské rozhraní jsou a srovnává nástroje na jejich tvorbu a způsoby jejich realizace. Hlavním bodem je vlastní návrh a implementace nástroje na tvorbu multiplatformních hardwarově akcelerovaných grafických uživatelských rozhraní. Srovnává vlastní koncept s existujícími řešeními, a uvádí ho do praxe na projektu s externí firmou.

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Gwosdek, Pascal [Verfasser], and Joachim [Akademischer Betreuer] Weickert. "Hardware-accelerated algorithms in visual computing / Pascal Gwosdek. Betreuer: Joachim Weickert." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2012. http://d-nb.info/1052549853/34.

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Karve, Mrudula Prabhakar. "Evaluation of GNU Radio Platform Enhanced for Hardware Accelerated Radio Design." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36405.

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The advent of software radio technology has enabled radio developers to design and imple- ment radios with great ease and flexibility. Software radios are effective in experimentation and development of radio designs. However, they have limitations when it comes to high- speed, high-throughput designs. This limitation can be overcome by introducing a hardware element to the software radio platform. Enhancing GNU Radio for Hardware Accelerated Radio Design project implements such a scheme by augmenting an FPGA co-processor to a conventional GNU Radio flow. In this thesis, this novel platform is

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Choi, Yuk-ming, and 蔡育明. "A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/206679.

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The era of big data has led to problems of unprecedented scale and complexity that are challenging the computing capability of conventional computer systems. One way to address the computational and communication challenges of such demanding applications is to incorporate the use of non-conventional hardware accelerators such as FPGAs into existing systems. By providing a mix of FPGAs and conventional CPUs as computing resources in a heterogeneous cluster, a distributed computing environment can be achieved to address the need of both compute-intensive and data-intensive applications. However,

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Müller, Eric Christian [Verfasser], and Karlheinz [Akademischer Betreuer] Meier. "Novel Operation Modes of Accelerated Neuromorphic Hardware / Eric Christian Müller ; Betreuer: Karlheinz Meier." Heidelberg : Universitätsbibliothek Heidelberg, 2015. http://d-nb.info/1180395220/34.

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Durbha, Sriram. "A methodology for analyzing hardware accelerated continuous-time methods for mixed signal simulatiion." Cincinnati, Ohio : University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=ucin1091060658.

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Van, Belle Jonathan. "Accelerated deconvolution of radio interferometric images using orthogonal matching pursuit and graphics hardware." Master's thesis, University of Cape Town, 2016. http://hdl.handle.net/11427/22991.

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Deconvolution of native radio interferometric images constitutes a major computational component of the radio astronomy imaging process. An efficient and robust deconvolution operation is essential for reconstruction of the true sky signal from measured correlator data. Traditionally, radio astronomers have mostly used the CLEAN algorithm, and variants thereof. However, the techniques of compressed sensing provide a mathematically rigorous framework within which deconvolution of radio interferometric images can be implemented. We present an accelerated implementation of the orthogonal matching

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DURBHA, SRIRAM. "A METHODOLOGY FOR ANALYZING HARDWARE ACCELERATED CONTINUOUS-TIME METHODS FOR MIXED SIGNAL SIMULATION." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1091060658.

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Gregertsen, Kristoffer Nyborg. "Execution Time Control : A hardware accelerated Ada implementation with novel support for interrupt handling." Doctoral thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for teknisk kybernetikk, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-16201.

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Execution time control is a technique that allows execution time budgets to be set and overruns to be handled dynamically to prevent deadline misses. This removes the need for the worst-case execution time (WCET) of tasks to be found by offline timing analysis – a problem that can be very hard to solve for modern computer architectures. Execution time control can also increase the processor utilization, as the WCET will often be much higher than the average execution time. This thesis describes how the GNU Ada Compiler and a bare-board Ravenscar run-time environment were ported to the Atmel AV

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Raval, Rajkumar Krushnakumar. "Content driven energy efficiency analysis of hardware accelerated spatial filters for digital image processing." Thesis, University of Reading, 2018. http://centaur.reading.ac.uk/80598/.

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Portable and mobile computing devices that run on batteries such as mobile phones, low-power and ultra-low-power IoT devices, wearable computing devices, wireless video sensor nodes etc. have become an indispensable part of human daily life. One of the major challenges is to have the longest battery life in such devices. Battery life time of the device depends on its energy efficiency which depends on the power consumption of the device. Power consumption of a device can be derived from the rate at which the device consumes energy. Many of these modern devices have touch screens where the cont

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Lundkvist, Herman, and Alexander Yngve. "Accelerated Simulation of Modelica Models Using an FPGA-Based Approach." Thesis, Linköpings universitet, Datorteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-145692.

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This thesis presents Monza, a system for accelerating the simulation of modelsof physical systems described by ordinary differential equations, using a generalpurpose computer with a PCIe FPGA expansion card. The system allows bothautomatic generation of an FPGA implementation from a model described in theModelica programming language, and simulation of said system.Monza accomplishes this by using a customizable hardware architecture forthe FPGA, consisting of a variable number of simple processing elements. A cus-tom compiler, also developed in this thesis, tailors and programs the architectu

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Najafi, Mohammadreza [Verfasser], Hans-Arno [Akademischer Betreuer] Jacobsen, Charles [Gutachter] Zhang, and Hans-Arno [Gutachter] Jacobsen. "Hardware Accelerated Stream Processing / Mohammadreza Najafi ; Gutachter: Charles Zhang, Hans-Arno Jacobsen ; Betreuer: Hans-Arno Jacobsen." München : Universitätsbibliothek der TU München, 2019. http://d-nb.info/1204200173/34.

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Schwartz, Marc-Olivier [Verfasser], and Karlheinz [Akademischer Betreuer] Meier. "Reproducing Biologically Realistic Regimes on a Highly-Accelerated Neuromorphic Hardware System / Marc-Olivier Schwartz ; Betreuer: Karlheinz Meier." Heidelberg : Universitätsbibliothek Heidelberg, 2013. http://d-nb.info/1177148455/34.

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Ma, Yunfeng. "Hardware-accelerated evolutionary hard real-time task mapping for wormhole network-on-chip with priority-preemptive arbitration." Thesis, University of York, 2016. http://etheses.whiterose.ac.uk/20446/.

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Network-on-Chip (NoC) is an alternative on-chip interconnection paradigm to replace existing ones such as Point-to-Point and shared bus. NoCs designed for hard real-time systems need to guarantee the system timing performance, even in the worst-case scenario. A carefully planned task mapping which indicates how tasks are distributed on a NoC platform can improve or guarantee their timing performance. While existing offline mapping optimisations can satisfy timing requirements, this is obtained by sacrificing the flexibility of the system. In addition, the design exploration process will be pro

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Lloyd, G. Scott. "Accelerated Large-Scale Multiple Sequence Alignment with Reconfigurable Computing." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2729.

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Multiple Sequence Alignment (MSA) is a fundamental analysis method used in bioinformatics and many comparative genomic applications. The time to compute an optimal MSA grows exponentially with respect to the number of sequences. Consequently, producing timely results on large problems requires more efficient algorithms and the use of parallel computing resources. Reconfigurable computing hardware provides one approach to the acceleration of biological sequence alignment. Other acceleration methods typically encounter scaling problems that arise from the overhead of inter-process communication

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Iyer, Srikrishna. "A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/34625.

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Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low power FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/software co-design for sensor node application development. We present the integration of nesC, a sensornet programming language, with GEZEL, an easy-to-use hardware description language. We describe th

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Werner, Stefan [Verfasser]. "Hybrid architecture for hardware-accelerated query processing in semantic web databases based on runtime reconfigurable FPGAs / Stefan Werner." Lübeck : Zentrale Hochschulbibliothek Lübeck, 2017. http://d-nb.info/1143986946/34.

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Hansson, Söderlund Herman. "Hardware-Accelerated Ray Tracing of Implicit Surfaces : A study of real-time editing and rendering of implicit surfaces." Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-21764.

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Background. Rasterization of triangle geometry has been the dominating rendering technique in the real-time rendering industry for many years. However, triangles are not always easy to work with for content creators. With the introduction of hardware-accelerated ray tracing, rasterization-based lighting techniques have been steadily replaced by ray tracing techniques. This shift may signify the opportunity of exploring other, more easily manipulated, geometry-type alternatives compared to triangle geometry. One such geometry type is implicit surfaces. Objectives. This thesis investigates the r

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Waldner, Fabian. "Real-time Ray Traced Ambient Occlusion and Animation : Image quality and performance of hardware- accelerated ray traced ambient occlusion." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-298085.

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Recently, new hardware capabilities in GPUs has opened the possibility of ray tracing in real-time at interactive framerates. These new capabilities can be used for a range of ray tracing techniques - the focus of this thesis is on ray traced ambient occlusion (RTAO). This thesis evaluates real-time ray RTAO by comparing it with ground- truth ambient occlusion (GTAO), a state-of-the-art screen space ambient occlusion (SSAO) method. A contribution by this thesis is that the evaluation is made in scenarios that includes animated objects, both rigid-body animations and skinning animations. This a

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Shareef, Naeem O. "Remote user-driven exploration of large scale volume data." Connect to this title online, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1117599341.

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Thesis (Ph. D.)--Ohio State University, 2005.<br>Title from first page of PDF file. Document formatted into pages; contains xvii, 104 p.; also includes graphics (some col.) Includes bibliographical references (p. 94-104). Available online via OhioLINK's ETD Center

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Zugárek, Adam. "Hardwarově akcelerovaný přenos dat s využitím TLS protokolu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413087.

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This paper describes implementation of the whole cryptographic protocol TLS including control logic and used cryptographic systems. The goal is to implement an application in the FPGA technology, so it could be used in hardware accelerated network card. The reason for this is new supported higher transmission speeds that Ethernet is able to operate on, and the absence of implementation of this protocol on FPGA. In the first half of this paper is described theory of cryptography followed by description of TLS protocol, its development, structure and operating workflow. The second half describes

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Wang, Lei. "Hardware accelerated Nios II implementation of Hilbert Huang Transform = 基於Nios II 軟核處理器的希爾伯特黃變換硬體加速實現". Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2182893.

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Chen, Zhe. "Hardware Accelerator of Matrix Multiplication on FPGAs : Hardware Accelerator of Matrix Multiplication on FPGAs." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-366815.

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To solve the computational complexity and time-consuming problem of large matrix multiplication, this thesis design a hardware accelerator using parallel computation structure based on FPGA. After function simulation in ModelSim, matrix multiplication functional modules as a custom component used as a coprocessor in co-operation with Nios II CPU by Avalon bus interface. To analyze computation performance of the hardware accelerator, two software systems are designed for comparison. The results show that the hardware accelerator can improve the computational performance of matrix multiplication

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Kempe, Marcus, and Carl Åbjörnsson. "Navigation, Visualisation and Editing of Very Large 2D Graphics Scenes." Thesis, Linköping University, Department of Science and Technology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2684.

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<p>The project has been carried out at, and in association with, Micronic Laser Systems AB in Täby, Sweden. Micronic Laser Systems, manufacture laser pattern generators for the semiconductor and display markets. Laser pattern generators are used to create photomasks, which are a key component in the microlithographic process of manufacturing microchips and displays. </p><p>An essential problem to all modern semiconductor manufacturing is the constantly decreasing sizes of features and increasing use of resolution enhancement techniques (RET), leading to ever growing sizes of datasets describin

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Lee, Junghee. "Many-core architecture for programmable hardware accelerator." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50319.

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As the further development of single-core architectures faces seemingly insurmountable physical and technological limitations, computer designers have turned their attention to alternative approaches. One such promising alternative is the use of several smaller cores working in unison as a programmable hardware accelerator. It is clear that the vast – and, as yet, largely untapped – potential of hardware accelerators is coming to the forefront of computer architecture. There are many challenges that must be addressed for the programmable hardware accelerator to be realized in practice. In this

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Mukre, Prakash. "Hardware accelerator for DNA code word searching." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2008.<br>Includes bibliographical references.

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Liu, Boyan. "A Data Sorting Hardware Accelerator on FPGA." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277851.

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In recent years, with the rise of the application of big data, efficiency has become more important for data processing, and simple sorting methods require higher stability and efficiency in large-scale scenarios. This thesis explores topics related to hardware acceleration for data sorting networks of massive input resource or data stream, which leads to our three different design approaches: running the whole data processing fully on the software side (sorting and merging on PC), a combination of PC side and field- programmable gate arrays (FPGA) platform (hardware sorting with software merg

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Ford, Nicky. "3D graphics hardware prototyping and implementation." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.367768.

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Sharma, Prashant. "Hardware accelerator for SOM based DNA sequencing Algorithm." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-251808.

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The prevalent experience based diagnosis of health problem are often incorrect. Different aspect of this problem are microorganism’s adaptation of antibiotics and effectiveness of the generic medicines on each individual etc. The DNA sequencing based diagnosis is evolving to deal with this problem. The algorithmic part of these techniques is difficult to speedup and therefore have a high latency. As a solution to this problem, machine learning based methods, such as BioNN, uses self organizing maps(SOM) which do not need an explicit assembly process and categorizes bacteria with smaller sample

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Dodge, Christopher J. "A fast Fourier Transform accelerator for a transputer system." Thesis, University of Aberdeen, 1993. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU554537.

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Multiple Instruction, Multiple Data (MIMD) networks can produce scalable processing power for a wide variety of image computing applications. For certain tasks however, data-distribution bottlenecks reduce the maximum achievable performance gain. Digital Signal Processing (DSP) technology is capable of high performance from a single processor, thus avoiding some of the data communication problems associated with multi-processor systems. Nevertheless, many practical applications require the incorporation of processing primitives provided by single computational elements, such as DSP, within a m

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Fox, Matthew (Matthew M. ). "Functional and timing models for a programmable hardware accelerator." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100595.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (page 79).<br>Classes of problems that exhibit high levels of data reuse have heavy overhead costs due to the necessity of repeated memory accesses. A proposed programmable hardware accelerator using a spatial architecture paired w

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Tan, Shawn Ser Ngiap. "Design and development of a heterogeneous hardware search accelerator." Thesis, University of Cambridge, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.608686.

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Truter, J. N. J. "Using CAMAC hardware for access to a particle accelerator." Master's thesis, University of Cape Town, 1988. http://hdl.handle.net/11427/17049.

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Includes bibliographical references and index.<br>The design and implementation of a method to software interface high level applications programs used for the control and monitoring of a Particle Accelerator is described. Effective methods of interfacing the instrumentation bus system with a Real time multitasking computer operating system were examined and optimized for efficient utilization of the operating system software and available hardware. Various methods of accessing the instrumentation bus are implemented as well as demand response servicing of the instruments on the bus.

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