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Journal articles on the topic 'Hardware and software co-simulation'

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Published: 4 June 2021
Last updated: 10 February 2022

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1

Wang, Shihao. "Software Simulation for Hardware/Software Co-Verification." Journal of Computer Research and Development 42, no. 3 (2005): 514. http://dx.doi.org/10.1360/crad20050322.

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2

AhmedAsifFuad, Kazi, and Shahriyar Masud Rizvi. "Hardware Software Co-Simulation of Canny Edge Detection Algorithm." International Journal of Computer Applications 122, no. 19 (2015): 7–12. http://dx.doi.org/10.5120/21806-5124.

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3

Vikram, K. N., and V. Vasudevan. "Hardware–software co-simulation of bus-based reconfigurable systems." Microprocessors and Microsystems 29, no. 4 (2005): 133–44. http://dx.doi.org/10.1016/j.micpro.2004.07.004.

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4

Milik, Adam, and Edward Hrynkiewicz. "Accelerated Co-Simulation of Hardware-Software System Based on Configurable Hardware Accelertor and Selective Simulation." IFAC Proceedings Volumes 36, no. 1 (2003): 31–36. http://dx.doi.org/10.1016/s1474-6670(17)33710-2.

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5

Júnior, José, Alisson Brito, and Tiago Nascimento. "Verification of Embedded System Designs through Hardware-Software Co-Simulation." International Journal of Information and Electronics Engineering 5, no. 1 (2015): 68–73. http://dx.doi.org/10.7763/ijiee.2015.v5.504.

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6

Qi, Dan, Mo Chen, Shaozhen Zhang, Dan Cheng, and Jun Mu. "Software and hardware co-simulation verification platform for navigation SoC." Journal of Physics: Conference Series 1735 (January 2021): 012010. http://dx.doi.org/10.1088/1742-6596/1735/1/012010.

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7

Díaz, Edel, Raúl Mateos, Emilio J. Bueno, and Rubén Nieto. "Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms." Electronics 10, no. 6 (2021): 759. http://dx.doi.org/10.3390/electronics10060759.

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Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.
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8

De Michell, G., and R. K. Gupta. "Hardware/software co-design." Proceedings of the IEEE 85, no. 3 (1997): 349–65. http://dx.doi.org/10.1109/5.558708.

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9

Mills, Mike, and Greg Peterson. "Hardware/software co-design." ACM SIGAda Ada Letters XVIII, no. 6 (1998): 18–27. http://dx.doi.org/10.1145/301687.289528.

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10

M Prasad, Thotamsetty. "Hardware/Software Co-Simulation of BPSK Modulator Using Xilinx System Generator." IOSR Journal of Engineering 02, no. 10 (2012): 54–58. http://dx.doi.org/10.9790/3021-021015458.

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11

Morris, D. "Simulating the Behaviour of Computer Systems: Co-simulation of Hardware/Software." Computer Journal 40, no. 10 (1997): 617–29. http://dx.doi.org/10.1093/comjnl/40.10.617.

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12

Kinoshita, Shingo, Hiroyuki Yamashita, Toshihiko Suguri, and Kouichi Nagami. "Hardware/software co-simulation focusing on functional verification of large-scale ASICs." Systems and Computers in Japan 30, no. 1 (1999): 43–59. http://dx.doi.org/10.1002/(sici)1520-684x(199901)30:1<43::aid-scj5>3.0.co;2-9.

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13

Birla, Shilpi, Shikha Sharma, and Neeraj Kr Shukla. "UVM-powered hardware/software co-verification." Journal of Information and Optimization Sciences 38, no. 6 (2017): 945–52. http://dx.doi.org/10.1080/02522667.2017.1372141.

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14

Aronsson, Markus, and Mary Sheeran. "Hardware software co-design in Haskell." ACM SIGPLAN Notices 52, no. 10 (2017): 162–73. http://dx.doi.org/10.1145/3156695.3122970.

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15

Hang, Tu, Wu Tao-jun, and Li Yuan-xiang. "Evolvable Hardware based software-hardware Co-designing platform ECDP." Wuhan University Journal of Natural Sciences 10, no. 6 (2005): 977–82. http://dx.doi.org/10.1007/bf02832451.

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16

Baldwin, Brian, Raveen R. Goundar, Mark Hamilton, and William P. Marnane. "Co- $$Z$$ ECC scalar multiplications for hardware, software and hardware–software co-design on embedded systems." Journal of Cryptographic Engineering 2, no. 4 (2012): 221–40. http://dx.doi.org/10.1007/s13389-012-0042-2.

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17

Gupta, Adhyana. "Hardware Software Co-Simulation for Traffic Load Computation Using Matlab Simulink Model Blockset." International Journal of Computational Science and Information Technology 1, no. 2 (2013): 1–12. http://dx.doi.org/10.5121/ijcsity.2013.1201.

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18

Mankar, Dushyant. "A Review on Implementation of Image Processing Algorithms using Hardware Software Co-simulation." International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 1 (2015): 14–17. http://dx.doi.org/10.17762/ijritcc2321-8169.150104.

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19

Balboni, Alessandro, William Fornaciari, and Donatella Sciuto. "Co-synthesis and co-simulation of control-dominated embedded systems." Design Automation for Embedded Systems 1, no. 3 (1996): 257–89. http://dx.doi.org/10.1007/bf00133305.

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20

Mekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.

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Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.
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21

Yang, Fu, Liu Xin, and Pei Yuan Guo. "A Multi-Objective Optimization Genetic Algorithm for SOPC Hardware-Software Partitioning." Advanced Materials Research 457-458 (January 2012): 1142–48. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1142.

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Hardware-software partitioning is the key technology in hardware-software co-design; the results will determine the design of system directly. Genetic algorithm is a classical search algorithm for solving such combinatorial optimization problem. A Multi-objective genetic algorithm for hardware-software partitioning is presented in this paper. This method can give consideration to both system performance and indicators such as time, power, area and cost, and achieve multi-objective optimization in system on programmable chip (SOPC). Simulation results show that the method can solve the SOPC hardware-software partitioning problem effectively.
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22

Grierson, W. O. "Perspectives in Simulation Hardware and Software Architecture." Modeling, Identification and Control: A Norwegian Research Bulletin 6, no. 4 (1985): 249–55. http://dx.doi.org/10.4173/mic.1985.4.5.

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23

Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (2018): 122. http://dx.doi.org/10.3390/jimaging4100122.

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Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images.
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24

Kent, K. B., M. Serra, and N. Horspool. "Hardware/software co-design for virtual machines." IEE Proceedings - Computers and Digital Techniques 152, no. 5 (2005): 537. http://dx.doi.org/10.1049/ip-cdt:20041264.

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25

Yanbing Li and W. H. Wolf. "Hardware/software co-synthesis with memory hierarchies." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 10 (1999): 1405–17. http://dx.doi.org/10.1109/43.790618.

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26

Wirth, Niklaus. "Hardware/software co-design then and now." Information Processing Letters 88, no. 1-2 (2003): 83–87. http://dx.doi.org/10.1016/s0020-0190(03)00385-5.

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27

Gómez-Pulido, Juan A. "Recent advances in Hardware/Software co-design." Journal of Systems Architecture 56, no. 8 (2010): 303–4. http://dx.doi.org/10.1016/j.sysarc.2010.06.008.

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28

Wolf, W. H. "Hardware-software co-design of embedded systems." Proceedings of the IEEE 82, no. 7 (1994): 967–89. http://dx.doi.org/10.1109/5.293155.

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29

Bennour, Imed E., Mohamed Abid, and Rached Tourki. "Hardware/Software Co-Verification: Models and Methods." Systems Analysis Modelling Simulation 42, no. 9 (2002): 1391–417. http://dx.doi.org/10.1080/716067216.

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30

Mian, Riaz-ul-haque, Michihiro Shintani, and Michiko Inoue. "Hardware–Software Co-Design for Decimal Multiplication." Computers 10, no. 2 (2021): 17. http://dx.doi.org/10.3390/computers10020017.

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Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.
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31

Elangovan, S., S. Sasikala, S. Arun Kumar, M. Bharathi, E. Naveen Sangath’, and T. Subashini. "A Deep Learning Based Multiclass Segregation of E-waste using Hardware Software Co-Simulation." Journal of Physics: Conference Series 1997, no. 1 (2021): 012039. http://dx.doi.org/10.1088/1742-6596/1997/1/012039.

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32

Edwards, M. D., J. Forrest, and A. E. Whelan. "Acceleration of software algorithms using hardware/software co-design techniques." Journal of Systems Architecture 42, no. 9-10 (1997): 697–707. http://dx.doi.org/10.1016/s1383-7621(96)00071-9.

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33

Fummi, Franco, Mirko Loghi, Giovanni Perbellini, and Massimo Poncino. "SystemC co-simulation for core-based embedded systems." Design Automation for Embedded Systems 11, no. 2-3 (2007): 141–66. http://dx.doi.org/10.1007/s10617-007-9006-7.

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34

Wu, Feng Jie, Zhong Hua Guo, and Wen Kai Huang. "Proteus for the Design of the Heat Treatment Process Parameters Control System." Advanced Materials Research 718-720 (July 2013): 1274–78. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.1274.

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The paper introduces Proteus virtual development techniques into the design of the heat treatment process parameter control system, and takes each heat treatment furnace controller unit for example to explain Proteus simulation circuit of hardware and software design methods. And finally, we achieve the soft parallel hardware co-development of the microcontroller system, which can effectively save hardware resources and improve the development efficiency. Simulation results and theoretical analysis prove the correctness and the accuracy of Proteus virtual simulation, having very important significance in the microcontroller virtual development.
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35

Grycel, Jacob, and Patrick Schaumont. "SimpliFI: Hardware Simulation of Embedded Software Fault Attacks." Cryptography 5, no. 2 (2021): 15. http://dx.doi.org/10.3390/cryptography5020015.

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Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities. These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor microarchitecture. We present SimpliFI, a simulation methodology to test fault attacks on embedded software using a hardware simulation of the processor running the software. We explain the purpose and advantage of SimpliFI, describe automation of the simulation framework, and apply SimpliFI on a BRISC-V embedded processor running an AES application.
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36

Panduranga, H. T., Kumar S. K. Naveen, and Kumar H. S. Sharath. "Hardware Software Co-Simulation of the Multiple Image Encryption Technique Using the Xilinx System Generator." Journal of Information Processing Systems 9, no. 3 (2013): 499–510. http://dx.doi.org/10.3745/jips.2013.9.3.499.

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37

Han, Dong, and Gang Li. "Development of smart english classroom system based on FPGA software and hardware co-simulation test." Microprocessors and Microsystems 81 (March 2021): 103774. http://dx.doi.org/10.1016/j.micpro.2020.103774.

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38

Nahvi, M. "Design-oriented DSP courseware-hardware, software, and simulation." IEEE Signal Processing Magazine 9, no. 4 (1992): 30–35. http://dx.doi.org/10.1109/79.157328.

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39

Liu, Jun, Lin Xuan Zhang, and Bing Cui. "Real-Time Semi-Physical Simulation of Industry Design System Based on Virtual Reality Technology." Applied Mechanics and Materials 607 (July 2014): 413–16. http://dx.doi.org/10.4028/www.scientific.net/amm.607.413.

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Research how to realize real-time hardware in the loop (HIL) of industry design system by utilizing a variety of virtual reality (VR) hardware and software. In this paper, it introduces VR and virtual prototyping technology, and then proposes joint control and simulation based on ADAMS / Aircraft, Simulink, Flightgear three software. Moreover, the virtual scene, data gloves and real-time semi-physical simulation are analyzed and researched; finally as an example, build a real-time semi-physical simulation platform of the landing gear system for multi-wheel and multi-strut aircraft. The system can do kinematic and dynamic analysis, real-time control by visual prototyping and digital models through real-time data acquisition and co-simulation.
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40

Phanomchoeng, Gridsada, Muhammad Saadi, Pruk Sasithong, Jedsada Tangmongkhonsuk, Sanika K. Wijayasekara, and Lunchakorn Wuttisittikulkij. "Hardware Software Co-Design of a Farming Robot." Engineering Journal 24, no. 1 (2020): 199–208. http://dx.doi.org/10.4186/ej.2020.24.1.199.

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41

Bolsens, I., H. J. De Man, B. Lin, K. Van Rompaey, S. Vercauteren, and D. Verkest. "Hardware/software co-design of digital telecommunication systems." Proceedings of the IEEE 85, no. 3 (1997): 391–418. http://dx.doi.org/10.1109/5.558713.

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42

Krawczyk, Kamil, Paweł Tomaszewicz, and Mariusz Rawski. "Whirlpool SoPC Implementation - Hardware/Software Co-Design Example." International Journal of Electronics and Telecommunications 58, no. 1 (2012): 21–26. http://dx.doi.org/10.2478/v10177-012-0003-9.

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Whirlpool SoPC Implementation - Hardware/Software Co-Design Example The aim of this work was to design a System on Programmable Chip (SoPC), that implements the Whirlpool Hash Function (WHF) algorithm. An assumption of the project was to use an embedded soft-processor NIOS II controlling the whole system, which functionality was extended by a custom logic in order to improve the used algorithm efficiency. This paper presents the Whirlpool Hash Function realized in several SoPC configurations, which differ in implementation complexity and performance.
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43

Faes, Philippe, Peter Bertels, Jan Van Campenhout, and Dirk Stroobandt. "Using method interception for hardware/software co-development." Design Automation for Embedded Systems 13, no. 4 (2009): 223–43. http://dx.doi.org/10.1007/s10617-009-9040-8.

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44

Sheliga, Michael, and Edwin Hsing-Mean Sha. "Hardware/Software co-design with the HMS framework." Journal of VLSI signal processing systems for signal, image and video technology 13, no. 1 (1996): 37–56. http://dx.doi.org/10.1007/bf00930666.

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45

M., Vardhana, and Anil Kumar Bhat. "VLSI Implementation and Software Co-Simulation of Digital Image Watermarking with Increased Security." International Journal of Sensors, Wireless Communications and Control 10, no. 4 (2020): 634–38. http://dx.doi.org/10.2174/2210327909666190319150314.

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Background: Security is one of the fundamental and essential factors, which has to be addressed in the field of communication. Communication refers to the exchange of useful information between two or more nodes. Sometimes it is required to exchange some of the confidential information such as a company’s logo, which needs to be hidden from the third person. The data that is being exchanged between these nodes has to be kept confidential and secured from unintended users. The three fundamental components of security are confidentiality, integrity and authentication. The data that is being exchanged has to be confidential, and only the authorized party should have access to the information that is being exchanged. One of the key methods for securing the data is encryption. Objective: The main objective of this paper was to address the problem of data hiding and security in communication systems. There is a need for having hardware resources for having high speed data security and protection. Methods: In this paper, we implemented image watermarking using LSB technique to hide a secret image, and employed encryption using Advanced Encryption Standard, to enhance the security of the image. An image is a two dimensional signal, with each pixel value representing the intensity level. The secure transmission of the image along the channel is a challenging task, because of the reason that, any individual can access it, if no security measures are taken. Conclusion: An efficient method of digital watermarking has been implemented with increased security and performance parameters are presented. Results: In this paper, hardware realization of image watermarking/encryption and dewatermarking/ decryption is implemented using Very Large Scale Integration. The design is verified by means of co-simulation using MATLAB and Xilinx. The paper also presents the performance parameters of the design, with respect to speed, area and power.
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46

Simard, Stéphane, Rachid Beguenane, and Jean-Gabriel Mailloux. "Performance Evaluation of Rotor Flux-Oriented Control on FPGA for Advanced AC Drives." Journal of Robotics and Mechatronics 21, no. 1 (2009): 113–20. http://dx.doi.org/10.20965/jrm.2009.p0113.

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Hardware implementation of mechatronic systems become more and more feasible with the constant development of simulation software tools and more performing computer hardware. The work presented here explains the use of Matlab/Simulink and Xilinx System Generator tools and FPGA hardware in designing, simulating and evaluating control laws for mechatronic systems. Particularly, this paper reports improved results for FPGA implementation and hardware/software co-simulation of a rotor flux-oriented control loop for three-phase AC induction motors. On FPGA, the computation time achieved for the complete control loop proves to be short enough that many enhancements proposed in theory become possible, including the use of neural networks, matrix calculations, on-line monitoring, advanced control of PWM inverter-fed AC machines, and multiple hybrid controls, without affecting system performance or sacrificing precision.
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47

Yang, Shufan, and Zheqi Yu. "A Highly Integrated Hardware/Software Co-Design and Co-Verification Platform." IEEE Design & Test 36, no. 1 (2019): 23–30. http://dx.doi.org/10.1109/mdat.2018.2841029.

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48

., Aniket A. Ingle. "HARDWARE SOFTWARE CO-SIMULATION OF EDGE DETECTION FOR IMAGE PROCESSING SYSTEM USING DELAY BLOCK IN XSG." International Journal of Research in Engineering and Technology 03, no. 05 (2014): 549–53. http://dx.doi.org/10.15623/ijret.2014.0305101.

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49

Al-Haija, Qasem Abu, Hanan Al-Mubarak, and Abdulla Al-Humam. "Hardware Design and Software Simulation for Four Classical Cryptosystems." Procedia Computer Science 21 (2013): 500–505. http://dx.doi.org/10.1016/j.procs.2013.09.069.

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50

Olukotun, K. A., R. Helaihel, J. Levitt, and R. Ramirez. "A software-hardware cosynthesis approach to digital system simulation." IEEE Micro 14, no. 4 (1994): 48–58. http://dx.doi.org/10.1109/40.296157.

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